1 //===- README_ALTIVEC.txt - Notes for improving Altivec code gen ----------===//
3 Implement PPCInstrInfo::isLoadFromStackSlot/isStoreToStackSlot for vector
4 registers, to generate better spill code.
6 //===----------------------------------------------------------------------===//
8 Altivec support. The first should be a single lvx from the constant pool, the
9 second should be a xor/stvx:
12 int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 1, 1, 1, 1, 1 };
18 int x[8] __attribute__((aligned(128)));
19 memset (x, 0, sizeof (x));
23 //===----------------------------------------------------------------------===//
25 Altivec: Codegen'ing MUL with vector FMADD should add -0.0, not 0.0:
26 http://gcc.gnu.org/bugzilla/show_bug.cgi?id=8763
28 When -ffast-math is on, we can use 0.0.
30 //===----------------------------------------------------------------------===//
34 v4f32 Vector2 = { Vector.X, Vector.X, Vector.X, Vector.X };
36 Since we know that "Vector" is 16-byte aligned and we know the element offset
37 of ".X", we should change the load into a lve*x instruction, instead of doing
38 a load/store/lve*x sequence.
40 //===----------------------------------------------------------------------===//
42 There are a wide range of vector constants we can generate with combinations of
43 altivec instructions. Examples
44 GCC does: "t=vsplti*, r = t+t" for constants it can't generate with one vsplti
46 -0.0 (sign bit): vspltisw v0,-1 / vslw v0,v0,v0
48 //===----------------------------------------------------------------------===//
57 vsel (some aliases only accessible using builtins)
59 //===----------------------------------------------------------------------===//
61 FABS/FNEG can be codegen'd with the appropriate and/xor of -0.0.
63 //===----------------------------------------------------------------------===//
65 Codegen the constant here with something better than a constant pool load.
67 void %test_f(<4 x float>* %P, <4 x float>* %Q, float %X) {
68 %tmp = load <4 x float>* %Q
69 %tmp = cast <4 x float> %tmp to <4 x int>
70 %tmp1 = and <4 x int> %tmp, < int 2147483647, int 2147483647, int 2147483647, int 2147483647 >
71 %tmp2 = cast <4 x int> %tmp1 to <4 x float>
72 store <4 x float> %tmp2, <4 x float>* %P
76 //===----------------------------------------------------------------------===//
78 For functions that use altivec AND have calls, we are VRSAVE'ing all call
81 //===----------------------------------------------------------------------===//
83 VSPLTW and friends are expanded by the FE into insert/extract element ops. Make
84 sure that the dag combiner puts them back together in the appropriate
85 vector_shuffle node and that this gets pattern matched appropriately.
87 //===----------------------------------------------------------------------===//
89 Implement passing/returning vectors by value.
91 //===----------------------------------------------------------------------===//
93 GCC apparently tries to codegen { C1, C2, Variable, C3 } as a constant pool load
94 of C1/C2/C3, then a load and vperm of Variable.
96 //===----------------------------------------------------------------------===//
98 We currently codegen SCALAR_TO_VECTOR as a store of the scalar to a 16-byte
99 aligned stack slot, followed by a lve*x/vperm. We should probably just store it
100 to a scalar stack slot, then use lvsl/vperm to load it. If the value is already
101 in memory, this is a huge win.
103 //===----------------------------------------------------------------------===//
105 Do not generate the MFCR/RLWINM sequence for predicate compares when the
106 predicate compare is used immediately by a branch. Just branch on the right
109 //===----------------------------------------------------------------------===//
111 SROA should turn "vector unions" into the appropriate insert/extract element
114 //===----------------------------------------------------------------------===//
116 We need an LLVM 'shuffle' instruction, that corresponds to the VECTOR_SHUFFLE
119 //===----------------------------------------------------------------------===//
121 We need a way to teach tblgen that some operands of an intrinsic are required to
122 be constants. The verifier should enforce this constraint.
124 //===----------------------------------------------------------------------===//
126 Instead of writting a pattern for type-agnostic operations (e.g. gen-zero, load,
127 store, and, ...) in every supported type, make legalize do the work. We should
128 have a canonical type that we want operations changed to (e.g. v4i32 for
129 build_vector) and legalize should change non-identical types to thse. This is
130 similar to what it does for operations that are only supported in some types,
131 e.g. x86 cmov (not supported on bytes).
133 This would fix two problems:
134 1. Writing patterns multiple times.
135 2. Identical operations in different types are not getting CSE'd (e.g.
136 { 0U, 0U, 0U, 0U } and {0.0, 0.0, 0.0, 0.0}.
138 //===----------------------------------------------------------------------===//
140 Instcombine llvm.ppc.altivec.vperm with an immediate into a shuffle operation.
142 //===----------------------------------------------------------------------===//
144 Handle VECTOR_SHUFFLE nodes with the appropriate shuffle mask with vsldoi,
147 //===----------------------------------------------------------------------===//
149 Implement multiply for vector integer types, to avoid the horrible scalarized
150 code produced by legalize.
152 void test(vector int *X, vector int *Y) {
156 //===----------------------------------------------------------------------===//