1 //===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
14 #include "llvm/Support/TargetRegistry.h"
15 #include "llvm/Target/TargetMachine.h"
19 class AMDGPUInstrPrinter;
20 class AMDGPUTargetMachine;
28 FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
29 FunctionPass *createR600TextureIntrinsicsReplacer();
30 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
31 FunctionPass *createR600EmitClauseMarkers();
32 FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
33 FunctionPass *createR600Packetizer(TargetMachine &tm);
34 FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
35 FunctionPass *createAMDGPUCFGStructurizerPass();
38 FunctionPass *createSITypeRewriter();
39 FunctionPass *createSIAnnotateControlFlowPass();
40 FunctionPass *createSILowerI1CopiesPass();
41 FunctionPass *createSILowerControlFlowPass(TargetMachine &tm);
42 FunctionPass *createSIFixSGPRCopiesPass(TargetMachine &tm);
43 FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
44 FunctionPass *createSIInsertWaits(TargetMachine &tm);
46 void initializeSILowerI1CopiesPass(PassRegistry &);
47 extern char &SILowerI1CopiesID;
49 // Passes common to R600 and SI
50 Pass *createAMDGPUStructurizeCFGPass();
51 FunctionPass *createAMDGPUConvertToISAPass(TargetMachine &tm);
52 FunctionPass *createAMDGPUISelDag(TargetMachine &tm);
54 /// \brief Creates an AMDGPU-specific Target Transformation Info pass.
56 createAMDGPUTargetTransformInfoPass(const AMDGPUTargetMachine *TM);
58 extern Target TheAMDGPUTarget;
60 } // End namespace llvm
62 namespace ShaderType {
71 /// OpenCL uses address spaces to differentiate between
72 /// various memory regions on the hardware. On the CPU
73 /// all of the address spaces point to the same memory,
74 /// however on the GPU, each address space points to
75 /// a separate piece of memory that is unique from other
79 PRIVATE_ADDRESS = 0, ///< Address space for private memory.
80 GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
81 CONSTANT_ADDRESS = 2, ///< Address space for constant memory
82 LOCAL_ADDRESS = 3, ///< Address space for local memory.
83 REGION_ADDRESS = 4, ///< Address space for region memory.
84 ADDRESS_NONE = 5, ///< Address space for unknown memory.
85 PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0)
86 PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1)
88 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this
89 // order to be able to dynamically index a constant buffer, for example:
91 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
93 CONSTANT_BUFFER_0 = 8,
94 CONSTANT_BUFFER_1 = 9,
95 CONSTANT_BUFFER_2 = 10,
96 CONSTANT_BUFFER_3 = 11,
97 CONSTANT_BUFFER_4 = 12,
98 CONSTANT_BUFFER_5 = 13,
99 CONSTANT_BUFFER_6 = 14,
100 CONSTANT_BUFFER_7 = 15,
101 CONSTANT_BUFFER_8 = 16,
102 CONSTANT_BUFFER_9 = 17,
103 CONSTANT_BUFFER_10 = 18,
104 CONSTANT_BUFFER_11 = 19,
105 CONSTANT_BUFFER_12 = 20,
106 CONSTANT_BUFFER_13 = 21,
107 CONSTANT_BUFFER_14 = 22,
108 CONSTANT_BUFFER_15 = 23,
112 } // namespace AMDGPUAS