1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
10 // Include AMDIL TD files
11 include "AMDILBase.td"
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
19 def FeatureDumpCode : SubtargetFeature <"DumpCode",
22 "Dump MachineInstrs in the CodeEmitter">;
26 def FeatureFP64 : SubtargetFeature<"fp64",
29 "Enable 64bit double precision operations">;
31 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
34 "Specify if 64bit addressing should be used.">;
36 def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
39 "Specify if 64bit sized pointers with 32bit addressing should be used.">;
41 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
44 "Older version of ALU instructions encoding.">;
46 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
49 "Specify use of dedicated vertex cache.">;
51 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
56 class SubtargetFeatureFetchLimit <string Value> :
57 SubtargetFeature <"fetch"#Value,
60 "Limit the maximum number of fetches in a clause to "#Value>;
62 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
63 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
65 class SubtargetFeatureGeneration <string Value,
66 list<SubtargetFeature> Implies> :
67 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
68 Value#" GPU generation", Implies>;
70 def FeatureR600 : SubtargetFeatureGeneration<"R600",
71 [FeatureR600ALUInst, FeatureFetchLimit8]>;
73 def FeatureR700 : SubtargetFeatureGeneration<"R700",
74 [FeatureFetchLimit16]>;
76 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
77 [FeatureFetchLimit16]>;
79 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
80 [FeatureFetchLimit16]>;
82 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
83 [Feature64BitPtr, FeatureFP64]>;
85 //===----------------------------------------------------------------------===//
87 def AMDGPUInstrInfo : InstrInfo {
88 let guessInstructionProperties = 1;
91 //===----------------------------------------------------------------------===//
92 // Declare the target which we are implementing
93 //===----------------------------------------------------------------------===//
94 def AMDGPUAsmWriter : AsmWriter {
95 string AsmWriterClassName = "InstPrinter";
97 bit isMCAsmWriter = 1;
100 def AMDGPU : Target {
101 // Pull in Instruction Info:
102 let InstructionSet = AMDGPUInstrInfo;
103 let AssemblyWriters = [AMDGPUAsmWriter];
106 // Include AMDGPU TD files
107 include "R600Schedule.td"
108 include "SISchedule.td"
109 include "Processors.td"
110 include "AMDGPUInstrInfo.td"
111 include "AMDGPUIntrinsics.td"
112 include "AMDGPURegisterInfo.td"
113 include "AMDGPUInstructions.td"
114 include "AMDGPUCallingConv.td"