1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
10 include "llvm/Target/Target.td"
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
21 "Dump MachineInstrs in the CodeEmitter">;
23 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
24 "EnableIRStructurizer",
26 "Disable IR Structurizer">;
28 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
29 "EnablePromoteAlloca",
31 "Enable promote alloca pass">;
35 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
38 "Disable the if conversion pass">;
40 def FeatureFP64 : SubtargetFeature<"fp64",
43 "Enable double precision operations">;
45 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
48 "Enable double precision denormal handling",
51 // Some instructions do not support denormals despite this flag. Using
52 // fp32 denormals also causes instructions to run at the double
53 // precision rate for the device.
54 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
57 "Enable single precision denormal handling">;
59 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
62 "Specify if 64-bit addressing should be used">;
64 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
67 "Older version of ALU instructions encoding">;
69 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
72 "Specify use of dedicated vertex cache">;
74 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
79 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
82 "GPU has CF_ALU bug">;
84 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
87 "Support flat address space">;
89 class SubtargetFeatureFetchLimit <string Value> :
90 SubtargetFeature <"fetch"#Value,
93 "Limit the maximum number of fetches in a clause to "#Value>;
95 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
96 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
98 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
99 "wavefrontsize"#Value,
101 !cast<string>(Value),
102 "The number of threads per wavefront">;
104 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
105 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
106 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
108 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
109 "localmemorysize"#Value,
111 !cast<string>(Value),
112 "The size of local memory in bytes">;
114 class SubtargetFeatureGeneration <string Value,
115 list<SubtargetFeature> Implies> :
116 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
117 Value#" GPU generation", Implies>;
119 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
120 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
121 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
123 def FeatureR600 : SubtargetFeatureGeneration<"R600",
124 [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
126 def FeatureR700 : SubtargetFeatureGeneration<"R700",
127 [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
129 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
130 [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
132 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
133 [FeatureFetchLimit16, FeatureWavefrontSize64,
134 FeatureLocalMemorySize32768]
137 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
138 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
139 FeatureWavefrontSize64]>;
141 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
142 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
143 FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
144 //===----------------------------------------------------------------------===//
146 def AMDGPUInstrInfo : InstrInfo {
147 let guessInstructionProperties = 1;
150 def AMDGPU : Target {
151 // Pull in Instruction Info:
152 let InstructionSet = AMDGPUInstrInfo;
155 // Dummy Instruction itineraries for pseudo instructions
156 def ALU_NULL : FuncUnit;
157 def NullALU : InstrItinClass;
159 //===----------------------------------------------------------------------===//
160 // Predicate helper class
161 //===----------------------------------------------------------------------===//
163 class PredicateControl {
164 Predicate SubtargetPredicate;
165 list<Predicate> OtherPredicates = [];
166 list<Predicate> Predicates = !listconcat([SubtargetPredicate],
170 // Include AMDGPU TD files
171 include "R600Schedule.td"
172 include "SISchedule.td"
173 include "Processors.td"
174 include "AMDGPUInstrInfo.td"
175 include "AMDGPUIntrinsics.td"
176 include "AMDGPURegisterInfo.td"
177 include "AMDGPUInstructions.td"
178 include "AMDGPUCallingConv.td"