lib/Target/R600/AMDGPU.td

   1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9
  10 include "llvm/Target/Target.td"
  11
  12 //===----------------------------------------------------------------------===//
  13 // Subtarget Features
  14 //===----------------------------------------------------------------------===//
  15
  16 // Debugging Features
  17
  18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
  19         "DumpCode",
  20         "true",
  21         "Dump MachineInstrs in the CodeEmitter">;
  22
  23 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
  24         "EnableIRStructurizer",
  25         "false",
  26         "Disable IR Structurizer">;
  27
  28 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
  29         "EnablePromoteAlloca",
  30         "true",
  31         "Enable promote alloca pass">;
  32
  33 // Target features
  34
  35 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
  36         "EnableIfCvt",
  37         "false",
  38         "Disable the if conversion pass">;
  39
  40 def FeatureFP64 : SubtargetFeature<"fp64",
  41         "FP64",
  42         "true",
  43         "Enable double precision operations">;
  44
  45 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
  46         "FP64Denormals",
  47         "true",
  48         "Enable double precision denormal handling",
  49         [FeatureFP64]>;
  50
  51 // Some instructions do not support denormals despite this flag. Using
  52 // fp32 denormals also causes instructions to run at the double
  53 // precision rate for the device.
  54 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
  55         "FP32Denormals",
  56         "true",
  57         "Enable single precision denormal handling">;
  58
  59 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
  60         "Is64bit",
  61         "true",
  62         "Specify if 64-bit addressing should be used">;
  63
  64 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
  65         "R600ALUInst",
  66         "false",
  67         "Older version of ALU instructions encoding">;
  68
  69 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
  70         "HasVertexCache",
  71         "true",
  72         "Specify use of dedicated vertex cache">;
  73
  74 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
  75         "CaymanISA",
  76         "true",
  77         "Use Cayman ISA">;
  78
  79 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
  80         "CFALUBug",
  81         "true",
  82         "GPU has CF_ALU bug">;
  83
  84 // XXX - This should probably be removed once enabled by default
  85 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
  86         "EnableLoadStoreOpt",
  87         "true",
  88         "Enable SI load/store optimizer pass">;
  89
  90 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
  91         "FlatAddressSpace",
  92         "true",
  93         "Support flat address space">;
  94
  95 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
  96         "EnableVGPRSpilling",
  97         "true",
  98         "Enable spilling of VGPRs to scratch memory">;
  99
 100 class SubtargetFeatureFetchLimit <string Value> :
 101                           SubtargetFeature <"fetch"#Value,
 102         "TexVTXClauseSize",
 103         Value,
 104         "Limit the maximum number of fetches in a clause to "#Value>;
 105
 106 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
 107 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
 108
 109 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
 110         "wavefrontsize"#Value,
 111         "WavefrontSize",
 112         !cast<string>(Value),
 113         "The number of threads per wavefront">;
 114
 115 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
 116 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
 117 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
 118
 119 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
 120         "localmemorysize"#Value,
 121         "LocalMemorySize",
 122         !cast<string>(Value),
 123         "The size of local memory in bytes">;
 124
 125 class SubtargetFeatureGeneration <string Value,
 126                                   list<SubtargetFeature> Implies> :
 127         SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
 128                           Value#" GPU generation", Implies>;
 129
 130 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
 131 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
 132 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
 133
 134 def FeatureR600 : SubtargetFeatureGeneration<"R600",
 135         [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
 136
 137 def FeatureR700 : SubtargetFeatureGeneration<"R700",
 138         [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
 139
 140 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
 141         [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
 142
 143 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
 144         [FeatureFetchLimit16, FeatureWavefrontSize64,
 145          FeatureLocalMemorySize32768]
 146 >;
 147
 148 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
 149         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
 150          FeatureWavefrontSize64]>;
 151
 152 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
 153         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
 154          FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
 155
 156 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
 157         [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
 158          FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
 159
 160 //===----------------------------------------------------------------------===//
 161
 162 def AMDGPUInstrInfo : InstrInfo {
 163   let guessInstructionProperties = 1;
 164 }
 165
 166 def AMDGPUAsmParser : AsmParser {
 167   // Some of the R600 registers have the same name, so this crashes.
 168   // For example T0_XYZW and T0_XY both have the asm name T0.
 169   let ShouldEmitMatchRegisterName = 0;
 170 }
 171
 172 def AMDGPU : Target {
 173   // Pull in Instruction Info:
 174   let InstructionSet = AMDGPUInstrInfo;
 175   let AssemblyParsers = [AMDGPUAsmParser];
 176 }
 177
 178 // Dummy Instruction itineraries for pseudo instructions
 179 def ALU_NULL : FuncUnit;
 180 def NullALU : InstrItinClass;
 181
 182 //===----------------------------------------------------------------------===//
 183 // Predicate helper class
 184 //===----------------------------------------------------------------------===//
 185
 186 class PredicateControl {
 187   Predicate SubtargetPredicate;
 188   list<Predicate> OtherPredicates = [];
 189   list<Predicate> Predicates = !listconcat([SubtargetPredicate],
 190                                             OtherPredicates);
 191 }
 192
 193 // Include AMDGPU TD files
 194 include "R600Schedule.td"
 195 include "SISchedule.td"
 196 include "Processors.td"
 197 include "AMDGPUInstrInfo.td"
 198 include "AMDGPUIntrinsics.td"
 199 include "AMDGPURegisterInfo.td"
 200 include "AMDGPUInstructions.td"
 201 include "AMDGPUCallingConv.td"