1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
10 include "llvm/Target/Target.td"
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
21 "Dump MachineInstrs in the CodeEmitter">;
23 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
24 "EnableIRStructurizer",
26 "Disable IR Structurizer">;
28 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
29 "EnablePromoteAlloca",
31 "Enable promote alloca pass">;
35 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
38 "Disable the if conversion pass">;
40 def FeatureFP64 : SubtargetFeature<"fp64",
43 "Enable double precision operations">;
45 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
48 "Enable double precision denormal handling",
51 // Some instructions do not support denormals despite this flag. Using
52 // fp32 denormals also causes instructions to run at the double
53 // precision rate for the device.
54 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
57 "Enable single precision denormal handling">;
59 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
62 "Specify if 64-bit addressing should be used">;
64 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
67 "Older version of ALU instructions encoding">;
69 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
72 "Specify use of dedicated vertex cache">;
74 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
79 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
82 "GPU has CF_ALU bug">;
84 // XXX - This should probably be removed once enabled by default
85 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
88 "Enable SI load/store optimizer pass">;
90 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
93 "Support flat address space">;
95 def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
98 "Enable spilling of VGPRs to scratch memory">;
100 class SubtargetFeatureFetchLimit <string Value> :
101 SubtargetFeature <"fetch"#Value,
104 "Limit the maximum number of fetches in a clause to "#Value>;
106 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
107 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
109 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
110 "wavefrontsize"#Value,
112 !cast<string>(Value),
113 "The number of threads per wavefront">;
115 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
116 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
117 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
119 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
120 "localmemorysize"#Value,
122 !cast<string>(Value),
123 "The size of local memory in bytes">;
125 class SubtargetFeatureGeneration <string Value,
126 list<SubtargetFeature> Implies> :
127 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
128 Value#" GPU generation", Implies>;
130 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
131 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
132 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
134 def FeatureR600 : SubtargetFeatureGeneration<"R600",
135 [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
137 def FeatureR700 : SubtargetFeatureGeneration<"R700",
138 [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
140 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
141 [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
143 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
144 [FeatureFetchLimit16, FeatureWavefrontSize64,
145 FeatureLocalMemorySize32768]
148 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
149 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
150 FeatureWavefrontSize64]>;
152 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
153 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
154 FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
156 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
157 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
158 FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
160 //===----------------------------------------------------------------------===//
162 def AMDGPUInstrInfo : InstrInfo {
163 let guessInstructionProperties = 1;
166 def AMDGPUAsmParser : AsmParser {
167 // Some of the R600 registers have the same name, so this crashes.
168 // For example T0_XYZW and T0_XY both have the asm name T0.
169 let ShouldEmitMatchRegisterName = 0;
172 def AMDGPU : Target {
173 // Pull in Instruction Info:
174 let InstructionSet = AMDGPUInstrInfo;
175 let AssemblyParsers = [AMDGPUAsmParser];
178 // Dummy Instruction itineraries for pseudo instructions
179 def ALU_NULL : FuncUnit;
180 def NullALU : InstrItinClass;
182 //===----------------------------------------------------------------------===//
183 // Predicate helper class
184 //===----------------------------------------------------------------------===//
186 class PredicateControl {
187 Predicate SubtargetPredicate;
188 list<Predicate> OtherPredicates = [];
189 list<Predicate> Predicates = !listconcat([SubtargetPredicate],
193 // Include AMDGPU TD files
194 include "R600Schedule.td"
195 include "SISchedule.td"
196 include "Processors.td"
197 include "AMDGPUInstrInfo.td"
198 include "AMDGPUIntrinsics.td"
199 include "AMDGPURegisterInfo.td"
200 include "AMDGPUInstructions.td"
201 include "AMDGPUCallingConv.td"