1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
10 include "llvm/Target/Target.td"
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
21 "Dump MachineInstrs in the CodeEmitter">;
23 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
24 "EnableIRStructurizer",
26 "Disable IR Structurizer">;
28 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
29 "EnablePromoteAlloca",
31 "Enable promote alloca pass">;
35 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
38 "Disable the if conversion pass">;
40 def FeatureFP64 : SubtargetFeature<"fp64",
43 "Enable double precision operations">;
45 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
48 "Enable double precision denormal handling",
51 // Some instructions do not support denormals despite this flag. Using
52 // fp32 denormals also causes instructions to run at the double
53 // precision rate for the device.
54 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
57 "Enable single precision denormal handling">;
59 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
62 "Specify if 64-bit addressing should be used">;
64 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
67 "Older version of ALU instructions encoding">;
69 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
72 "Specify use of dedicated vertex cache">;
74 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
79 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
82 "GPU has CF_ALU bug">;
84 class SubtargetFeatureFetchLimit <string Value> :
85 SubtargetFeature <"fetch"#Value,
88 "Limit the maximum number of fetches in a clause to "#Value>;
90 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
91 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
93 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
94 "wavefrontsize"#Value,
97 "The number of threads per wavefront">;
99 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
100 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
101 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
103 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
104 "localmemorysize"#Value,
106 !cast<string>(Value),
107 "The size of local memory in bytes">;
109 class SubtargetFeatureGeneration <string Value,
110 list<SubtargetFeature> Implies> :
111 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
112 Value#" GPU generation", Implies>;
114 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
115 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
116 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
118 def FeatureR600 : SubtargetFeatureGeneration<"R600",
119 [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
121 def FeatureR700 : SubtargetFeatureGeneration<"R700",
122 [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
124 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
125 [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
127 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
128 [FeatureFetchLimit16, FeatureWavefrontSize64,
129 FeatureLocalMemorySize32768]
132 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
133 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
134 FeatureWavefrontSize64]>;
136 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
137 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
138 FeatureWavefrontSize64]>;
139 //===----------------------------------------------------------------------===//
141 def AMDGPUInstrInfo : InstrInfo {
142 let guessInstructionProperties = 1;
145 def AMDGPU : Target {
146 // Pull in Instruction Info:
147 let InstructionSet = AMDGPUInstrInfo;
150 // Dummy Instruction itineraries for pseudo instructions
151 def ALU_NULL : FuncUnit;
152 def NullALU : InstrItinClass;
154 //===----------------------------------------------------------------------===//
155 // Predicate helper class
156 //===----------------------------------------------------------------------===//
158 class PredicateControl {
159 Predicate SubtargetPredicate;
160 list<Predicate> OtherPredicates = [];
161 list<Predicate> Predicates = !listconcat([SubtargetPredicate],
165 // Include AMDGPU TD files
166 include "R600Schedule.td"
167 include "SISchedule.td"
168 include "Processors.td"
169 include "AMDGPUInstrInfo.td"
170 include "AMDGPUIntrinsics.td"
171 include "AMDGPURegisterInfo.td"
172 include "AMDGPUInstructions.td"
173 include "AMDGPUCallingConv.td"