1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
10 include "llvm/Target/Target.td"
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
21 "Dump MachineInstrs in the CodeEmitter">;
23 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
24 "EnableIRStructurizer",
26 "Disable IR Structurizer">;
28 def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
29 "EnablePromoteAlloca",
31 "Enable promote alloca pass">;
35 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
38 "Disable the if conversion pass">;
40 def FeatureFP64 : SubtargetFeature<"fp64",
43 "Enable double precision operations">;
45 def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
48 "Enable double precision denormal handling",
51 // Some instructions do not support denormals despite this flag. Using
52 // fp32 denormals also causes instructions to run at the double
53 // precision rate for the device.
54 def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
57 "Enable single precision denormal handling">;
59 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
62 "Specify if 64-bit addressing should be used">;
64 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
67 "Older version of ALU instructions encoding">;
69 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
72 "Specify use of dedicated vertex cache">;
74 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
79 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
82 "GPU has CF_ALU bug">;
84 // XXX - This should probably be removed once enabled by default
85 def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
88 "Enable SI load/store optimizer pass">;
90 def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
93 "Support flat address space">;
95 class SubtargetFeatureFetchLimit <string Value> :
96 SubtargetFeature <"fetch"#Value,
99 "Limit the maximum number of fetches in a clause to "#Value>;
101 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
102 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
104 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
105 "wavefrontsize"#Value,
107 !cast<string>(Value),
108 "The number of threads per wavefront">;
110 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
111 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
112 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
114 class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
115 "localmemorysize"#Value,
117 !cast<string>(Value),
118 "The size of local memory in bytes">;
120 class SubtargetFeatureGeneration <string Value,
121 list<SubtargetFeature> Implies> :
122 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
123 Value#" GPU generation", Implies>;
125 def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
126 def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
127 def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
129 def FeatureR600 : SubtargetFeatureGeneration<"R600",
130 [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
132 def FeatureR700 : SubtargetFeatureGeneration<"R700",
133 [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
135 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
136 [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
138 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
139 [FeatureFetchLimit16, FeatureWavefrontSize64,
140 FeatureLocalMemorySize32768]
143 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
144 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
145 FeatureWavefrontSize64]>;
147 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
148 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
149 FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
151 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
152 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
153 FeatureWavefrontSize64, FeatureFlatAddressSpace]>;
155 //===----------------------------------------------------------------------===//
157 def AMDGPUInstrInfo : InstrInfo {
158 let guessInstructionProperties = 1;
161 def AMDGPUAsmParser : AsmParser {
162 // Some of the R600 registers have the same name, so this crashes.
163 // For example T0_XYZW and T0_XY both have the asm name T0.
164 let ShouldEmitMatchRegisterName = 0;
167 def AMDGPU : Target {
168 // Pull in Instruction Info:
169 let InstructionSet = AMDGPUInstrInfo;
170 let AssemblyParsers = [AMDGPUAsmParser];
173 // Dummy Instruction itineraries for pseudo instructions
174 def ALU_NULL : FuncUnit;
175 def NullALU : InstrItinClass;
177 //===----------------------------------------------------------------------===//
178 // Predicate helper class
179 //===----------------------------------------------------------------------===//
181 class PredicateControl {
182 Predicate SubtargetPredicate;
183 list<Predicate> OtherPredicates = [];
184 list<Predicate> Predicates = !listconcat([SubtargetPredicate],
188 // Include AMDGPU TD files
189 include "R600Schedule.td"
190 include "SISchedule.td"
191 include "Processors.td"
192 include "AMDGPUInstrInfo.td"
193 include "AMDGPUIntrinsics.td"
194 include "AMDGPURegisterInfo.td"
195 include "AMDGPUInstructions.td"
196 include "AMDGPUCallingConv.td"