1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
10 // Include AMDIL TD files
11 include "AMDILBase.td"
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
19 def FeatureDumpCode : SubtargetFeature <"DumpCode",
22 "Dump MachineInstrs in the CodeEmitter">;
24 def FeatureIRStructurizer : SubtargetFeature <"EnableIRStructurizer",
25 "EnableIRStructurizer",
27 "Enable IR Structurizer">;
31 def FeatureFP64 : SubtargetFeature<"fp64",
34 "Enable 64bit double precision operations">;
36 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
39 "Specify if 64bit addressing should be used.">;
41 def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
44 "Specify if 64bit sized pointers with 32bit addressing should be used.">;
46 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
49 "Older version of ALU instructions encoding.">;
51 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
54 "Specify use of dedicated vertex cache.">;
56 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
61 class SubtargetFeatureFetchLimit <string Value> :
62 SubtargetFeature <"fetch"#Value,
65 "Limit the maximum number of fetches in a clause to "#Value>;
67 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
68 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
70 class SubtargetFeatureGeneration <string Value,
71 list<SubtargetFeature> Implies> :
72 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
73 Value#" GPU generation", Implies>;
75 def FeatureR600 : SubtargetFeatureGeneration<"R600",
76 [FeatureR600ALUInst, FeatureFetchLimit8]>;
78 def FeatureR700 : SubtargetFeatureGeneration<"R700",
79 [FeatureFetchLimit16]>;
81 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
82 [FeatureFetchLimit16]>;
84 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
85 [FeatureFetchLimit16]>;
87 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
88 [Feature64BitPtr, FeatureFP64]>;
90 //===----------------------------------------------------------------------===//
92 def AMDGPUInstrInfo : InstrInfo {
93 let guessInstructionProperties = 1;
96 //===----------------------------------------------------------------------===//
97 // Declare the target which we are implementing
98 //===----------------------------------------------------------------------===//
99 def AMDGPUAsmWriter : AsmWriter {
100 string AsmWriterClassName = "InstPrinter";
102 bit isMCAsmWriter = 1;
105 def AMDGPU : Target {
106 // Pull in Instruction Info:
107 let InstructionSet = AMDGPUInstrInfo;
108 let AssemblyWriters = [AMDGPUAsmWriter];
111 // Include AMDGPU TD files
112 include "R600Schedule.td"
113 include "SISchedule.td"
114 include "Processors.td"
115 include "AMDGPUInstrInfo.td"
116 include "AMDGPUIntrinsics.td"
117 include "AMDGPURegisterInfo.td"
118 include "AMDGPUInstructions.td"
119 include "AMDGPUCallingConv.td"