1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
10 // Include AMDIL TD files
11 include "AMDILBase.td"
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
19 def FeatureDumpCode : SubtargetFeature <"DumpCode",
22 "Dump MachineInstrs in the CodeEmitter">;
24 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
25 "EnableIRStructurizer",
27 "Disable IR Structurizer">;
31 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
34 "Disable the if conversion pass">;
36 def FeatureFP64 : SubtargetFeature<"fp64",
39 "Enable 64bit double precision operations">;
41 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
44 "Specify if 64bit addressing should be used.">;
46 def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
49 "Specify if 64bit sized pointers with 32bit addressing should be used.">;
51 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
54 "Older version of ALU instructions encoding.">;
56 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
59 "Specify use of dedicated vertex cache.">;
61 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
66 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
69 "GPU has CF_ALU bug">;
71 class SubtargetFeatureFetchLimit <string Value> :
72 SubtargetFeature <"fetch"#Value,
75 "Limit the maximum number of fetches in a clause to "#Value>;
77 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
78 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
80 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
81 "wavefrontsize"#Value,
84 "The number of threads per wavefront">;
86 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
87 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
88 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
90 class SubtargetFeatureGeneration <string Value,
91 list<SubtargetFeature> Implies> :
92 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
93 Value#" GPU generation", Implies>;
95 def FeatureR600 : SubtargetFeatureGeneration<"R600",
96 [FeatureR600ALUInst, FeatureFetchLimit8]>;
98 def FeatureR700 : SubtargetFeatureGeneration<"R700",
99 [FeatureFetchLimit16]>;
101 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
102 [FeatureFetchLimit16]>;
104 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
105 [FeatureFetchLimit16, FeatureWavefrontSize64]>;
107 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
108 [Feature64BitPtr, FeatureFP64]>;
110 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
111 [Feature64BitPtr, FeatureFP64]>;
112 //===----------------------------------------------------------------------===//
114 def AMDGPUInstrInfo : InstrInfo {
115 let guessInstructionProperties = 1;
118 def AMDGPU : Target {
119 // Pull in Instruction Info:
120 let InstructionSet = AMDGPUInstrInfo;
123 // Include AMDGPU TD files
124 include "R600Schedule.td"
125 include "SISchedule.td"
126 include "Processors.td"
127 include "AMDGPUInstrInfo.td"
128 include "AMDGPUIntrinsics.td"
129 include "AMDGPURegisterInfo.td"
130 include "AMDGPUInstructions.td"
131 include "AMDGPUCallingConv.td"