lib/Target/R600/AMDGPU.td

   1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //==-----------------------------------------------------------------------===//
   9
  10 include "llvm/Target/Target.td"
  11
  12 //===----------------------------------------------------------------------===//
  13 // Subtarget Features
  14 //===----------------------------------------------------------------------===//
  15
  16 // Debugging Features
  17
  18 def FeatureDumpCode : SubtargetFeature <"DumpCode",
  19         "DumpCode",
  20         "true",
  21         "Dump MachineInstrs in the CodeEmitter">;
  22
  23 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
  24         "EnableIRStructurizer",
  25         "false",
  26         "Disable IR Structurizer">;
  27
  28 // Target features
  29
  30 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
  31         "EnableIfCvt",
  32         "false",
  33         "Disable the if conversion pass">;
  34
  35 def FeatureFP64     : SubtargetFeature<"fp64",
  36         "FP64",
  37         "true",
  38         "Enable 64bit double precision operations">;
  39
  40 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
  41         "Is64bit",
  42         "true",
  43         "Specify if 64bit addressing should be used.">;
  44
  45 def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
  46         "Is32on64bit",
  47         "false",
  48         "Specify if 64bit sized pointers with 32bit addressing should be used.">;
  49
  50 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
  51         "R600ALUInst",
  52         "false",
  53         "Older version of ALU instructions encoding.">;
  54
  55 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
  56         "HasVertexCache",
  57         "true",
  58         "Specify use of dedicated vertex cache.">;
  59
  60 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
  61         "CaymanISA",
  62         "true",
  63         "Use Cayman ISA">;
  64
  65 def FeatureCFALUBug : SubtargetFeature<"cfalubug",
  66         "CFALUBug",
  67         "true",
  68         "GPU has CF_ALU bug">;
  69
  70 class SubtargetFeatureFetchLimit <string Value> :
  71                           SubtargetFeature <"fetch"#Value,
  72         "TexVTXClauseSize",
  73         Value,
  74         "Limit the maximum number of fetches in a clause to "#Value>;
  75
  76 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
  77 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
  78
  79 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
  80         "wavefrontsize"#Value,
  81         "WavefrontSize",
  82         !cast<string>(Value),
  83         "The number of threads per wavefront">;
  84
  85 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
  86 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
  87 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
  88
  89 class SubtargetFeatureGeneration <string Value,
  90                                   list<SubtargetFeature> Implies> :
  91         SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
  92                           Value#" GPU generation", Implies>;
  93
  94 def FeatureR600 : SubtargetFeatureGeneration<"R600",
  95         [FeatureR600ALUInst, FeatureFetchLimit8]>;
  96
  97 def FeatureR700 : SubtargetFeatureGeneration<"R700",
  98         [FeatureFetchLimit16]>;
  99
 100 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
 101         [FeatureFetchLimit16]>;
 102
 103 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
 104         [FeatureFetchLimit16, FeatureWavefrontSize64]>;
 105
 106 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
 107         [Feature64BitPtr, FeatureFP64]>;
 108
 109 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
 110         [Feature64BitPtr, FeatureFP64]>;
 111 //===----------------------------------------------------------------------===//
 112
 113 def AMDGPUInstrInfo : InstrInfo {
 114   let guessInstructionProperties = 1;
 115 }
 116
 117 def AMDGPU : Target {
 118   // Pull in Instruction Info:
 119   let InstructionSet = AMDGPUInstrInfo;
 120 }
 121
 122 // Dummy Instruction itineraries for pseudo instructions
 123 def ALU_NULL : FuncUnit;
 124 def NullALU : InstrItinClass;
 125
 126 //===----------------------------------------------------------------------===//
 127 // Predicate helper class
 128 //===----------------------------------------------------------------------===//
 129
 130 class PredicateControl {
 131   Predicate SubtargetPredicate;
 132   list<Predicate> OtherPredicates = [];
 133   list<Predicate> Predicates = !listconcat([SubtargetPredicate],
 134                                             OtherPredicates);
 135 }
 136
 137 // Include AMDGPU TD files
 138 include "R600Schedule.td"
 139 include "SISchedule.td"
 140 include "Processors.td"
 141 include "AMDGPUInstrInfo.td"
 142 include "AMDGPUIntrinsics.td"
 143 include "AMDGPURegisterInfo.td"
 144 include "AMDGPUInstructions.td"
 145 include "AMDGPUCallingConv.td"