1 //===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
10 // Include AMDIL TD files
11 include "AMDILBase.td"
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
19 def FeatureDumpCode : SubtargetFeature <"DumpCode",
22 "Dump MachineInstrs in the CodeEmitter">;
24 def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
25 "EnableIRStructurizer",
27 "Disable IR Structurizer">;
31 def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
34 "Disable the if conversion pass">;
36 def FeatureFP64 : SubtargetFeature<"fp64",
39 "Enable 64bit double precision operations">;
41 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
44 "Specify if 64bit addressing should be used.">;
46 def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
49 "Specify if 64bit sized pointers with 32bit addressing should be used.">;
51 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
54 "Older version of ALU instructions encoding.">;
56 def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
59 "Specify use of dedicated vertex cache.">;
61 def FeatureCaymanISA : SubtargetFeature<"caymanISA",
66 class SubtargetFeatureFetchLimit <string Value> :
67 SubtargetFeature <"fetch"#Value,
70 "Limit the maximum number of fetches in a clause to "#Value>;
72 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
73 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
75 class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
76 "wavefrontsize"#Value,
79 "The number of threads per wavefront">;
81 def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
82 def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
83 def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
85 class SubtargetFeatureGeneration <string Value,
86 list<SubtargetFeature> Implies> :
87 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
88 Value#" GPU generation", Implies>;
90 def FeatureR600 : SubtargetFeatureGeneration<"R600",
91 [FeatureR600ALUInst, FeatureFetchLimit8]>;
93 def FeatureR700 : SubtargetFeatureGeneration<"R700",
94 [FeatureFetchLimit16]>;
96 def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
97 [FeatureFetchLimit16]>;
99 def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
100 [FeatureFetchLimit16, FeatureWavefrontSize64]>;
102 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
103 [Feature64BitPtr, FeatureFP64]>;
105 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
106 [Feature64BitPtr, FeatureFP64]>;
107 //===----------------------------------------------------------------------===//
109 def AMDGPUInstrInfo : InstrInfo {
110 let guessInstructionProperties = 1;
113 def AMDGPU : Target {
114 // Pull in Instruction Info:
115 let InstructionSet = AMDGPUInstrInfo;
118 // Include AMDGPU TD files
119 include "R600Schedule.td"
120 include "SISchedule.td"
121 include "Processors.td"
122 include "AMDGPUInstrInfo.td"
123 include "AMDGPUIntrinsics.td"
124 include "AMDGPURegisterInfo.td"
125 include "AMDGPUInstructions.td"
126 include "AMDGPUCallingConv.td"