lib/Target/R600/AMDGPUAsmPrinter.cpp

   1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 ///
  12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
  13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
  14 /// an MCObjectStreamer it outputs binary code.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 //
  18
  19
  20 #include "AMDGPUAsmPrinter.h"
  21 #include "AMDGPU.h"
  22 #include "AMDGPUSubtarget.h"
  23 #include "R600Defines.h"
  24 #include "R600MachineFunctionInfo.h"
  25 #include "R600RegisterInfo.h"
  26 #include "SIDefines.h"
  27 #include "SIMachineFunctionInfo.h"
  28 #include "SIRegisterInfo.h"
  29 #include "llvm/MC/MCContext.h"
  30 #include "llvm/MC/MCSectionELF.h"
  31 #include "llvm/MC/MCStreamer.h"
  32 #include "llvm/Support/ELF.h"
  33 #include "llvm/Support/MathExtras.h"
  34 #include "llvm/Support/TargetRegistry.h"
  35 #include "llvm/Target/TargetLoweringObjectFile.h"
  36
  37 using namespace llvm;
  38
  39
  40 static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
  41                                               MCStreamer &Streamer) {
  42   return new AMDGPUAsmPrinter(tm, Streamer);
  43 }
  44
  45 extern "C" void LLVMInitializeR600AsmPrinter() {
  46   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
  47 }
  48
  49 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
  50     : AsmPrinter(TM, Streamer) {
  51   DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode();
  52 }
  53
  54 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
  55   SetupMachineFunction(MF);
  56
  57   OutStreamer.emitRawComment(Twine('@') + MF.getName() + Twine(':'));
  58
  59   MCContext &Context = getObjFileLowering().getContext();
  60   const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
  61                                               ELF::SHT_PROGBITS, 0,
  62                                               SectionKind::getReadOnly());
  63   OutStreamer.SwitchSection(ConfigSection);
  64
  65   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
  66   SIProgramInfo KernelInfo;
  67   if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
  68     getSIProgramInfo(KernelInfo, MF);
  69     EmitProgramInfoSI(MF, KernelInfo);
  70   } else {
  71     EmitProgramInfoR600(MF);
  72   }
  73
  74   DisasmLines.clear();
  75   HexLines.clear();
  76   DisasmLineMaxLen = 0;
  77
  78   OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
  79   EmitFunctionBody();
  80
  81   if (isVerbose()) {
  82     const MCSectionELF *CommentSection
  83       = Context.getELFSection(".AMDGPU.csdata",
  84                               ELF::SHT_PROGBITS, 0,
  85                               SectionKind::getReadOnly());
  86     OutStreamer.SwitchSection(CommentSection);
  87
  88     if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
  89       OutStreamer.emitRawComment(" Kernel info:", false);
  90       OutStreamer.emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
  91                                  false);
  92       OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
  93                                  false);
  94       OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
  95                                  false);
  96     } else {
  97       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
  98       OutStreamer.emitRawComment(
  99         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
 100     }
 101   }
 102
 103   if (STM.dumpCode()) {
 104 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 105     MF.dump();
 106 #endif
 107
 108     if (DisasmEnabled) {
 109       OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm",
 110                                                   ELF::SHT_NOTE, 0,
 111                                                   SectionKind::getReadOnly()));
 112
 113       for (size_t i = 0; i < DisasmLines.size(); ++i) {
 114         std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
 115         Comment += " ; " + HexLines[i] + "\n";
 116
 117         OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
 118         OutStreamer.EmitBytes(StringRef(Comment));
 119       }
 120     }
 121   }
 122
 123   return false;
 124 }
 125
 126 void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
 127   unsigned MaxGPR = 0;
 128   bool killPixel = false;
 129   const R600RegisterInfo * RI =
 130                 static_cast<const R600RegisterInfo*>(TM.getRegisterInfo());
 131   R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 132   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 133
 134   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
 135                                                   BB != BB_E; ++BB) {
 136     MachineBasicBlock &MBB = *BB;
 137     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
 138                                                     I != E; ++I) {
 139       MachineInstr &MI = *I;
 140       if (MI.getOpcode() == AMDGPU::KILLGT)
 141         killPixel = true;
 142       unsigned numOperands = MI.getNumOperands();
 143       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 144         MachineOperand & MO = MI.getOperand(op_idx);
 145         if (!MO.isReg())
 146           continue;
 147         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
 148
 149         // Register with value > 127 aren't GPR
 150         if (HWReg > 127)
 151           continue;
 152         MaxGPR = std::max(MaxGPR, HWReg);
 153       }
 154     }
 155   }
 156
 157   unsigned RsrcReg;
 158   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
 159     // Evergreen / Northern Islands
 160     switch (MFI->ShaderType) {
 161     default: // Fall through
 162     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
 163     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
 164     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
 165     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
 166     }
 167   } else {
 168     // R600 / R700
 169     switch (MFI->ShaderType) {
 170     default: // Fall through
 171     case ShaderType::GEOMETRY: // Fall through
 172     case ShaderType::COMPUTE:  // Fall through
 173     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
 174     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
 175     }
 176   }
 177
 178   OutStreamer.EmitIntValue(RsrcReg, 4);
 179   OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
 180                            S_STACK_SIZE(MFI->StackSize), 4);
 181   OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
 182   OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
 183
 184   if (MFI->ShaderType == ShaderType::COMPUTE) {
 185     OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
 186     OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
 187   }
 188 }
 189
 190 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
 191                                         MachineFunction &MF) const {
 192   uint64_t CodeSize = 0;
 193   unsigned MaxSGPR = 0;
 194   unsigned MaxVGPR = 0;
 195   bool VCCUsed = false;
 196   const SIRegisterInfo * RI =
 197                 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
 198
 199   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
 200                                                   BB != BB_E; ++BB) {
 201     MachineBasicBlock &MBB = *BB;
 202     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
 203                                                     I != E; ++I) {
 204       MachineInstr &MI = *I;
 205
 206       // TODO: CodeSize should account for multiple functions.
 207       CodeSize += MI.getDesc().Size;
 208
 209       unsigned numOperands = MI.getNumOperands();
 210       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 211         MachineOperand &MO = MI.getOperand(op_idx);
 212         unsigned width = 0;
 213         bool isSGPR = false;
 214
 215         if (!MO.isReg()) {
 216           continue;
 217         }
 218         unsigned reg = MO.getReg();
 219         if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
 220             reg == AMDGPU::VCC_HI) {
 221           VCCUsed = true;
 222           continue;
 223         }
 224
 225         switch (reg) {
 226         default: break;
 227         case AMDGPU::SCC:
 228         case AMDGPU::EXEC:
 229         case AMDGPU::M0:
 230           continue;
 231         }
 232
 233         if (AMDGPU::SReg_32RegClass.contains(reg)) {
 234           isSGPR = true;
 235           width = 1;
 236         } else if (AMDGPU::VReg_32RegClass.contains(reg)) {
 237           isSGPR = false;
 238           width = 1;
 239         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
 240           isSGPR = true;
 241           width = 2;
 242         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
 243           isSGPR = false;
 244           width = 2;
 245         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
 246           isSGPR = false;
 247           width = 3;
 248         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
 249           isSGPR = true;
 250           width = 4;
 251         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
 252           isSGPR = false;
 253           width = 4;
 254         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
 255           isSGPR = true;
 256           width = 8;
 257         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
 258           isSGPR = false;
 259           width = 8;
 260         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
 261           isSGPR = true;
 262           width = 16;
 263         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
 264           isSGPR = false;
 265           width = 16;
 266         } else {
 267           llvm_unreachable("Unknown register class");
 268         }
 269         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
 270         unsigned maxUsed = hwReg + width - 1;
 271         if (isSGPR) {
 272           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
 273         } else {
 274           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
 275         }
 276       }
 277     }
 278   }
 279
 280   if (VCCUsed)
 281     MaxSGPR += 2;
 282
 283   ProgInfo.CodeLen = CodeSize;
 284   ProgInfo.NumSGPR = MaxSGPR;
 285   ProgInfo.NumVGPR = MaxVGPR;
 286 }
 287
 288 void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF,
 289                                          const SIProgramInfo &KernelInfo) {
 290   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 291
 292   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 293   unsigned RsrcReg;
 294   switch (MFI->ShaderType) {
 295   default: // Fall through
 296   case ShaderType::COMPUTE:  RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break;
 297   case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break;
 298   case ShaderType::PIXEL:    RsrcReg = R_00B028_SPI_SHADER_PGM_RSRC1_PS; break;
 299   case ShaderType::VERTEX:   RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; break;
 300   }
 301
 302   OutStreamer.EmitIntValue(RsrcReg, 4);
 303   OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.NumVGPR / 4) |
 304                            S_00B028_SGPRS(KernelInfo.NumSGPR / 8), 4);
 305
 306   unsigned LDSAlignShift;
 307   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
 308     // LDS is allocated in 64 dword blocks
 309     LDSAlignShift = 8;
 310   } else {
 311     // LDS is allocated in 128 dword blocks
 312     LDSAlignShift = 9;
 313   }
 314   unsigned LDSBlocks =
 315           RoundUpToAlignment(MFI->LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
 316
 317   if (MFI->ShaderType == ShaderType::COMPUTE) {
 318     OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
 319     OutStreamer.EmitIntValue(S_00B84C_LDS_SIZE(LDSBlocks), 4);
 320   }
 321   if (MFI->ShaderType == ShaderType::PIXEL) {
 322     OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
 323     OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(LDSBlocks), 4);
 324     OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
 325     OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
 326   }
 327 }