1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code. When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
16 //===----------------------------------------------------------------------===//
20 #include "AMDGPUAsmPrinter.h"
22 #include "SIMachineFunctionInfo.h"
23 #include "SIRegisterInfo.h"
24 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/Target/TargetLoweringObjectFile.h"
26 #include "llvm/Support/TargetRegistry.h"
31 static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
32 MCStreamer &Streamer) {
33 return new AMDGPUAsmPrinter(tm, Streamer);
36 extern "C" void LLVMInitializeR600AsmPrinter() {
37 TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
40 /// We need to override this function so we can avoid
41 /// the call to EmitFunctionHeader(), which the MCPureStreamer can't handle.
42 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
43 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
45 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
49 SetupMachineFunction(MF);
50 OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
51 if (STM.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
58 void AMDGPUAsmPrinter::EmitProgramInfo(MachineFunction &MF) {
62 const SIRegisterInfo * RI =
63 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
65 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
67 MachineBasicBlock &MBB = *BB;
68 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
70 MachineInstr &MI = *I;
72 unsigned numOperands = MI.getNumOperands();
73 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
74 MachineOperand & MO = MI.getOperand(op_idx);
84 if (reg == AMDGPU::VCC) {
91 case AMDGPU::SI_LITERAL_CONSTANT:
92 case AMDGPU::SREG_LIT_0:
97 if (AMDGPU::SReg_32RegClass.contains(reg)) {
100 } else if (AMDGPU::VReg_32RegClass.contains(reg)) {
103 } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
106 } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
109 } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
112 } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
115 } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
119 assert(!"Unknown register class");
121 hwReg = RI->getEncodingValue(reg);
122 maxUsed = hwReg + width - 1;
124 MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
126 MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
134 SIMachineFunctionInfo * MFI = MF.getInfo<SIMachineFunctionInfo>();
135 OutStreamer.EmitIntValue(MaxSGPR + 1, 4);
136 OutStreamer.EmitIntValue(MaxVGPR + 1, 4);
137 OutStreamer.EmitIntValue(MFI->SPIPSInputAddr, 4);