1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code. When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
16 //===----------------------------------------------------------------------===//
20 #include "AMDGPUAsmPrinter.h"
22 #include "R600Defines.h"
23 #include "R600MachineFunctionInfo.h"
24 #include "R600RegisterInfo.h"
25 #include "SIDefines.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIRegisterInfo.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCSectionELF.h"
30 #include "llvm/MC/MCStreamer.h"
31 #include "llvm/Support/ELF.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
39 static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
40 MCStreamer &Streamer) {
41 return new AMDGPUAsmPrinter(tm, Streamer);
44 extern "C" void LLVMInitializeR600AsmPrinter() {
45 TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
48 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
49 : AsmPrinter(TM, Streamer) {
50 DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode() &&
51 ! Streamer.hasRawTextSupport();
54 /// We need to override this function so we can avoid
55 /// the call to EmitFunctionHeader(), which the MCPureStreamer can't handle.
56 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
57 SetupMachineFunction(MF);
59 if (OutStreamer.hasRawTextSupport()) {
60 OutStreamer.EmitRawText("@" + MF.getName() + ":");
63 MCContext &Context = getObjFileLowering().getContext();
64 const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
66 SectionKind::getReadOnly());
67 OutStreamer.SwitchSection(ConfigSection);
69 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
70 SIProgramInfo KernelInfo;
71 if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
72 findNumUsedRegistersSI(MF, KernelInfo.NumSGPR, KernelInfo.NumVGPR);
73 EmitProgramInfoSI(MF, KernelInfo);
75 EmitProgramInfoR600(MF);
82 OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
85 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
86 const MCSectionELF *CommentSection
87 = Context.getELFSection(".AMDGPU.csdata",
89 SectionKind::getReadOnly());
90 OutStreamer.SwitchSection(CommentSection);
92 OutStreamer.EmitRawText(
93 Twine("; Kernel info:\n") +
94 "; NumSgprs: " + Twine(KernelInfo.NumSGPR) + "\n" +
95 "; NumVgprs: " + Twine(KernelInfo.NumVGPR) + "\n");
99 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
104 OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm",
106 SectionKind::getReadOnly()));
108 for (size_t i = 0; i < DisasmLines.size(); ++i) {
109 std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
110 Comment += " ; " + HexLines[i] + "\n";
112 OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
113 OutStreamer.EmitBytes(StringRef(Comment));
121 void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
123 bool killPixel = false;
124 const R600RegisterInfo * RI =
125 static_cast<const R600RegisterInfo*>(TM.getRegisterInfo());
126 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
127 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
129 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
131 MachineBasicBlock &MBB = *BB;
132 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
134 MachineInstr &MI = *I;
135 if (MI.getOpcode() == AMDGPU::KILLGT)
137 unsigned numOperands = MI.getNumOperands();
138 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
139 MachineOperand & MO = MI.getOperand(op_idx);
142 unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
144 // Register with value > 127 aren't GPR
147 MaxGPR = std::max(MaxGPR, HWReg);
153 if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
154 // Evergreen / Northern Islands
155 switch (MFI->ShaderType) {
156 default: // Fall through
157 case ShaderType::COMPUTE: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
158 case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
159 case ShaderType::PIXEL: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
160 case ShaderType::VERTEX: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
164 switch (MFI->ShaderType) {
165 default: // Fall through
166 case ShaderType::GEOMETRY: // Fall through
167 case ShaderType::COMPUTE: // Fall through
168 case ShaderType::VERTEX: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
169 case ShaderType::PIXEL: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
173 OutStreamer.EmitIntValue(RsrcReg, 4);
174 OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
175 S_STACK_SIZE(MFI->StackSize), 4);
176 OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
177 OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
179 if (MFI->ShaderType == ShaderType::COMPUTE) {
180 OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
181 OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
185 void AMDGPUAsmPrinter::findNumUsedRegistersSI(MachineFunction &MF,
187 unsigned &NumVGPR) const {
188 unsigned MaxSGPR = 0;
189 unsigned MaxVGPR = 0;
190 bool VCCUsed = false;
191 const SIRegisterInfo * RI =
192 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
194 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
196 MachineBasicBlock &MBB = *BB;
197 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
199 MachineInstr &MI = *I;
201 unsigned numOperands = MI.getNumOperands();
202 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
203 MachineOperand &MO = MI.getOperand(op_idx);
213 if (reg == AMDGPU::VCC) {
226 if (AMDGPU::SReg_32RegClass.contains(reg)) {
229 } else if (AMDGPU::VReg_32RegClass.contains(reg)) {
232 } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
235 } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
238 } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
241 } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
244 } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
247 } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
250 } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
253 } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
256 } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
260 llvm_unreachable("Unknown register class");
262 hwReg = RI->getEncodingValue(reg) & 0xff;
263 maxUsed = hwReg + width - 1;
265 MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
267 MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
280 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &Out,
281 MachineFunction &MF) const {
282 findNumUsedRegistersSI(MF, Out.NumSGPR, Out.NumVGPR);
285 void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF,
286 const SIProgramInfo &KernelInfo) {
287 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
289 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
291 switch (MFI->ShaderType) {
292 default: // Fall through
293 case ShaderType::COMPUTE: RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break;
294 case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break;
295 case ShaderType::PIXEL: RsrcReg = R_00B028_SPI_SHADER_PGM_RSRC1_PS; break;
296 case ShaderType::VERTEX: RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; break;
299 OutStreamer.EmitIntValue(RsrcReg, 4);
300 OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.NumVGPR / 4) |
301 S_00B028_SGPRS(KernelInfo.NumSGPR / 8), 4);
303 unsigned LDSAlignShift;
304 if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
305 // LDS is allocated in 64 dword blocks
308 // LDS is allocated in 128 dword blocks
312 RoundUpToAlignment(MFI->LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
314 if (MFI->ShaderType == ShaderType::COMPUTE) {
315 OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
316 OutStreamer.EmitIntValue(S_00B84C_LDS_SIZE(LDSBlocks), 4);
318 if (MFI->ShaderType == ShaderType::PIXEL) {
319 OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
320 OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(LDSBlocks), 4);
321 OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
322 OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);