1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code. When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
16 //===----------------------------------------------------------------------===//
20 #include "AMDGPUAsmPrinter.h"
22 #include "R600Defines.h"
23 #include "R600MachineFunctionInfo.h"
24 #include "R600RegisterInfo.h"
25 #include "SIDefines.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIRegisterInfo.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCSectionELF.h"
30 #include "llvm/MC/MCStreamer.h"
31 #include "llvm/Support/ELF.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
39 static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
40 MCStreamer &Streamer) {
41 return new AMDGPUAsmPrinter(tm, Streamer);
44 extern "C" void LLVMInitializeR600AsmPrinter() {
45 TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
48 /// We need to override this function so we can avoid
49 /// the call to EmitFunctionHeader(), which the MCPureStreamer can't handle.
50 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
51 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
53 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
57 SetupMachineFunction(MF);
58 if (OutStreamer.hasRawTextSupport()) {
59 OutStreamer.EmitRawText("@" + MF.getName() + ":");
62 const MCSectionELF *ConfigSection = getObjFileLowering().getContext()
63 .getELFSection(".AMDGPU.config",
65 SectionKind::getReadOnly());
66 OutStreamer.SwitchSection(ConfigSection);
67 if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
68 EmitProgramInfoSI(MF);
70 EmitProgramInfoR600(MF);
72 OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
77 void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
79 bool killPixel = false;
80 const R600RegisterInfo * RI =
81 static_cast<const R600RegisterInfo*>(TM.getRegisterInfo());
82 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
83 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
85 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
87 MachineBasicBlock &MBB = *BB;
88 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
90 MachineInstr &MI = *I;
91 if (MI.getOpcode() == AMDGPU::KILLGT)
93 unsigned numOperands = MI.getNumOperands();
94 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
95 MachineOperand & MO = MI.getOperand(op_idx);
98 unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
100 // Register with value > 127 aren't GPR
103 MaxGPR = std::max(MaxGPR, HWReg);
109 if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
110 // Evergreen / Northern Islands
111 switch (MFI->ShaderType) {
112 default: // Fall through
113 case ShaderType::COMPUTE: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
114 case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
115 case ShaderType::PIXEL: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
116 case ShaderType::VERTEX: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
120 switch (MFI->ShaderType) {
121 default: // Fall through
122 case ShaderType::GEOMETRY: // Fall through
123 case ShaderType::COMPUTE: // Fall through
124 case ShaderType::VERTEX: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
125 case ShaderType::PIXEL: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
129 OutStreamer.EmitIntValue(RsrcReg, 4);
130 OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
131 S_STACK_SIZE(MFI->StackSize), 4);
132 OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
133 OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
135 if (MFI->ShaderType == ShaderType::COMPUTE) {
136 OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
137 OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
141 void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF) {
142 unsigned MaxSGPR = 0;
143 unsigned MaxVGPR = 0;
144 bool VCCUsed = false;
145 const SIRegisterInfo * RI =
146 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
148 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
150 MachineBasicBlock &MBB = *BB;
151 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
153 MachineInstr &MI = *I;
155 unsigned numOperands = MI.getNumOperands();
156 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
157 MachineOperand & MO = MI.getOperand(op_idx);
167 if (reg == AMDGPU::VCC) {
178 if (AMDGPU::SReg_32RegClass.contains(reg)) {
181 } else if (AMDGPU::VReg_32RegClass.contains(reg)) {
184 } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
187 } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
190 } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
193 } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
196 } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
199 } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
202 } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
205 } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
209 assert(!"Unknown register class");
211 hwReg = RI->getEncodingValue(reg) & 0xff;
212 maxUsed = hwReg + width - 1;
214 MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
216 MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
224 SIMachineFunctionInfo * MFI = MF.getInfo<SIMachineFunctionInfo>();
226 switch (MFI->ShaderType) {
227 default: // Fall through
228 case ShaderType::COMPUTE: RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break;
229 case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break;
230 case ShaderType::PIXEL: RsrcReg = R_00B028_SPI_SHADER_PGM_RSRC1_PS; break;
231 case ShaderType::VERTEX: RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; break;
234 OutStreamer.EmitIntValue(RsrcReg, 4);
235 OutStreamer.EmitIntValue(S_00B028_VGPRS(MaxVGPR / 4) | S_00B028_SGPRS(MaxSGPR / 8), 4);
236 if (MFI->ShaderType == ShaderType::PIXEL) {
237 OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
238 OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);