1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code. When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
16 //===----------------------------------------------------------------------===//
19 #include "AMDGPUAsmPrinter.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600Defines.h"
23 #include "R600MachineFunctionInfo.h"
24 #include "R600RegisterInfo.h"
25 #include "SIDefines.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIRegisterInfo.h"
28 #include "llvm/MC/MCContext.h"
29 #include "llvm/MC/MCSectionELF.h"
30 #include "llvm/MC/MCStreamer.h"
31 #include "llvm/Support/ELF.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
38 // TODO: This should get the default rounding mode from the kernel. We just set
39 // the default here, but this could change if the OpenCL rounding mode pragmas
42 // The denormal mode here should match what is reported by the OpenCL runtime
43 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
44 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
46 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
47 // precision, and leaves single precision to flush all and does not report
48 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
49 // CL_FP_DENORM for both.
51 // FIXME: It seems some instructions do not support single precision denormals
52 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
53 // and sin_f32, cos_f32 on most parts).
55 // We want to use these instructions, and using fp32 denormals also causes
56 // instructions to run at the double precision rate for the device so it's
57 // probably best to just report no single precision denormals.
58 static uint32_t getFPMode(const MachineFunction &F) {
59 const AMDGPUSubtarget& ST = F.getTarget().getSubtarget<AMDGPUSubtarget>();
60 // TODO: Is there any real use for the flush in only / flush out only modes?
62 uint32_t FP32Denormals =
63 ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
65 uint32_t FP64Denormals =
66 ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
68 return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
69 FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
70 FP_DENORM_MODE_SP(FP32Denormals) |
71 FP_DENORM_MODE_DP(FP64Denormals);
74 static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
75 MCStreamer &Streamer) {
76 return new AMDGPUAsmPrinter(tm, Streamer);
79 extern "C" void LLVMInitializeR600AsmPrinter() {
80 TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
83 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
84 : AsmPrinter(TM, Streamer) {
85 DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode();
88 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
89 SetupMachineFunction(MF);
91 OutStreamer.emitRawComment(Twine('@') + MF.getName() + Twine(':'));
93 MCContext &Context = getObjFileLowering().getContext();
94 const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
96 SectionKind::getReadOnly());
97 OutStreamer.SwitchSection(ConfigSection);
99 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
100 SIProgramInfo KernelInfo;
101 if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
102 getSIProgramInfo(KernelInfo, MF);
103 EmitProgramInfoSI(MF, KernelInfo);
105 EmitProgramInfoR600(MF);
110 DisasmLineMaxLen = 0;
112 OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
116 const MCSectionELF *CommentSection
117 = Context.getELFSection(".AMDGPU.csdata",
118 ELF::SHT_PROGBITS, 0,
119 SectionKind::getReadOnly());
120 OutStreamer.SwitchSection(CommentSection);
122 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
123 OutStreamer.emitRawComment(" Kernel info:", false);
124 OutStreamer.emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
126 OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
128 OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
130 OutStreamer.emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
132 OutStreamer.emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
135 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
136 OutStreamer.emitRawComment(
137 Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
141 if (STM.dumpCode()) {
142 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
147 OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm",
149 SectionKind::getReadOnly()));
151 for (size_t i = 0; i < DisasmLines.size(); ++i) {
152 std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
153 Comment += " ; " + HexLines[i] + "\n";
155 OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
156 OutStreamer.EmitBytes(StringRef(Comment));
164 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
166 bool killPixel = false;
167 const R600RegisterInfo *RI
168 = static_cast<const R600RegisterInfo*>(TM.getRegisterInfo());
169 const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
170 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
172 for (const MachineBasicBlock &MBB : MF) {
173 for (const MachineInstr &MI : MBB) {
174 if (MI.getOpcode() == AMDGPU::KILLGT)
176 unsigned numOperands = MI.getNumOperands();
177 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
178 const MachineOperand &MO = MI.getOperand(op_idx);
181 unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
183 // Register with value > 127 aren't GPR
186 MaxGPR = std::max(MaxGPR, HWReg);
192 if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
193 // Evergreen / Northern Islands
194 switch (MFI->getShaderType()) {
195 default: // Fall through
196 case ShaderType::COMPUTE: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
197 case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
198 case ShaderType::PIXEL: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
199 case ShaderType::VERTEX: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
203 switch (MFI->getShaderType()) {
204 default: // Fall through
205 case ShaderType::GEOMETRY: // Fall through
206 case ShaderType::COMPUTE: // Fall through
207 case ShaderType::VERTEX: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
208 case ShaderType::PIXEL: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
212 OutStreamer.EmitIntValue(RsrcReg, 4);
213 OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
214 S_STACK_SIZE(MFI->StackSize), 4);
215 OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
216 OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
218 if (MFI->getShaderType() == ShaderType::COMPUTE) {
219 OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
220 OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
224 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
225 const MachineFunction &MF) const {
226 uint64_t CodeSize = 0;
227 unsigned MaxSGPR = 0;
228 unsigned MaxVGPR = 0;
229 bool VCCUsed = false;
230 const SIRegisterInfo *RI
231 = static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
233 for (const MachineBasicBlock &MBB : MF) {
234 for (const MachineInstr &MI : MBB) {
235 // TODO: CodeSize should account for multiple functions.
236 CodeSize += MI.getDesc().Size;
238 unsigned numOperands = MI.getNumOperands();
239 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
240 const MachineOperand &MO = MI.getOperand(op_idx);
247 unsigned reg = MO.getReg();
248 if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
249 reg == AMDGPU::VCC_HI) {
262 if (AMDGPU::SReg_32RegClass.contains(reg)) {
265 } else if (AMDGPU::VReg_32RegClass.contains(reg)) {
268 } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
271 } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
274 } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
277 } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
280 } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
283 } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
286 } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
289 } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
292 } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
296 llvm_unreachable("Unknown register class");
298 unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
299 unsigned maxUsed = hwReg + width - 1;
301 MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
303 MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
312 ProgInfo.NumVGPR = MaxVGPR;
313 ProgInfo.NumSGPR = MaxSGPR;
315 // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
317 ProgInfo.FloatMode = getFPMode(MF);
319 // XXX: Not quite sure what this does, but sc seems to unset this.
320 ProgInfo.IEEEMode = 0;
322 // Do not clamp NAN to 0.
323 ProgInfo.DX10Clamp = 0;
325 ProgInfo.CodeLen = CodeSize;
328 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
329 const SIProgramInfo &KernelInfo) {
330 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
331 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
334 switch (MFI->getShaderType()) {
335 default: // Fall through
336 case ShaderType::COMPUTE: RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break;
337 case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break;
338 case ShaderType::PIXEL: RsrcReg = R_00B028_SPI_SHADER_PGM_RSRC1_PS; break;
339 case ShaderType::VERTEX: RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; break;
342 unsigned LDSAlignShift;
343 if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
344 // LDS is allocated in 64 dword blocks.
347 // LDS is allocated in 128 dword blocks.
352 RoundUpToAlignment(MFI->LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
354 if (MFI->getShaderType() == ShaderType::COMPUTE) {
355 OutStreamer.EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
357 const uint32_t ComputePGMRSrc1 =
358 S_00B848_VGPRS(KernelInfo.NumVGPR / 4) |
359 S_00B848_SGPRS(KernelInfo.NumSGPR / 8) |
360 S_00B848_PRIORITY(KernelInfo.Priority) |
361 S_00B848_FLOAT_MODE(KernelInfo.FloatMode) |
362 S_00B848_PRIV(KernelInfo.Priv) |
363 S_00B848_DX10_CLAMP(KernelInfo.DX10Clamp) |
364 S_00B848_IEEE_MODE(KernelInfo.DebugMode) |
365 S_00B848_IEEE_MODE(KernelInfo.IEEEMode);
367 OutStreamer.EmitIntValue(ComputePGMRSrc1, 4);
369 OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
370 OutStreamer.EmitIntValue(S_00B84C_LDS_SIZE(LDSBlocks), 4);
372 OutStreamer.EmitIntValue(RsrcReg, 4);
373 OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.NumVGPR / 4) |
374 S_00B028_SGPRS(KernelInfo.NumSGPR / 8), 4);
377 if (MFI->getShaderType() == ShaderType::PIXEL) {
378 OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
379 OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(LDSBlocks), 4);
380 OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
381 OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);