lib/Target/R600/AMDGPUAsmPrinter.cpp

   1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 ///
  12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
  13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
  14 /// an MCObjectStreamer it outputs binary code.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 //
  18
  19
  20 #include "AMDGPUAsmPrinter.h"
  21 #include "AMDGPU.h"
  22 #include "R600Defines.h"
  23 #include "R600MachineFunctionInfo.h"
  24 #include "R600RegisterInfo.h"
  25 #include "SIDefines.h"
  26 #include "SIMachineFunctionInfo.h"
  27 #include "SIRegisterInfo.h"
  28 #include "llvm/MC/MCContext.h"
  29 #include "llvm/MC/MCSectionELF.h"
  30 #include "llvm/MC/MCStreamer.h"
  31 #include "llvm/Support/ELF.h"
  32 #include "llvm/Support/MathExtras.h"
  33 #include "llvm/Support/TargetRegistry.h"
  34 #include "llvm/Target/TargetLoweringObjectFile.h"
  35
  36 using namespace llvm;
  37
  38
  39 static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
  40                                               MCStreamer &Streamer) {
  41   return new AMDGPUAsmPrinter(tm, Streamer);
  42 }
  43
  44 extern "C" void LLVMInitializeR600AsmPrinter() {
  45   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
  46 }
  47
  48 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
  49     : AsmPrinter(TM, Streamer) {
  50   DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode() &&
  51                   ! Streamer.hasRawTextSupport();
  52 }
  53
  54 /// We need to override this function so we can avoid
  55 /// the call to EmitFunctionHeader(), which the MCPureStreamer can't handle.
  56 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
  57   SetupMachineFunction(MF);
  58
  59   if (OutStreamer.hasRawTextSupport()) {
  60     OutStreamer.EmitRawText("@" + MF.getName() + ":");
  61   }
  62
  63   MCContext &Context = getObjFileLowering().getContext();
  64   const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
  65                                               ELF::SHT_PROGBITS, 0,
  66                                               SectionKind::getReadOnly());
  67   OutStreamer.SwitchSection(ConfigSection);
  68
  69   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
  70   SIProgramInfo KernelInfo;
  71   if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
  72     findNumUsedRegistersSI(MF, KernelInfo.NumSGPR, KernelInfo.NumVGPR);
  73     EmitProgramInfoSI(MF, KernelInfo);
  74   } else {
  75     EmitProgramInfoR600(MF);
  76   }
  77
  78   DisasmLines.clear();
  79   HexLines.clear();
  80   DisasmLineMaxLen = 0;
  81
  82   OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
  83   EmitFunctionBody();
  84
  85   if (isVerbose() && OutStreamer.hasRawTextSupport()) {
  86     const MCSectionELF *CommentSection
  87       = Context.getELFSection(".AMDGPU.csdata",
  88                               ELF::SHT_PROGBITS, 0,
  89                               SectionKind::getReadOnly());
  90     OutStreamer.SwitchSection(CommentSection);
  91
  92     OutStreamer.EmitRawText(
  93       Twine("; Kernel info:\n") +
  94       "; NumSgprs: " + Twine(KernelInfo.NumSGPR) + "\n" +
  95       "; NumVgprs: " + Twine(KernelInfo.NumVGPR) + "\n");
  96   }
  97
  98   if (STM.dumpCode()) {
  99 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 100     MF.dump();
 101 #endif
 102
 103     if (DisasmEnabled) {
 104       OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm",
 105                                                   ELF::SHT_NOTE, 0,
 106                                                   SectionKind::getReadOnly()));
 107
 108       for (size_t i = 0; i < DisasmLines.size(); ++i) {
 109         std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
 110         Comment += " ; " + HexLines[i] + "\n";
 111
 112         OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
 113         OutStreamer.EmitBytes(StringRef(Comment));
 114       }
 115     }
 116   }
 117
 118   return false;
 119 }
 120
 121 void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
 122   unsigned MaxGPR = 0;
 123   bool killPixel = false;
 124   const R600RegisterInfo * RI =
 125                 static_cast<const R600RegisterInfo*>(TM.getRegisterInfo());
 126   R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 127   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 128
 129   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
 130                                                   BB != BB_E; ++BB) {
 131     MachineBasicBlock &MBB = *BB;
 132     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
 133                                                     I != E; ++I) {
 134       MachineInstr &MI = *I;
 135       if (MI.getOpcode() == AMDGPU::KILLGT)
 136         killPixel = true;
 137       unsigned numOperands = MI.getNumOperands();
 138       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 139         MachineOperand & MO = MI.getOperand(op_idx);
 140         if (!MO.isReg())
 141           continue;
 142         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
 143
 144         // Register with value > 127 aren't GPR
 145         if (HWReg > 127)
 146           continue;
 147         MaxGPR = std::max(MaxGPR, HWReg);
 148       }
 149     }
 150   }
 151
 152   unsigned RsrcReg;
 153   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
 154     // Evergreen / Northern Islands
 155     switch (MFI->ShaderType) {
 156     default: // Fall through
 157     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
 158     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
 159     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
 160     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
 161     }
 162   } else {
 163     // R600 / R700
 164     switch (MFI->ShaderType) {
 165     default: // Fall through
 166     case ShaderType::GEOMETRY: // Fall through
 167     case ShaderType::COMPUTE:  // Fall through
 168     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
 169     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
 170     }
 171   }
 172
 173   OutStreamer.EmitIntValue(RsrcReg, 4);
 174   OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
 175                            S_STACK_SIZE(MFI->StackSize), 4);
 176   OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
 177   OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
 178
 179   if (MFI->ShaderType == ShaderType::COMPUTE) {
 180     OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
 181     OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
 182   }
 183 }
 184
 185 void AMDGPUAsmPrinter::findNumUsedRegistersSI(MachineFunction &MF,
 186                                               unsigned &NumSGPR,
 187                                               unsigned &NumVGPR) const {
 188   unsigned MaxSGPR = 0;
 189   unsigned MaxVGPR = 0;
 190   bool VCCUsed = false;
 191   const SIRegisterInfo * RI =
 192                 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
 193
 194   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
 195                                                   BB != BB_E; ++BB) {
 196     MachineBasicBlock &MBB = *BB;
 197     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
 198                                                     I != E; ++I) {
 199       MachineInstr &MI = *I;
 200
 201       unsigned numOperands = MI.getNumOperands();
 202       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 203         MachineOperand &MO = MI.getOperand(op_idx);
 204         unsigned width = 0;
 205         bool isSGPR = false;
 206
 207         if (!MO.isReg()) {
 208           continue;
 209         }
 210         unsigned reg = MO.getReg();
 211         if (reg == AMDGPU::VCC) {
 212           VCCUsed = true;
 213           continue;
 214         }
 215
 216         switch (reg) {
 217         default: break;
 218         case AMDGPU::SCC:
 219         case AMDGPU::EXEC:
 220         case AMDGPU::M0:
 221           continue;
 222         }
 223
 224         if (AMDGPU::SReg_32RegClass.contains(reg)) {
 225           isSGPR = true;
 226           width = 1;
 227         } else if (AMDGPU::VReg_32RegClass.contains(reg)) {
 228           isSGPR = false;
 229           width = 1;
 230         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
 231           isSGPR = true;
 232           width = 2;
 233         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
 234           isSGPR = false;
 235           width = 2;
 236         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
 237           isSGPR = false;
 238           width = 3;
 239         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
 240           isSGPR = true;
 241           width = 4;
 242         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
 243           isSGPR = false;
 244           width = 4;
 245         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
 246           isSGPR = true;
 247           width = 8;
 248         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
 249           isSGPR = false;
 250           width = 8;
 251         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
 252           isSGPR = true;
 253           width = 16;
 254         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
 255           isSGPR = false;
 256           width = 16;
 257         } else {
 258           llvm_unreachable("Unknown register class");
 259         }
 260         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
 261         unsigned maxUsed = hwReg + width - 1;
 262         if (isSGPR) {
 263           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
 264         } else {
 265           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
 266         }
 267       }
 268     }
 269   }
 270
 271   if (VCCUsed)
 272     MaxSGPR += 2;
 273
 274   NumSGPR = MaxSGPR;
 275   NumVGPR = MaxVGPR;
 276 }
 277
 278 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &Out,
 279                                         MachineFunction &MF) const {
 280   findNumUsedRegistersSI(MF, Out.NumSGPR, Out.NumVGPR);
 281 }
 282
 283 void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF,
 284                                          const SIProgramInfo &KernelInfo) {
 285   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 286
 287   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 288   unsigned RsrcReg;
 289   switch (MFI->ShaderType) {
 290   default: // Fall through
 291   case ShaderType::COMPUTE:  RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break;
 292   case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break;
 293   case ShaderType::PIXEL:    RsrcReg = R_00B028_SPI_SHADER_PGM_RSRC1_PS; break;
 294   case ShaderType::VERTEX:   RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; break;
 295   }
 296
 297   OutStreamer.EmitIntValue(RsrcReg, 4);
 298   OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.NumVGPR / 4) |
 299                            S_00B028_SGPRS(KernelInfo.NumSGPR / 8), 4);
 300
 301   unsigned LDSAlignShift;
 302   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
 303     // LDS is allocated in 64 dword blocks
 304     LDSAlignShift = 8;
 305   } else {
 306     // LDS is allocated in 128 dword blocks
 307     LDSAlignShift = 9;
 308   }
 309   unsigned LDSBlocks =
 310           RoundUpToAlignment(MFI->LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
 311
 312   if (MFI->ShaderType == ShaderType::COMPUTE) {
 313     OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
 314     OutStreamer.EmitIntValue(S_00B84C_LDS_SIZE(LDSBlocks), 4);
 315   }
 316   if (MFI->ShaderType == ShaderType::PIXEL) {
 317     OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
 318     OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(LDSBlocks), 4);
 319     OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
 320     OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
 321   }
 322 }