1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer --------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
13 /// code. When passed an MCAsmStreamer it prints assembly and when passed
14 /// an MCObjectStreamer it outputs binary code.
16 //===----------------------------------------------------------------------===//
19 #include "AMDGPUAsmPrinter.h"
21 #include "AMDKernelCodeT.h"
22 #include "AMDGPUSubtarget.h"
23 #include "R600Defines.h"
24 #include "R600MachineFunctionInfo.h"
25 #include "R600RegisterInfo.h"
26 #include "SIDefines.h"
27 #include "SIMachineFunctionInfo.h"
28 #include "SIRegisterInfo.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/MC/MCContext.h"
31 #include "llvm/MC/MCSectionELF.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/Support/ELF.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/TargetRegistry.h"
36 #include "llvm/Target/TargetLoweringObjectFile.h"
40 // TODO: This should get the default rounding mode from the kernel. We just set
41 // the default here, but this could change if the OpenCL rounding mode pragmas
44 // The denormal mode here should match what is reported by the OpenCL runtime
45 // for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
46 // can also be override to flush with the -cl-denorms-are-zero compiler flag.
48 // AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
49 // precision, and leaves single precision to flush all and does not report
50 // CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
51 // CL_FP_DENORM for both.
53 // FIXME: It seems some instructions do not support single precision denormals
54 // regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
55 // and sin_f32, cos_f32 on most parts).
57 // We want to use these instructions, and using fp32 denormals also causes
58 // instructions to run at the double precision rate for the device so it's
59 // probably best to just report no single precision denormals.
60 static uint32_t getFPMode(const MachineFunction &F) {
61 const AMDGPUSubtarget& ST = F.getTarget().getSubtarget<AMDGPUSubtarget>();
62 // TODO: Is there any real use for the flush in only / flush out only modes?
64 uint32_t FP32Denormals =
65 ST.hasFP32Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
67 uint32_t FP64Denormals =
68 ST.hasFP64Denormals() ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
70 return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
71 FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
72 FP_DENORM_MODE_SP(FP32Denormals) |
73 FP_DENORM_MODE_DP(FP64Denormals);
76 static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
77 MCStreamer &Streamer) {
78 return new AMDGPUAsmPrinter(tm, Streamer);
81 extern "C" void LLVMInitializeR600AsmPrinter() {
82 TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
83 TargetRegistry::RegisterAsmPrinter(TheGCNTarget, createAMDGPUAsmPrinterPass);
86 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
87 : AsmPrinter(TM, Streamer) {
88 DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode();
91 void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
93 // This label is used to mark the end of the .text section.
94 const TargetLoweringObjectFile &TLOF = getObjFileLowering();
95 OutStreamer.SwitchSection(TLOF.getTextSection());
96 MCSymbol *EndOfTextLabel =
97 OutContext.GetOrCreateSymbol(StringRef(END_OF_TEXT_LABEL_NAME));
98 OutStreamer.EmitLabel(EndOfTextLabel);
101 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
103 // The starting address of all shader programs must be 256 bytes aligned.
106 SetupMachineFunction(MF);
108 EmitFunctionHeader();
110 MCContext &Context = getObjFileLowering().getContext();
111 const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
112 ELF::SHT_PROGBITS, 0,
113 SectionKind::getReadOnly());
114 OutStreamer.SwitchSection(ConfigSection);
116 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
117 SIProgramInfo KernelInfo;
118 if (STM.isAmdHsaOS()) {
119 OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
120 getSIProgramInfo(KernelInfo, MF);
121 EmitAmdKernelCodeT(MF, KernelInfo);
122 OutStreamer.EmitCodeAlignment(2 << (MF.getAlignment() - 1));
123 } else if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
124 getSIProgramInfo(KernelInfo, MF);
125 EmitProgramInfoSI(MF, KernelInfo);
127 EmitProgramInfoR600(MF);
132 DisasmLineMaxLen = 0;
134 OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
138 const MCSectionELF *CommentSection
139 = Context.getELFSection(".AMDGPU.csdata",
140 ELF::SHT_PROGBITS, 0,
141 SectionKind::getReadOnly());
142 OutStreamer.SwitchSection(CommentSection);
144 if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
145 OutStreamer.emitRawComment(" Kernel info:", false);
146 OutStreamer.emitRawComment(" codeLenInByte = " + Twine(KernelInfo.CodeLen),
148 OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
150 OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
152 OutStreamer.emitRawComment(" FloatMode: " + Twine(KernelInfo.FloatMode),
154 OutStreamer.emitRawComment(" IeeeMode: " + Twine(KernelInfo.IEEEMode),
156 OutStreamer.emitRawComment(" ScratchSize: " + Twine(KernelInfo.ScratchSize),
159 R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
160 OutStreamer.emitRawComment(
161 Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
165 if (STM.dumpCode() && DisasmEnabled) {
167 OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm",
169 SectionKind::getReadOnly()));
171 for (size_t i = 0; i < DisasmLines.size(); ++i) {
172 std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
173 Comment += " ; " + HexLines[i] + "\n";
175 OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
176 OutStreamer.EmitBytes(StringRef(Comment));
183 void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
185 bool killPixel = false;
186 const R600RegisterInfo *RI = static_cast<const R600RegisterInfo *>(
187 TM.getSubtargetImpl()->getRegisterInfo());
188 const R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
189 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
191 for (const MachineBasicBlock &MBB : MF) {
192 for (const MachineInstr &MI : MBB) {
193 if (MI.getOpcode() == AMDGPU::KILLGT)
195 unsigned numOperands = MI.getNumOperands();
196 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
197 const MachineOperand &MO = MI.getOperand(op_idx);
200 unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
202 // Register with value > 127 aren't GPR
205 MaxGPR = std::max(MaxGPR, HWReg);
211 if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
212 // Evergreen / Northern Islands
213 switch (MFI->getShaderType()) {
214 default: // Fall through
215 case ShaderType::COMPUTE: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
216 case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
217 case ShaderType::PIXEL: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
218 case ShaderType::VERTEX: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
222 switch (MFI->getShaderType()) {
223 default: // Fall through
224 case ShaderType::GEOMETRY: // Fall through
225 case ShaderType::COMPUTE: // Fall through
226 case ShaderType::VERTEX: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
227 case ShaderType::PIXEL: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
231 OutStreamer.EmitIntValue(RsrcReg, 4);
232 OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
233 S_STACK_SIZE(MFI->StackSize), 4);
234 OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
235 OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
237 if (MFI->getShaderType() == ShaderType::COMPUTE) {
238 OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
239 OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
243 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
244 const MachineFunction &MF) const {
245 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
246 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
247 uint64_t CodeSize = 0;
248 unsigned MaxSGPR = 0;
249 unsigned MaxVGPR = 0;
250 bool VCCUsed = false;
251 bool FlatUsed = false;
252 const SIRegisterInfo *RI = static_cast<const SIRegisterInfo *>(
253 TM.getSubtargetImpl()->getRegisterInfo());
255 for (const MachineBasicBlock &MBB : MF) {
256 for (const MachineInstr &MI : MBB) {
257 // TODO: CodeSize should account for multiple functions.
258 CodeSize += MI.getDesc().Size;
260 unsigned numOperands = MI.getNumOperands();
261 for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
262 const MachineOperand &MO = MI.getOperand(op_idx);
269 unsigned reg = MO.getReg();
270 if (reg == AMDGPU::VCC || reg == AMDGPU::VCC_LO ||
271 reg == AMDGPU::VCC_HI) {
274 } else if (reg == AMDGPU::FLAT_SCR ||
275 reg == AMDGPU::FLAT_SCR_LO ||
276 reg == AMDGPU::FLAT_SCR_HI) {
289 if (AMDGPU::SReg_32RegClass.contains(reg)) {
292 } else if (AMDGPU::VReg_32RegClass.contains(reg)) {
295 } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
298 } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
301 } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
304 } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
307 } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
310 } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
313 } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
316 } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
319 } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
323 llvm_unreachable("Unknown register class");
325 unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
326 unsigned maxUsed = hwReg + width - 1;
328 MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
330 MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
342 // We found the maximum register index. They start at 0, so add one to get the
343 // number of registers.
344 ProgInfo.NumVGPR = MaxVGPR + 1;
345 ProgInfo.NumSGPR = MaxSGPR + 1;
347 ProgInfo.VGPRBlocks = (ProgInfo.NumVGPR - 1) / 4;
348 ProgInfo.SGPRBlocks = (ProgInfo.NumSGPR - 1) / 8;
349 // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
351 ProgInfo.FloatMode = getFPMode(MF);
353 // XXX: Not quite sure what this does, but sc seems to unset this.
354 ProgInfo.IEEEMode = 0;
356 // Do not clamp NAN to 0.
357 ProgInfo.DX10Clamp = 0;
359 const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
360 ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);
362 ProgInfo.FlatUsed = FlatUsed;
363 ProgInfo.VCCUsed = VCCUsed;
364 ProgInfo.CodeLen = CodeSize;
366 unsigned LDSAlignShift;
367 if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
368 // LDS is allocated in 64 dword blocks.
371 // LDS is allocated in 128 dword blocks.
375 unsigned LDSSpillSize = MFI->LDSWaveSpillSize *
376 MFI->getMaximumWorkGroupSize(MF);
378 ProgInfo.LDSSize = MFI->LDSSize + LDSSpillSize;
380 RoundUpToAlignment(ProgInfo.LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
382 // Scratch is allocated in 256 dword blocks.
383 unsigned ScratchAlignShift = 10;
384 // We need to program the hardware with the amount of scratch memory that
385 // is used by the entire wave. ProgInfo.ScratchSize is the amount of
386 // scratch memory used per thread.
387 ProgInfo.ScratchBlocks =
388 RoundUpToAlignment(ProgInfo.ScratchSize * STM.getWavefrontSize(),
389 1 << ScratchAlignShift) >> ScratchAlignShift;
391 ProgInfo.ComputePGMRSrc1 =
392 S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
393 S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
394 S_00B848_PRIORITY(ProgInfo.Priority) |
395 S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
396 S_00B848_PRIV(ProgInfo.Priv) |
397 S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
398 S_00B848_IEEE_MODE(ProgInfo.DebugMode) |
399 S_00B848_IEEE_MODE(ProgInfo.IEEEMode);
401 ProgInfo.ComputePGMRSrc2 =
402 S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
403 S_00B84C_USER_SGPR(MFI->NumUserSGPRs) |
404 S_00B84C_TGID_X_EN(1) |
405 S_00B84C_TGID_Y_EN(1) |
406 S_00B84C_TGID_Z_EN(1) |
407 S_00B84C_TG_SIZE_EN(1) |
408 S_00B84C_TIDIG_COMP_CNT(2) |
409 S_00B84C_LDS_SIZE(ProgInfo.LDSBlocks);
412 static unsigned getRsrcReg(unsigned ShaderType) {
413 switch (ShaderType) {
414 default: // Fall through
415 case ShaderType::COMPUTE: return R_00B848_COMPUTE_PGM_RSRC1;
416 case ShaderType::GEOMETRY: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
417 case ShaderType::PIXEL: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
418 case ShaderType::VERTEX: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
422 void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
423 const SIProgramInfo &KernelInfo) {
424 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
425 unsigned RsrcReg = getRsrcReg(MFI->getShaderType());
427 if (MFI->getShaderType() == ShaderType::COMPUTE) {
428 OutStreamer.EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
430 OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc1, 4);
432 OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
433 OutStreamer.EmitIntValue(KernelInfo.ComputePGMRSrc2, 4);
435 OutStreamer.EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
436 OutStreamer.EmitIntValue(S_00B860_WAVESIZE(KernelInfo.ScratchBlocks), 4);
438 // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
439 // 0" comment but I don't see a corresponding field in the register spec.
441 OutStreamer.EmitIntValue(RsrcReg, 4);
442 OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.VGPRBlocks) |
443 S_00B028_SGPRS(KernelInfo.SGPRBlocks), 4);
446 if (MFI->getShaderType() == ShaderType::PIXEL) {
447 OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
448 OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(KernelInfo.LDSBlocks), 4);
449 OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
450 OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
454 void AMDGPUAsmPrinter::EmitAmdKernelCodeT(const MachineFunction &MF,
455 const SIProgramInfo &KernelInfo) const {
456 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
457 const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
458 amd_kernel_code_t header;
460 memset(&header, 0, sizeof(header));
462 header.amd_code_version_major = AMD_CODE_VERSION_MAJOR;
463 header.amd_code_version_minor = AMD_CODE_VERSION_MINOR;
465 header.struct_byte_size = sizeof(amd_kernel_code_t);
467 header.target_chip = STM.getAmdKernelCodeChipID();
469 header.kernel_code_entry_byte_offset = (1ULL << MF.getAlignment());
471 header.compute_pgm_resource_registers =
472 KernelInfo.ComputePGMRSrc1 |
473 (KernelInfo.ComputePGMRSrc2 << 32);
476 header.code_properties = AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR |
477 AMD_CODE_PROPERTY_IS_PTR64;
479 if (KernelInfo.FlatUsed)
480 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
482 if (KernelInfo.ScratchBlocks)
483 header.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE;
485 header.workitem_private_segment_byte_size = KernelInfo.ScratchSize;
486 header.workgroup_group_segment_byte_size = KernelInfo.LDSSize;
488 // MFI->ABIArgOffset is the number of bytes for the kernel arguments
489 // plus 36. 36 is the number of bytes reserved at the begining of the
490 // input buffer to store work-group size information.
491 // FIXME: We should be adding the size of the implicit arguments
493 header.kernarg_segment_byte_size = MFI->ABIArgOffset;
495 header.wavefront_sgpr_count = KernelInfo.NumSGPR;
496 header.workitem_vgpr_count = KernelInfo.NumVGPR;
498 // FIXME: What values do I put for these alignments
499 header.kernarg_segment_alignment = 0;
500 header.group_segment_alignment = 0;
501 header.private_segment_alignment = 0;
503 header.code_type = 1; // HSA_EXT_CODE_KERNEL
505 header.wavefront_size = STM.getWavefrontSize();
508 OutStreamer.emitRawComment("amd_code_version_major = " +
509 Twine(header.amd_code_version_major), false);
510 OutStreamer.emitRawComment("amd_code_version_minor = " +
511 Twine(header.amd_code_version_minor), false);
512 OutStreamer.emitRawComment("struct_byte_size = " +
513 Twine(header.struct_byte_size), false);
514 OutStreamer.emitRawComment("target_chip = " +
515 Twine(header.target_chip), false);
516 OutStreamer.emitRawComment(" compute_pgm_rsrc1: " +
517 Twine::utohexstr(KernelInfo.ComputePGMRSrc1), false);
518 OutStreamer.emitRawComment(" compute_pgm_rsrc2: " +
519 Twine::utohexstr(KernelInfo.ComputePGMRSrc2), false);
520 OutStreamer.emitRawComment("enable_sgpr_private_segment_buffer = " +
521 Twine((bool)(header.code_properties &
522 AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE)), false);
523 OutStreamer.emitRawComment("enable_sgpr_kernarg_segment_ptr = " +
524 Twine((bool)(header.code_properties &
525 AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR)), false);
526 OutStreamer.emitRawComment("private_element_size = 2 ", false);
527 OutStreamer.emitRawComment("is_ptr64 = " +
528 Twine((bool)(header.code_properties & AMD_CODE_PROPERTY_IS_PTR64)), false);
529 OutStreamer.emitRawComment("workitem_private_segment_byte_size = " +
530 Twine(header.workitem_private_segment_byte_size),
532 OutStreamer.emitRawComment("workgroup_group_segment_byte_size = " +
533 Twine(header.workgroup_group_segment_byte_size),
535 OutStreamer.emitRawComment("gds_segment_byte_size = " +
536 Twine(header.gds_segment_byte_size), false);
537 OutStreamer.emitRawComment("kernarg_segment_byte_size = " +
538 Twine(header.kernarg_segment_byte_size), false);
539 OutStreamer.emitRawComment("wavefront_sgpr_count = " +
540 Twine(header.wavefront_sgpr_count), false);
541 OutStreamer.emitRawComment("workitem_vgpr_count = " +
542 Twine(header.workitem_vgpr_count), false);
543 OutStreamer.emitRawComment("code_type = " + Twine(header.code_type), false);
544 OutStreamer.emitRawComment("wavefront_size = " +
545 Twine((int)header.wavefront_size), false);
546 OutStreamer.emitRawComment("optimization_level = " +
547 Twine(header.optimization_level), false);
548 OutStreamer.emitRawComment("hsail_profile = " +
549 Twine(header.hsail_profile), false);
550 OutStreamer.emitRawComment("hsail_machine_model = " +
551 Twine(header.hsail_machine_model), false);
552 OutStreamer.emitRawComment("hsail_version_major = " +
553 Twine(header.hsail_version_major), false);
554 OutStreamer.emitRawComment("hsail_version_minor = " +
555 Twine(header.hsail_version_minor), false);
558 OutStreamer.EmitBytes(StringRef((char*)&header, sizeof(header)));