lib/Target/R600/AMDGPUAsmPrinter.cpp

   1 //===-- AMDGPUAsmPrinter.cpp - AMDGPU Assebly printer  --------------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 /// \file
  11 ///
  12 /// The AMDGPUAsmPrinter is used to print both assembly string and also binary
  13 /// code.  When passed an MCAsmStreamer it prints assembly and when passed
  14 /// an MCObjectStreamer it outputs binary code.
  15 //
  16 //===----------------------------------------------------------------------===//
  17 //
  18
  19
  20 #include "AMDGPUAsmPrinter.h"
  21 #include "AMDGPU.h"
  22 #include "R600Defines.h"
  23 #include "R600MachineFunctionInfo.h"
  24 #include "R600RegisterInfo.h"
  25 #include "SIDefines.h"
  26 #include "SIMachineFunctionInfo.h"
  27 #include "SIRegisterInfo.h"
  28 #include "llvm/MC/MCContext.h"
  29 #include "llvm/MC/MCSectionELF.h"
  30 #include "llvm/MC/MCStreamer.h"
  31 #include "llvm/Support/ELF.h"
  32 #include "llvm/Support/MathExtras.h"
  33 #include "llvm/Support/TargetRegistry.h"
  34 #include "llvm/Target/TargetLoweringObjectFile.h"
  35
  36 using namespace llvm;
  37
  38
  39 static AsmPrinter *createAMDGPUAsmPrinterPass(TargetMachine &tm,
  40                                               MCStreamer &Streamer) {
  41   return new AMDGPUAsmPrinter(tm, Streamer);
  42 }
  43
  44 extern "C" void LLVMInitializeR600AsmPrinter() {
  45   TargetRegistry::RegisterAsmPrinter(TheAMDGPUTarget, createAMDGPUAsmPrinterPass);
  46 }
  47
  48 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
  49     : AsmPrinter(TM, Streamer) {
  50   DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode() &&
  51                   ! Streamer.hasRawTextSupport();
  52 }
  53
  54 /// We need to override this function so we can avoid
  55 /// the call to EmitFunctionHeader(), which the MCPureStreamer can't handle.
  56 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
  57   SetupMachineFunction(MF);
  58
  59   OutStreamer.emitRawComment(Twine('@') + MF.getName() + Twine(':'));
  60
  61   MCContext &Context = getObjFileLowering().getContext();
  62   const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
  63                                               ELF::SHT_PROGBITS, 0,
  64                                               SectionKind::getReadOnly());
  65   OutStreamer.SwitchSection(ConfigSection);
  66
  67   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
  68   SIProgramInfo KernelInfo;
  69   if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
  70     findNumUsedRegistersSI(MF, KernelInfo.NumSGPR, KernelInfo.NumVGPR);
  71     EmitProgramInfoSI(MF, KernelInfo);
  72   } else {
  73     EmitProgramInfoR600(MF);
  74   }
  75
  76   DisasmLines.clear();
  77   HexLines.clear();
  78   DisasmLineMaxLen = 0;
  79
  80   OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
  81   EmitFunctionBody();
  82
  83   if (isVerbose()) {
  84     const MCSectionELF *CommentSection
  85       = Context.getELFSection(".AMDGPU.csdata",
  86                               ELF::SHT_PROGBITS, 0,
  87                               SectionKind::getReadOnly());
  88     OutStreamer.SwitchSection(CommentSection);
  89
  90     if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
  91       OutStreamer.emitRawComment(" Kernel info:", false);
  92       OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
  93                                  false);
  94       OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
  95                                  false);
  96     } else {
  97       R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
  98       OutStreamer.emitRawComment(
  99         Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
 100     }
 101   }
 102
 103   if (STM.dumpCode()) {
 104 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 105     MF.dump();
 106 #endif
 107
 108     if (DisasmEnabled) {
 109       OutStreamer.SwitchSection(Context.getELFSection(".AMDGPU.disasm",
 110                                                   ELF::SHT_NOTE, 0,
 111                                                   SectionKind::getReadOnly()));
 112
 113       for (size_t i = 0; i < DisasmLines.size(); ++i) {
 114         std::string Comment(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
 115         Comment += " ; " + HexLines[i] + "\n";
 116
 117         OutStreamer.EmitBytes(StringRef(DisasmLines[i]));
 118         OutStreamer.EmitBytes(StringRef(Comment));
 119       }
 120     }
 121   }
 122
 123   return false;
 124 }
 125
 126 void AMDGPUAsmPrinter::EmitProgramInfoR600(MachineFunction &MF) {
 127   unsigned MaxGPR = 0;
 128   bool killPixel = false;
 129   const R600RegisterInfo * RI =
 130                 static_cast<const R600RegisterInfo*>(TM.getRegisterInfo());
 131   R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
 132   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 133
 134   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
 135                                                   BB != BB_E; ++BB) {
 136     MachineBasicBlock &MBB = *BB;
 137     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
 138                                                     I != E; ++I) {
 139       MachineInstr &MI = *I;
 140       if (MI.getOpcode() == AMDGPU::KILLGT)
 141         killPixel = true;
 142       unsigned numOperands = MI.getNumOperands();
 143       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 144         MachineOperand & MO = MI.getOperand(op_idx);
 145         if (!MO.isReg())
 146           continue;
 147         unsigned HWReg = RI->getEncodingValue(MO.getReg()) & 0xff;
 148
 149         // Register with value > 127 aren't GPR
 150         if (HWReg > 127)
 151           continue;
 152         MaxGPR = std::max(MaxGPR, HWReg);
 153       }
 154     }
 155   }
 156
 157   unsigned RsrcReg;
 158   if (STM.getGeneration() >= AMDGPUSubtarget::EVERGREEN) {
 159     // Evergreen / Northern Islands
 160     switch (MFI->ShaderType) {
 161     default: // Fall through
 162     case ShaderType::COMPUTE:  RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
 163     case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
 164     case ShaderType::PIXEL:    RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
 165     case ShaderType::VERTEX:   RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
 166     }
 167   } else {
 168     // R600 / R700
 169     switch (MFI->ShaderType) {
 170     default: // Fall through
 171     case ShaderType::GEOMETRY: // Fall through
 172     case ShaderType::COMPUTE:  // Fall through
 173     case ShaderType::VERTEX:   RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
 174     case ShaderType::PIXEL:    RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
 175     }
 176   }
 177
 178   OutStreamer.EmitIntValue(RsrcReg, 4);
 179   OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
 180                            S_STACK_SIZE(MFI->StackSize), 4);
 181   OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
 182   OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
 183
 184   if (MFI->ShaderType == ShaderType::COMPUTE) {
 185     OutStreamer.EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
 186     OutStreamer.EmitIntValue(RoundUpToAlignment(MFI->LDSSize, 4) >> 2, 4);
 187   }
 188 }
 189
 190 void AMDGPUAsmPrinter::findNumUsedRegistersSI(MachineFunction &MF,
 191                                               unsigned &NumSGPR,
 192                                               unsigned &NumVGPR) const {
 193   unsigned MaxSGPR = 0;
 194   unsigned MaxVGPR = 0;
 195   bool VCCUsed = false;
 196   const SIRegisterInfo * RI =
 197                 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
 198
 199   for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
 200                                                   BB != BB_E; ++BB) {
 201     MachineBasicBlock &MBB = *BB;
 202     for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
 203                                                     I != E; ++I) {
 204       MachineInstr &MI = *I;
 205
 206       unsigned numOperands = MI.getNumOperands();
 207       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
 208         MachineOperand &MO = MI.getOperand(op_idx);
 209         unsigned width = 0;
 210         bool isSGPR = false;
 211
 212         if (!MO.isReg()) {
 213           continue;
 214         }
 215         unsigned reg = MO.getReg();
 216         if (reg == AMDGPU::VCC) {
 217           VCCUsed = true;
 218           continue;
 219         }
 220
 221         switch (reg) {
 222         default: break;
 223         case AMDGPU::SCC:
 224         case AMDGPU::EXEC:
 225         case AMDGPU::M0:
 226           continue;
 227         }
 228
 229         if (AMDGPU::SReg_32RegClass.contains(reg)) {
 230           isSGPR = true;
 231           width = 1;
 232         } else if (AMDGPU::VReg_32RegClass.contains(reg)) {
 233           isSGPR = false;
 234           width = 1;
 235         } else if (AMDGPU::SReg_64RegClass.contains(reg)) {
 236           isSGPR = true;
 237           width = 2;
 238         } else if (AMDGPU::VReg_64RegClass.contains(reg)) {
 239           isSGPR = false;
 240           width = 2;
 241         } else if (AMDGPU::VReg_96RegClass.contains(reg)) {
 242           isSGPR = false;
 243           width = 3;
 244         } else if (AMDGPU::SReg_128RegClass.contains(reg)) {
 245           isSGPR = true;
 246           width = 4;
 247         } else if (AMDGPU::VReg_128RegClass.contains(reg)) {
 248           isSGPR = false;
 249           width = 4;
 250         } else if (AMDGPU::SReg_256RegClass.contains(reg)) {
 251           isSGPR = true;
 252           width = 8;
 253         } else if (AMDGPU::VReg_256RegClass.contains(reg)) {
 254           isSGPR = false;
 255           width = 8;
 256         } else if (AMDGPU::SReg_512RegClass.contains(reg)) {
 257           isSGPR = true;
 258           width = 16;
 259         } else if (AMDGPU::VReg_512RegClass.contains(reg)) {
 260           isSGPR = false;
 261           width = 16;
 262         } else {
 263           llvm_unreachable("Unknown register class");
 264         }
 265         unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
 266         unsigned maxUsed = hwReg + width - 1;
 267         if (isSGPR) {
 268           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
 269         } else {
 270           MaxVGPR = maxUsed > MaxVGPR ? maxUsed : MaxVGPR;
 271         }
 272       }
 273     }
 274   }
 275
 276   if (VCCUsed)
 277     MaxSGPR += 2;
 278
 279   NumSGPR = MaxSGPR;
 280   NumVGPR = MaxVGPR;
 281 }
 282
 283 void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &Out,
 284                                         MachineFunction &MF) const {
 285   findNumUsedRegistersSI(MF, Out.NumSGPR, Out.NumVGPR);
 286 }
 287
 288 void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF,
 289                                          const SIProgramInfo &KernelInfo) {
 290   const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
 291
 292   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
 293   unsigned RsrcReg;
 294   switch (MFI->ShaderType) {
 295   default: // Fall through
 296   case ShaderType::COMPUTE:  RsrcReg = R_00B848_COMPUTE_PGM_RSRC1; break;
 297   case ShaderType::GEOMETRY: RsrcReg = R_00B228_SPI_SHADER_PGM_RSRC1_GS; break;
 298   case ShaderType::PIXEL:    RsrcReg = R_00B028_SPI_SHADER_PGM_RSRC1_PS; break;
 299   case ShaderType::VERTEX:   RsrcReg = R_00B128_SPI_SHADER_PGM_RSRC1_VS; break;
 300   }
 301
 302   OutStreamer.EmitIntValue(RsrcReg, 4);
 303   OutStreamer.EmitIntValue(S_00B028_VGPRS(KernelInfo.NumVGPR / 4) |
 304                            S_00B028_SGPRS(KernelInfo.NumSGPR / 8), 4);
 305
 306   unsigned LDSAlignShift;
 307   if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
 308     // LDS is allocated in 64 dword blocks
 309     LDSAlignShift = 8;
 310   } else {
 311     // LDS is allocated in 128 dword blocks
 312     LDSAlignShift = 9;
 313   }
 314   unsigned LDSBlocks =
 315           RoundUpToAlignment(MFI->LDSSize, 1 << LDSAlignShift) >> LDSAlignShift;
 316
 317   if (MFI->ShaderType == ShaderType::COMPUTE) {
 318     OutStreamer.EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
 319     OutStreamer.EmitIntValue(S_00B84C_LDS_SIZE(LDSBlocks), 4);
 320   }
 321   if (MFI->ShaderType == ShaderType::PIXEL) {
 322     OutStreamer.EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
 323     OutStreamer.EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(LDSBlocks), 4);
 324     OutStreamer.EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
 325     OutStreamer.EmitIntValue(MFI->PSInputAddr, 4);
 326   }
 327 }