1 //===---- AMDCallingConv.td - Calling Conventions for Radeon GPUs ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for the AMD Radeon GPUs.
12 //===----------------------------------------------------------------------===//
14 // Inversion of CCIfInReg
15 class CCIfNotInReg<CCAction A> : CCIf<"!ArgFlags.isInReg()", A> {}
17 // Calling convention for SI
18 def CC_SI : CallingConv<[
20 CCIfInReg<CCIfType<[f32, i32] , CCAssignToReg<[
21 SGPR0, SGPR1, SGPR2, SGPR3, SGPR4, SGPR5, SGPR6, SGPR7,
22 SGPR8, SGPR9, SGPR10, SGPR11, SGPR12, SGPR13, SGPR14, SGPR15
25 CCIfInReg<CCIfType<[i64] , CCAssignToRegWithShadow<
26 [ SGPR0, SGPR2, SGPR4, SGPR6, SGPR8, SGPR10, SGPR12, SGPR14 ],
27 [ SGPR1, SGPR3, SGPR5, SGPR7, SGPR9, SGPR11, SGPR12, SGPR15 ]
30 CCIfNotInReg<CCIfType<[f32, i32] , CCAssignToReg<[
31 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
32 VGPR8, VGPR9, VGPR10, VGPR11, VGPR12, VGPR13, VGPR14, VGPR15,
33 VGPR16, VGPR17, VGPR18, VGPR19, VGPR20, VGPR21, VGPR22, VGPR23,
34 VGPR24, VGPR25, VGPR26, VGPR27, VGPR28, VGPR29, VGPR30, VGPR31
39 // Calling convention for SI compute kernels
40 def CC_SI_Kernel : CallingConv<[
41 CCIfType<[v4i32, v4f32], CCAssignToStack <16, 4>>,
42 CCIfType<[i64], CCAssignToStack < 8, 4>>,
43 CCIfType<[i32, f32], CCAssignToStack < 4, 4>>,
44 CCIfType<[i16], CCAssignToStack < 2, 4>>,
45 CCIfType<[i8], CCAssignToStack < 1, 4>>
48 def CC_AMDGPU : CallingConv<[
49 CCIf<"State.getMachineFunction().getInfo<SIMachineFunctionInfo>()->"#
50 "ShaderType == ShaderType::COMPUTE", CCDelegateTo<CC_SI_Kernel>>,
51 CCIf<"State.getTarget().getSubtarget<AMDGPUSubtarget>()"#
52 ".getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS", CCDelegateTo<CC_SI>>