1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "R600InstrInfo.h"
19 #include "SIDefines.h"
20 #include "SIISelLowering.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/CodeGen/FunctionLoweringInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/IR/Function.h"
32 //===----------------------------------------------------------------------===//
33 // Instruction Selector Implementation
34 //===----------------------------------------------------------------------===//
37 /// AMDGPU specific code to select AMDGPU machine instructions for
38 /// SelectionDAG operations.
39 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
40 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
41 // make the right decision when generating code for different targets.
42 const AMDGPUSubtarget &Subtarget;
44 AMDGPUDAGToDAGISel(TargetMachine &TM);
45 virtual ~AMDGPUDAGToDAGISel();
47 SDNode *Select(SDNode *N) override;
48 const char *getPassName() const override;
49 void PostprocessISelDAG() override;
52 bool isInlineImmediate(SDNode *N) const;
53 inline SDValue getSmallIPtrImm(unsigned Imm);
54 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
55 const R600InstrInfo *TII);
56 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
57 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
59 // Complex pattern selectors
60 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
61 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
62 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
64 static bool checkType(const Value *ptr, unsigned int addrspace);
65 static bool checkPrivateAddress(const MachineMemOperand *Op);
67 static bool isGlobalStore(const StoreSDNode *N);
68 static bool isPrivateStore(const StoreSDNode *N);
69 static bool isLocalStore(const StoreSDNode *N);
70 static bool isRegionStore(const StoreSDNode *N);
72 bool isCPLoad(const LoadSDNode *N) const;
73 bool isConstantLoad(const LoadSDNode *N, int cbID) const;
74 bool isGlobalLoad(const LoadSDNode *N) const;
75 bool isParamLoad(const LoadSDNode *N) const;
76 bool isPrivateLoad(const LoadSDNode *N) const;
77 bool isLocalLoad(const LoadSDNode *N) const;
78 bool isRegionLoad(const LoadSDNode *N) const;
80 /// \returns True if the current basic block being selected is at control
81 /// flow depth 0. Meaning that the current block dominates the
83 bool isCFDepth0() const;
85 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
86 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
87 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
89 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
90 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
91 bool SelectMUBUFAddr64(SDValue Addr, SDValue &Ptr, SDValue &Offset,
92 SDValue &ImmOffset) const;
93 bool SelectMUBUFScratch(SDValue Addr, SDValue &RSrc, SDValue &VAddr,
94 SDValue &SOffset, SDValue &ImmOffset) const;
95 bool SelectMUBUFAddr32(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
96 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
97 SDValue &Idxen, SDValue &GLC, SDValue &SLC,
99 bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
100 bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
101 SDValue &Clamp, SDValue &Omod) const;
103 SDNode *SelectADD_SUB_I64(SDNode *N);
104 SDNode *SelectDIV_SCALE(SDNode *N);
106 // Include the pieces autogenerated from the target description.
107 #include "AMDGPUGenDAGISel.inc"
109 } // end anonymous namespace
111 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
112 // DAG, ready for instruction scheduling.
113 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM) {
114 return new AMDGPUDAGToDAGISel(TM);
117 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
118 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
121 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
124 bool AMDGPUDAGToDAGISel::isInlineImmediate(SDNode *N) const {
125 const SITargetLowering *TL
126 = static_cast<const SITargetLowering *>(getTargetLowering());
127 return TL->analyzeImmediate(N) == 0;
130 /// \brief Determine the register class for \p OpNo
131 /// \returns The register class of the virtual register that will be used for
132 /// the given operand number \OpNo or NULL if the register class cannot be
134 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
135 unsigned OpNo) const {
136 if (!N->isMachineOpcode())
139 switch (N->getMachineOpcode()) {
141 const MCInstrDesc &Desc = TM.getInstrInfo()->get(N->getMachineOpcode());
142 unsigned OpIdx = Desc.getNumDefs() + OpNo;
143 if (OpIdx >= Desc.getNumOperands())
145 int RegClass = Desc.OpInfo[OpIdx].RegClass;
149 return TM.getRegisterInfo()->getRegClass(RegClass);
151 case AMDGPU::REG_SEQUENCE: {
152 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
153 const TargetRegisterClass *SuperRC = TM.getRegisterInfo()->getRegClass(RCID);
155 SDValue SubRegOp = N->getOperand(OpNo + 1);
156 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
157 return TM.getRegisterInfo()->getSubClassWithSubReg(SuperRC, SubRegIdx);
162 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
163 return CurDAG->getTargetConstant(Imm, MVT::i32);
166 bool AMDGPUDAGToDAGISel::SelectADDRParam(
167 SDValue Addr, SDValue& R1, SDValue& R2) {
169 if (Addr.getOpcode() == ISD::FrameIndex) {
170 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
171 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
172 R2 = CurDAG->getTargetConstant(0, MVT::i32);
175 R2 = CurDAG->getTargetConstant(0, MVT::i32);
177 } else if (Addr.getOpcode() == ISD::ADD) {
178 R1 = Addr.getOperand(0);
179 R2 = Addr.getOperand(1);
182 R2 = CurDAG->getTargetConstant(0, MVT::i32);
187 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
188 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
189 Addr.getOpcode() == ISD::TargetGlobalAddress) {
192 return SelectADDRParam(Addr, R1, R2);
196 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
197 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
198 Addr.getOpcode() == ISD::TargetGlobalAddress) {
202 if (Addr.getOpcode() == ISD::FrameIndex) {
203 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
204 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
205 R2 = CurDAG->getTargetConstant(0, MVT::i64);
208 R2 = CurDAG->getTargetConstant(0, MVT::i64);
210 } else if (Addr.getOpcode() == ISD::ADD) {
211 R1 = Addr.getOperand(0);
212 R2 = Addr.getOperand(1);
215 R2 = CurDAG->getTargetConstant(0, MVT::i64);
220 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
221 unsigned int Opc = N->getOpcode();
222 if (N->isMachineOpcode()) {
224 return nullptr; // Already selected.
227 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
230 // We are selecting i64 ADD here instead of custom lower it during
231 // DAG legalization, so we can fold some i64 ADDs used for address
232 // calculation into the LOAD and STORE instructions.
235 if (N->getValueType(0) != MVT::i64 ||
236 ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
239 return SelectADD_SUB_I64(N);
241 case ISD::SCALAR_TO_VECTOR:
242 case AMDGPUISD::BUILD_VERTICAL_VECTOR:
243 case ISD::BUILD_VECTOR: {
245 const AMDGPURegisterInfo *TRI =
246 static_cast<const AMDGPURegisterInfo*>(TM.getRegisterInfo());
247 const SIRegisterInfo *SIRI =
248 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
249 EVT VT = N->getValueType(0);
250 unsigned NumVectorElts = VT.getVectorNumElements();
251 EVT EltVT = VT.getVectorElementType();
252 assert(EltVT.bitsEq(MVT::i32));
253 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
255 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
257 if (!U->isMachineOpcode()) {
260 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
264 if (SIRI->isSGPRClass(RC)) {
268 switch(NumVectorElts) {
269 case 1: RegClassID = UseVReg ? AMDGPU::VReg_32RegClassID :
270 AMDGPU::SReg_32RegClassID;
272 case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID :
273 AMDGPU::SReg_64RegClassID;
275 case 4: RegClassID = UseVReg ? AMDGPU::VReg_128RegClassID :
276 AMDGPU::SReg_128RegClassID;
278 case 8: RegClassID = UseVReg ? AMDGPU::VReg_256RegClassID :
279 AMDGPU::SReg_256RegClassID;
281 case 16: RegClassID = UseVReg ? AMDGPU::VReg_512RegClassID :
282 AMDGPU::SReg_512RegClassID;
284 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
287 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
288 // that adds a 128 bits reg copy when going through TwoAddressInstructions
289 // pass. We want to avoid 128 bits copies as much as possible because they
290 // can't be bundled by our scheduler.
291 switch(NumVectorElts) {
292 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
294 if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
295 RegClassID = AMDGPU::R600_Reg128VerticalRegClassID;
297 RegClassID = AMDGPU::R600_Reg128RegClassID;
299 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
303 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, MVT::i32);
305 if (NumVectorElts == 1) {
306 return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT,
307 N->getOperand(0), RegClass);
310 assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
312 // 16 = Max Num Vector Elements
313 // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
314 // 1 = Vector Register Class
315 SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
317 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, MVT::i32);
318 bool IsRegSeq = true;
319 unsigned NOps = N->getNumOperands();
320 for (unsigned i = 0; i < NOps; i++) {
321 // XXX: Why is this here?
322 if (dyn_cast<RegisterSDNode>(N->getOperand(i))) {
326 RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
327 RegSeqArgs[1 + (2 * i) + 1] =
328 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
331 if (NOps != NumVectorElts) {
332 // Fill in the missing undef elements if this was a scalar_to_vector.
333 assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
335 MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
337 for (unsigned i = NOps; i < NumVectorElts; ++i) {
338 RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
339 RegSeqArgs[1 + (2 * i) + 1] =
340 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
346 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
349 case ISD::BUILD_PAIR: {
350 SDValue RC, SubReg0, SubReg1;
351 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
354 if (N->getValueType(0) == MVT::i128) {
355 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
356 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
357 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
358 } else if (N->getValueType(0) == MVT::i64) {
359 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
360 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
361 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
363 llvm_unreachable("Unhandled value type for BUILD_PAIR");
365 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
366 N->getOperand(1), SubReg1 };
367 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
368 SDLoc(N), N->getValueType(0), Ops);
372 case ISD::ConstantFP: {
373 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
374 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
375 N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
379 if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
380 Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
382 ConstantSDNode *C = cast<ConstantSDNode>(N);
383 Imm = C->getZExtValue();
386 SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
387 CurDAG->getConstant(Imm & 0xFFFFFFFF, MVT::i32));
388 SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
389 CurDAG->getConstant(Imm >> 32, MVT::i32));
390 const SDValue Ops[] = {
391 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
392 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
393 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32)
396 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, SDLoc(N),
397 N->getValueType(0), Ops);
400 case AMDGPUISD::REGISTER_LOAD: {
401 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
403 SDValue Addr, Offset;
405 SelectADDRIndirect(N->getOperand(1), Addr, Offset);
406 const SDValue Ops[] = {
409 CurDAG->getTargetConstant(0, MVT::i32),
412 return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, SDLoc(N),
413 CurDAG->getVTList(MVT::i32, MVT::i64, MVT::Other),
416 case AMDGPUISD::REGISTER_STORE: {
417 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
419 SDValue Addr, Offset;
420 SelectADDRIndirect(N->getOperand(2), Addr, Offset);
421 const SDValue Ops[] = {
425 CurDAG->getTargetConstant(0, MVT::i32),
428 return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, SDLoc(N),
429 CurDAG->getVTList(MVT::Other),
433 case AMDGPUISD::BFE_I32:
434 case AMDGPUISD::BFE_U32: {
435 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
438 // There is a scalar version available, but unlike the vector version which
439 // has a separate operand for the offset and width, the scalar version packs
440 // the width and offset into a single operand. Try to move to the scalar
441 // version if the offsets are constant, so that we can try to keep extended
442 // loads of kernel arguments in SGPRs.
444 // TODO: Technically we could try to pattern match scalar bitshifts of
445 // dynamic values, but it's probably not useful.
446 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
450 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
454 bool Signed = Opc == AMDGPUISD::BFE_I32;
456 // Transformation function, pack the offset and width of a BFE into
457 // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
458 // source, bits [5:0] contain the offset and bits [22:16] the width.
460 uint32_t OffsetVal = Offset->getZExtValue();
461 uint32_t WidthVal = Width->getZExtValue();
463 uint32_t PackedVal = OffsetVal | WidthVal << 16;
465 SDValue PackedOffsetWidth = CurDAG->getTargetConstant(PackedVal, MVT::i32);
466 return CurDAG->getMachineNode(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32,
473 case AMDGPUISD::DIV_SCALE: {
474 return SelectDIV_SCALE(N);
477 return SelectCode(N);
481 bool AMDGPUDAGToDAGISel::checkType(const Value *Ptr, unsigned AS) {
482 assert(AS != 0 && "Use checkPrivateAddress instead.");
486 return Ptr->getType()->getPointerAddressSpace() == AS;
489 bool AMDGPUDAGToDAGISel::checkPrivateAddress(const MachineMemOperand *Op) {
490 if (Op->getPseudoValue())
493 if (PointerType *PT = dyn_cast<PointerType>(Op->getValue()->getType()))
494 return PT->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
499 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
500 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
503 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
504 const Value *MemVal = N->getMemOperand()->getValue();
505 return (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
506 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
507 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS));
510 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
511 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
514 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
515 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
518 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
519 const Value *MemVal = N->getMemOperand()->getValue();
521 return checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS);
523 return checkType(MemVal, AMDGPUAS::CONSTANT_BUFFER_0 + CbId);
526 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
527 if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) {
528 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
529 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
530 N->getMemoryVT().bitsLT(MVT::i32)) {
534 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
537 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
538 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::PARAM_I_ADDRESS);
541 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
542 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
545 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
546 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
549 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
550 MachineMemOperand *MMO = N->getMemOperand();
551 if (checkPrivateAddress(N->getMemOperand())) {
553 const PseudoSourceValue *PSV = MMO->getPseudoValue();
554 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
562 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
563 if (checkPrivateAddress(N->getMemOperand())) {
564 // Check to make sure we are not a constant pool load or a constant load
565 // that is marked as a private load
566 if (isCPLoad(N) || isConstantLoad(N, -1)) {
571 const Value *MemVal = N->getMemOperand()->getValue();
572 if (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
573 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
574 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS) &&
575 !checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) &&
576 !checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) &&
577 !checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS)){
583 bool AMDGPUDAGToDAGISel::isCFDepth0() const {
584 // FIXME: Figure out a way to use DominatorTree analysis here.
585 const BasicBlock *CurBlock = FuncInfo->MBB->getBasicBlock();
586 const Function *Fn = FuncInfo->Fn;
587 return &Fn->front() == CurBlock || &Fn->back() == CurBlock;
591 const char *AMDGPUDAGToDAGISel::getPassName() const {
592 return "AMDGPU DAG->DAG Pattern Instruction Selection";
600 //===----------------------------------------------------------------------===//
602 //===----------------------------------------------------------------------===//
604 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
606 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
607 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
613 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
614 SDValue& BaseReg, SDValue &Offset) {
615 if (!isa<ConstantSDNode>(Addr)) {
617 Offset = CurDAG->getIntPtrConstant(0, true);
623 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
625 ConstantSDNode *IMMOffset;
627 if (Addr.getOpcode() == ISD::ADD
628 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
629 && isInt<16>(IMMOffset->getZExtValue())) {
631 Base = Addr.getOperand(0);
632 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
634 // If the pointer address is constant, we can move it to the offset field.
635 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
636 && isInt<16>(IMMOffset->getZExtValue())) {
637 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
638 SDLoc(CurDAG->getEntryNode()),
639 AMDGPU::ZERO, MVT::i32);
640 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
644 // Default case, no offset
646 Offset = CurDAG->getTargetConstant(0, MVT::i32);
650 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
654 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
655 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
656 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
657 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
658 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
659 Base = Addr.getOperand(0);
660 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
663 Offset = CurDAG->getTargetConstant(0, MVT::i32);
669 SDNode *AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
671 SDValue LHS = N->getOperand(0);
672 SDValue RHS = N->getOperand(1);
674 bool IsAdd = (N->getOpcode() == ISD::ADD);
676 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
677 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
679 SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
680 DL, MVT::i32, LHS, Sub0);
681 SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
682 DL, MVT::i32, LHS, Sub1);
684 SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
685 DL, MVT::i32, RHS, Sub0);
686 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
687 DL, MVT::i32, RHS, Sub1);
689 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
690 SDValue AddLoArgs[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
693 unsigned Opc = IsAdd ? AMDGPU::S_ADD_I32 : AMDGPU::S_SUB_I32;
694 unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
697 Opc = IsAdd ? AMDGPU::V_ADD_I32_e32 : AMDGPU::V_SUB_I32_e32;
698 CarryOpc = IsAdd ? AMDGPU::V_ADDC_U32_e32 : AMDGPU::V_SUBB_U32_e32;
701 SDNode *AddLo = CurDAG->getMachineNode( Opc, DL, VTList, AddLoArgs);
702 SDValue Carry(AddLo, 1);
704 = CurDAG->getMachineNode(CarryOpc, DL, MVT::i32,
705 SDValue(Hi0, 0), SDValue(Hi1, 0), Carry);
708 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
714 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args);
717 SDNode *AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
719 EVT VT = N->getValueType(0);
721 assert(VT == MVT::f32 || VT == MVT::f64);
724 = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
726 const SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
738 return CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
741 static SDValue wrapAddr64Rsrc(SelectionDAG *DAG, SDLoc DL, SDValue Ptr) {
742 return SDValue(DAG->getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::v4i32,
746 static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) {
747 return isUInt<12>(Imm->getZExtValue());
750 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &Ptr,
752 SDValue &ImmOffset) const {
755 if (CurDAG->isBaseWithConstantOffset(Addr)) {
756 SDValue N0 = Addr.getOperand(0);
757 SDValue N1 = Addr.getOperand(1);
758 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
760 if (isLegalMUBUFImmOffset(C1)) {
762 if (N0.getOpcode() == ISD::ADD) {
763 // (add (add N2, N3), C1)
764 SDValue N2 = N0.getOperand(0);
765 SDValue N3 = N0.getOperand(1);
766 Ptr = wrapAddr64Rsrc(CurDAG, DL, N2);
768 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
773 Ptr = wrapAddr64Rsrc(CurDAG, DL, CurDAG->getTargetConstant(0, MVT::i64));;
775 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
779 if (Addr.getOpcode() == ISD::ADD) {
781 SDValue N0 = Addr.getOperand(0);
782 SDValue N1 = Addr.getOperand(1);
783 Ptr = wrapAddr64Rsrc(CurDAG, DL, N0);
785 ImmOffset = CurDAG->getTargetConstant(0, MVT::i16);
790 Ptr = wrapAddr64Rsrc(CurDAG, DL, CurDAG->getConstant(0, MVT::i64));
792 ImmOffset = CurDAG->getTargetConstant(0, MVT::i16);
796 /// \brief Return a resource descriptor with the 'Add TID' bit enabled
797 /// The TID (Thread ID) is multipled by the stride value (bits [61:48]
798 /// of the resource descriptor) to create an offset, which is added to the
800 static SDValue buildScratchRSRC(SelectionDAG *DAG, SDLoc DL, SDValue Ptr) {
802 uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE |
805 SDValue PtrLo = DAG->getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
806 SDValue PtrHi = DAG->getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
807 SDValue DataLo = DAG->getTargetConstant(
808 Rsrc & APInt::getAllOnesValue(32).getZExtValue(), MVT::i32);
809 SDValue DataHi = DAG->getTargetConstant(Rsrc >> 32, MVT::i32);
811 const SDValue Ops[] = { PtrLo, PtrHi, DataLo, DataHi };
812 return SDValue(DAG->getMachineNode(AMDGPU::SI_BUFFER_RSRC, DL,
813 MVT::v4i32, Ops), 0);
816 bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
817 SDValue &VAddr, SDValue &SOffset,
818 SDValue &ImmOffset) const {
821 MachineFunction &MF = CurDAG->getMachineFunction();
822 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo*>(MF.getTarget().getRegisterInfo());
823 MachineRegisterInfo &MRI = MF.getRegInfo();
826 unsigned ScratchPtrReg =
827 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
828 unsigned ScratchOffsetReg =
829 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET);
831 Rsrc = buildScratchRSRC(CurDAG, DL, CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, MRI.getLiveInVirtReg(ScratchPtrReg), MVT::i64));
832 SOffset = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
833 MRI.getLiveInVirtReg(ScratchOffsetReg), MVT::i32);
836 if (CurDAG->isBaseWithConstantOffset(Addr)) {
837 SDValue N1 = Addr.getOperand(1);
838 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
840 if (isLegalMUBUFImmOffset(C1)) {
841 VAddr = Addr.getOperand(0);
842 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
848 if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
849 isa<FrameIndexSDNode>(Addr.getOperand(0))) {
850 VAddr = Addr.getOperand(1);
851 ImmOffset = Addr.getOperand(0);
856 if (isa<FrameIndexSDNode>(Addr)) {
857 VAddr = SDValue(CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, DL, MVT::i32,
858 CurDAG->getConstant(0, MVT::i32)), 0);
865 ImmOffset = CurDAG->getTargetConstant(0, MVT::i16);
869 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr32(SDValue Addr, SDValue &SRsrc,
870 SDValue &VAddr, SDValue &SOffset,
871 SDValue &Offset, SDValue &Offen,
872 SDValue &Idxen, SDValue &GLC,
873 SDValue &SLC, SDValue &TFE) const {
875 GLC = CurDAG->getTargetConstant(0, MVT::i1);
876 SLC = CurDAG->getTargetConstant(0, MVT::i1);
877 TFE = CurDAG->getTargetConstant(0, MVT::i1);
879 Idxen = CurDAG->getTargetConstant(0, MVT::i1);
880 Offen = CurDAG->getTargetConstant(1, MVT::i1);
882 return SelectMUBUFScratch(Addr, SRsrc, VAddr, SOffset, Offset);
885 bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
886 SDValue &SrcMods) const {
892 if (Src.getOpcode() == ISD::FNEG) {
893 Mods |= SISrcMods::NEG;
894 Src = Src.getOperand(0);
897 if (Src.getOpcode() == ISD::FABS) {
898 Mods |= SISrcMods::ABS;
899 Src = Src.getOperand(0);
902 SrcMods = CurDAG->getTargetConstant(Mods, MVT::i32);
907 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
908 SDValue &SrcMods, SDValue &Clamp,
909 SDValue &Omod) const {
910 // FIXME: Handle Clamp and Omod
911 Clamp = CurDAG->getTargetConstant(0, MVT::i32);
912 Omod = CurDAG->getTargetConstant(0, MVT::i32);
914 return SelectVOP3Mods(In, Src, SrcMods);
917 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
918 const AMDGPUTargetLowering& Lowering =
919 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
920 bool IsModified = false;
923 // Go over all selected nodes and try to fold them a bit more
924 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
925 E = CurDAG->allnodes_end(); I != E; ++I) {
929 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
933 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
934 if (ResNode != Node) {
935 ReplaceUses(Node, ResNode);
939 CurDAG->RemoveDeadNodes();
940 } while (IsModified);