1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "R600InstrInfo.h"
19 #include "SIDefines.h"
20 #include "SIISelLowering.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/CodeGen/FunctionLoweringInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/IR/Function.h"
32 //===----------------------------------------------------------------------===//
33 // Instruction Selector Implementation
34 //===----------------------------------------------------------------------===//
37 /// AMDGPU specific code to select AMDGPU machine instructions for
38 /// SelectionDAG operations.
39 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
40 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
41 // make the right decision when generating code for different targets.
42 const AMDGPUSubtarget &Subtarget;
44 AMDGPUDAGToDAGISel(TargetMachine &TM);
45 virtual ~AMDGPUDAGToDAGISel();
47 SDNode *Select(SDNode *N) override;
48 const char *getPassName() const override;
49 void PostprocessISelDAG() override;
52 bool isInlineImmediate(SDNode *N) const;
53 inline SDValue getSmallIPtrImm(unsigned Imm);
54 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
55 const R600InstrInfo *TII);
56 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
57 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
59 // Complex pattern selectors
60 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
61 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
62 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
64 static bool checkType(const Value *ptr, unsigned int addrspace);
65 static bool checkPrivateAddress(const MachineMemOperand *Op);
67 static bool isGlobalStore(const StoreSDNode *N);
68 static bool isFlatStore(const StoreSDNode *N);
69 static bool isPrivateStore(const StoreSDNode *N);
70 static bool isLocalStore(const StoreSDNode *N);
71 static bool isRegionStore(const StoreSDNode *N);
73 bool isCPLoad(const LoadSDNode *N) const;
74 bool isConstantLoad(const LoadSDNode *N, int cbID) const;
75 bool isGlobalLoad(const LoadSDNode *N) const;
76 bool isFlatLoad(const LoadSDNode *N) const;
77 bool isParamLoad(const LoadSDNode *N) const;
78 bool isPrivateLoad(const LoadSDNode *N) const;
79 bool isLocalLoad(const LoadSDNode *N) const;
80 bool isRegionLoad(const LoadSDNode *N) const;
82 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
83 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
84 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
86 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
87 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
88 bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
89 unsigned OffsetBits) const;
90 bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
91 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
92 SDValue &Offset1) const;
93 void SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
94 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
95 SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
97 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
98 SDValue &Offset) const;
99 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
100 SDValue &VAddr, SDValue &Offset,
102 bool SelectMUBUFScratch(SDValue Addr, SDValue &RSrc, SDValue &VAddr,
103 SDValue &SOffset, SDValue &ImmOffset) const;
104 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
105 SDValue &Offset, SDValue &GLC, SDValue &SLC,
107 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
108 SDValue &Offset, SDValue &GLC) const;
109 SDNode *SelectAddrSpaceCast(SDNode *N);
110 bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
111 bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
112 SDValue &Clamp, SDValue &Omod) const;
114 SDNode *SelectADD_SUB_I64(SDNode *N);
115 SDNode *SelectDIV_SCALE(SDNode *N);
117 // Include the pieces autogenerated from the target description.
118 #include "AMDGPUGenDAGISel.inc"
120 } // end anonymous namespace
122 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
123 // DAG, ready for instruction scheduling.
124 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM) {
125 return new AMDGPUDAGToDAGISel(TM);
128 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
129 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
132 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
135 bool AMDGPUDAGToDAGISel::isInlineImmediate(SDNode *N) const {
136 const SITargetLowering *TL
137 = static_cast<const SITargetLowering *>(getTargetLowering());
138 return TL->analyzeImmediate(N) == 0;
141 /// \brief Determine the register class for \p OpNo
142 /// \returns The register class of the virtual register that will be used for
143 /// the given operand number \OpNo or NULL if the register class cannot be
145 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
146 unsigned OpNo) const {
147 if (!N->isMachineOpcode())
150 switch (N->getMachineOpcode()) {
152 const MCInstrDesc &Desc =
153 TM.getSubtargetImpl()->getInstrInfo()->get(N->getMachineOpcode());
154 unsigned OpIdx = Desc.getNumDefs() + OpNo;
155 if (OpIdx >= Desc.getNumOperands())
157 int RegClass = Desc.OpInfo[OpIdx].RegClass;
161 return TM.getSubtargetImpl()->getRegisterInfo()->getRegClass(RegClass);
163 case AMDGPU::REG_SEQUENCE: {
164 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
165 const TargetRegisterClass *SuperRC =
166 TM.getSubtargetImpl()->getRegisterInfo()->getRegClass(RCID);
168 SDValue SubRegOp = N->getOperand(OpNo + 1);
169 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
170 return TM.getSubtargetImpl()->getRegisterInfo()->getSubClassWithSubReg(
176 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
177 return CurDAG->getTargetConstant(Imm, MVT::i32);
180 bool AMDGPUDAGToDAGISel::SelectADDRParam(
181 SDValue Addr, SDValue& R1, SDValue& R2) {
183 if (Addr.getOpcode() == ISD::FrameIndex) {
184 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
185 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
186 R2 = CurDAG->getTargetConstant(0, MVT::i32);
189 R2 = CurDAG->getTargetConstant(0, MVT::i32);
191 } else if (Addr.getOpcode() == ISD::ADD) {
192 R1 = Addr.getOperand(0);
193 R2 = Addr.getOperand(1);
196 R2 = CurDAG->getTargetConstant(0, MVT::i32);
201 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
202 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
203 Addr.getOpcode() == ISD::TargetGlobalAddress) {
206 return SelectADDRParam(Addr, R1, R2);
210 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
211 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
212 Addr.getOpcode() == ISD::TargetGlobalAddress) {
216 if (Addr.getOpcode() == ISD::FrameIndex) {
217 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
218 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
219 R2 = CurDAG->getTargetConstant(0, MVT::i64);
222 R2 = CurDAG->getTargetConstant(0, MVT::i64);
224 } else if (Addr.getOpcode() == ISD::ADD) {
225 R1 = Addr.getOperand(0);
226 R2 = Addr.getOperand(1);
229 R2 = CurDAG->getTargetConstant(0, MVT::i64);
234 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
235 unsigned int Opc = N->getOpcode();
236 if (N->isMachineOpcode()) {
238 return nullptr; // Already selected.
241 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
244 // We are selecting i64 ADD here instead of custom lower it during
245 // DAG legalization, so we can fold some i64 ADDs used for address
246 // calculation into the LOAD and STORE instructions.
249 if (N->getValueType(0) != MVT::i64 ||
250 ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
253 return SelectADD_SUB_I64(N);
255 case ISD::SCALAR_TO_VECTOR:
256 case AMDGPUISD::BUILD_VERTICAL_VECTOR:
257 case ISD::BUILD_VECTOR: {
259 const AMDGPURegisterInfo *TRI = static_cast<const AMDGPURegisterInfo *>(
260 TM.getSubtargetImpl()->getRegisterInfo());
261 const SIRegisterInfo *SIRI = static_cast<const SIRegisterInfo *>(
262 TM.getSubtargetImpl()->getRegisterInfo());
263 EVT VT = N->getValueType(0);
264 unsigned NumVectorElts = VT.getVectorNumElements();
265 EVT EltVT = VT.getVectorElementType();
266 assert(EltVT.bitsEq(MVT::i32));
267 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
269 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
271 if (!U->isMachineOpcode()) {
274 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
278 if (SIRI->isSGPRClass(RC)) {
282 switch(NumVectorElts) {
283 case 1: RegClassID = UseVReg ? AMDGPU::VReg_32RegClassID :
284 AMDGPU::SReg_32RegClassID;
286 case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID :
287 AMDGPU::SReg_64RegClassID;
289 case 4: RegClassID = UseVReg ? AMDGPU::VReg_128RegClassID :
290 AMDGPU::SReg_128RegClassID;
292 case 8: RegClassID = UseVReg ? AMDGPU::VReg_256RegClassID :
293 AMDGPU::SReg_256RegClassID;
295 case 16: RegClassID = UseVReg ? AMDGPU::VReg_512RegClassID :
296 AMDGPU::SReg_512RegClassID;
298 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
301 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
302 // that adds a 128 bits reg copy when going through TwoAddressInstructions
303 // pass. We want to avoid 128 bits copies as much as possible because they
304 // can't be bundled by our scheduler.
305 switch(NumVectorElts) {
306 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
308 if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
309 RegClassID = AMDGPU::R600_Reg128VerticalRegClassID;
311 RegClassID = AMDGPU::R600_Reg128RegClassID;
313 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
317 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, MVT::i32);
319 if (NumVectorElts == 1) {
320 return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT,
321 N->getOperand(0), RegClass);
324 assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
326 // 16 = Max Num Vector Elements
327 // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
328 // 1 = Vector Register Class
329 SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
331 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, MVT::i32);
332 bool IsRegSeq = true;
333 unsigned NOps = N->getNumOperands();
334 for (unsigned i = 0; i < NOps; i++) {
335 // XXX: Why is this here?
336 if (dyn_cast<RegisterSDNode>(N->getOperand(i))) {
340 RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
341 RegSeqArgs[1 + (2 * i) + 1] =
342 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
345 if (NOps != NumVectorElts) {
346 // Fill in the missing undef elements if this was a scalar_to_vector.
347 assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
349 MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
351 for (unsigned i = NOps; i < NumVectorElts; ++i) {
352 RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
353 RegSeqArgs[1 + (2 * i) + 1] =
354 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
360 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
363 case ISD::BUILD_PAIR: {
364 SDValue RC, SubReg0, SubReg1;
365 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
368 if (N->getValueType(0) == MVT::i128) {
369 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
370 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
371 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
372 } else if (N->getValueType(0) == MVT::i64) {
373 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
374 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
375 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
377 llvm_unreachable("Unhandled value type for BUILD_PAIR");
379 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
380 N->getOperand(1), SubReg1 };
381 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
382 SDLoc(N), N->getValueType(0), Ops);
386 case ISD::ConstantFP: {
387 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
388 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
389 N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
393 if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
394 Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
396 ConstantSDNode *C = cast<ConstantSDNode>(N);
397 Imm = C->getZExtValue();
400 SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
401 CurDAG->getConstant(Imm & 0xFFFFFFFF, MVT::i32));
402 SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
403 CurDAG->getConstant(Imm >> 32, MVT::i32));
404 const SDValue Ops[] = {
405 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
406 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
407 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32)
410 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, SDLoc(N),
411 N->getValueType(0), Ops);
414 case AMDGPUISD::REGISTER_LOAD: {
415 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
417 SDValue Addr, Offset;
419 SelectADDRIndirect(N->getOperand(1), Addr, Offset);
420 const SDValue Ops[] = {
423 CurDAG->getTargetConstant(0, MVT::i32),
426 return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, SDLoc(N),
427 CurDAG->getVTList(MVT::i32, MVT::i64, MVT::Other),
430 case AMDGPUISD::REGISTER_STORE: {
431 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
433 SDValue Addr, Offset;
434 SelectADDRIndirect(N->getOperand(2), Addr, Offset);
435 const SDValue Ops[] = {
439 CurDAG->getTargetConstant(0, MVT::i32),
442 return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, SDLoc(N),
443 CurDAG->getVTList(MVT::Other),
447 case AMDGPUISD::BFE_I32:
448 case AMDGPUISD::BFE_U32: {
449 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
452 // There is a scalar version available, but unlike the vector version which
453 // has a separate operand for the offset and width, the scalar version packs
454 // the width and offset into a single operand. Try to move to the scalar
455 // version if the offsets are constant, so that we can try to keep extended
456 // loads of kernel arguments in SGPRs.
458 // TODO: Technically we could try to pattern match scalar bitshifts of
459 // dynamic values, but it's probably not useful.
460 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
464 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
468 bool Signed = Opc == AMDGPUISD::BFE_I32;
470 // Transformation function, pack the offset and width of a BFE into
471 // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
472 // source, bits [5:0] contain the offset and bits [22:16] the width.
474 uint32_t OffsetVal = Offset->getZExtValue();
475 uint32_t WidthVal = Width->getZExtValue();
477 uint32_t PackedVal = OffsetVal | WidthVal << 16;
479 SDValue PackedOffsetWidth = CurDAG->getTargetConstant(PackedVal, MVT::i32);
480 return CurDAG->getMachineNode(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32,
487 case AMDGPUISD::DIV_SCALE: {
488 return SelectDIV_SCALE(N);
490 case ISD::ADDRSPACECAST:
491 return SelectAddrSpaceCast(N);
493 return SelectCode(N);
497 bool AMDGPUDAGToDAGISel::checkType(const Value *Ptr, unsigned AS) {
498 assert(AS != 0 && "Use checkPrivateAddress instead.");
502 return Ptr->getType()->getPointerAddressSpace() == AS;
505 bool AMDGPUDAGToDAGISel::checkPrivateAddress(const MachineMemOperand *Op) {
506 if (Op->getPseudoValue())
509 if (PointerType *PT = dyn_cast<PointerType>(Op->getValue()->getType()))
510 return PT->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
515 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
516 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
519 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
520 const Value *MemVal = N->getMemOperand()->getValue();
521 return (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
522 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
523 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS));
526 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
527 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
530 bool AMDGPUDAGToDAGISel::isFlatStore(const StoreSDNode *N) {
531 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
534 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
535 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
538 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
539 const Value *MemVal = N->getMemOperand()->getValue();
541 return checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS);
543 return checkType(MemVal, AMDGPUAS::CONSTANT_BUFFER_0 + CbId);
546 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
547 if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) {
548 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
549 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
550 N->getMemoryVT().bitsLT(MVT::i32)) {
554 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
557 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
558 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::PARAM_I_ADDRESS);
561 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
562 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
565 bool AMDGPUDAGToDAGISel::isFlatLoad(const LoadSDNode *N) const {
566 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
569 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
570 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
573 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
574 MachineMemOperand *MMO = N->getMemOperand();
575 if (checkPrivateAddress(N->getMemOperand())) {
577 const PseudoSourceValue *PSV = MMO->getPseudoValue();
578 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
586 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
587 if (checkPrivateAddress(N->getMemOperand())) {
588 // Check to make sure we are not a constant pool load or a constant load
589 // that is marked as a private load
590 if (isCPLoad(N) || isConstantLoad(N, -1)) {
595 const Value *MemVal = N->getMemOperand()->getValue();
596 if (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
597 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
598 !checkType(MemVal, AMDGPUAS::FLAT_ADDRESS) &&
599 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS) &&
600 !checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) &&
601 !checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) &&
602 !checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS)) {
608 const char *AMDGPUDAGToDAGISel::getPassName() const {
609 return "AMDGPU DAG->DAG Pattern Instruction Selection";
617 //===----------------------------------------------------------------------===//
619 //===----------------------------------------------------------------------===//
621 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
623 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
624 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
630 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
631 SDValue& BaseReg, SDValue &Offset) {
632 if (!isa<ConstantSDNode>(Addr)) {
634 Offset = CurDAG->getIntPtrConstant(0, true);
640 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
642 ConstantSDNode *IMMOffset;
644 if (Addr.getOpcode() == ISD::ADD
645 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
646 && isInt<16>(IMMOffset->getZExtValue())) {
648 Base = Addr.getOperand(0);
649 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
651 // If the pointer address is constant, we can move it to the offset field.
652 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
653 && isInt<16>(IMMOffset->getZExtValue())) {
654 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
655 SDLoc(CurDAG->getEntryNode()),
656 AMDGPU::ZERO, MVT::i32);
657 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
661 // Default case, no offset
663 Offset = CurDAG->getTargetConstant(0, MVT::i32);
667 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
671 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
672 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
673 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
674 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
675 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
676 Base = Addr.getOperand(0);
677 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
680 Offset = CurDAG->getTargetConstant(0, MVT::i32);
686 SDNode *AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
688 SDValue LHS = N->getOperand(0);
689 SDValue RHS = N->getOperand(1);
691 bool IsAdd = (N->getOpcode() == ISD::ADD);
693 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
694 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
696 SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
697 DL, MVT::i32, LHS, Sub0);
698 SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
699 DL, MVT::i32, LHS, Sub1);
701 SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
702 DL, MVT::i32, RHS, Sub0);
703 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
704 DL, MVT::i32, RHS, Sub1);
706 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
707 SDValue AddLoArgs[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
710 unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
711 unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
713 SDNode *AddLo = CurDAG->getMachineNode( Opc, DL, VTList, AddLoArgs);
714 SDValue Carry(AddLo, 1);
716 = CurDAG->getMachineNode(CarryOpc, DL, MVT::i32,
717 SDValue(Hi0, 0), SDValue(Hi1, 0), Carry);
720 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
726 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args);
729 SDNode *AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
731 EVT VT = N->getValueType(0);
733 assert(VT == MVT::f32 || VT == MVT::f64);
736 = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
738 const SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
750 return CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
753 bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
754 unsigned OffsetBits) const {
755 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
756 if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
757 (OffsetBits == 8 && !isUInt<8>(Offset)))
760 if (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
763 // On Southern Islands instruction with a negative base value and an offset
764 // don't seem to work.
765 return CurDAG->SignBitIsZero(Base);
768 bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
769 SDValue &Offset) const {
770 if (CurDAG->isBaseWithConstantOffset(Addr)) {
771 SDValue N0 = Addr.getOperand(0);
772 SDValue N1 = Addr.getOperand(1);
773 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
774 if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
784 Offset = CurDAG->getTargetConstant(0, MVT::i16);
788 bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
790 SDValue &Offset1) const {
791 if (CurDAG->isBaseWithConstantOffset(Addr)) {
792 SDValue N0 = Addr.getOperand(0);
793 SDValue N1 = Addr.getOperand(1);
794 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
795 unsigned DWordOffset0 = C1->getZExtValue() / 4;
796 unsigned DWordOffset1 = DWordOffset0 + 1;
798 if (isDSOffsetLegal(N0, DWordOffset1, 8)) {
800 Offset0 = CurDAG->getTargetConstant(DWordOffset0, MVT::i8);
801 Offset1 = CurDAG->getTargetConstant(DWordOffset1, MVT::i8);
808 Offset0 = CurDAG->getTargetConstant(0, MVT::i8);
809 Offset1 = CurDAG->getTargetConstant(1, MVT::i8);
813 static SDValue wrapAddr64Rsrc(SelectionDAG *DAG, SDLoc DL, SDValue Ptr) {
814 return SDValue(DAG->getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::v4i32,
818 static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) {
819 return isUInt<12>(Imm->getZExtValue());
822 void AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
823 SDValue &VAddr, SDValue &SOffset,
824 SDValue &Offset, SDValue &Offen,
825 SDValue &Idxen, SDValue &Addr64,
826 SDValue &GLC, SDValue &SLC,
827 SDValue &TFE) const {
830 GLC = CurDAG->getTargetConstant(0, MVT::i1);
831 SLC = CurDAG->getTargetConstant(0, MVT::i1);
832 TFE = CurDAG->getTargetConstant(0, MVT::i1);
834 Idxen = CurDAG->getTargetConstant(0, MVT::i1);
835 Offen = CurDAG->getTargetConstant(0, MVT::i1);
836 Addr64 = CurDAG->getTargetConstant(0, MVT::i1);
837 SOffset = CurDAG->getTargetConstant(0, MVT::i32);
839 if (CurDAG->isBaseWithConstantOffset(Addr)) {
840 SDValue N0 = Addr.getOperand(0);
841 SDValue N1 = Addr.getOperand(1);
842 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
844 if (isLegalMUBUFImmOffset(C1)) {
846 if (N0.getOpcode() == ISD::ADD) {
847 // (add (add N2, N3), C1) -> addr64
848 SDValue N2 = N0.getOperand(0);
849 SDValue N3 = N0.getOperand(1);
850 Addr64 = CurDAG->getTargetConstant(1, MVT::i1);
853 Offset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
857 // (add N0, C1) -> offset
858 VAddr = CurDAG->getTargetConstant(0, MVT::i32);
860 Offset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
864 if (Addr.getOpcode() == ISD::ADD) {
865 // (add N0, N1) -> addr64
866 SDValue N0 = Addr.getOperand(0);
867 SDValue N1 = Addr.getOperand(1);
868 Addr64 = CurDAG->getTargetConstant(1, MVT::i1);
871 Offset = CurDAG->getTargetConstant(0, MVT::i16);
875 // default case -> offset
876 VAddr = CurDAG->getTargetConstant(0, MVT::i32);
878 Offset = CurDAG->getTargetConstant(0, MVT::i16);
882 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
884 SDValue &Offset) const {
885 SDValue Ptr, SOffset, Offen, Idxen, Addr64, GLC, SLC, TFE;
887 SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
890 ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
891 if (C->getSExtValue()) {
893 SRsrc = wrapAddr64Rsrc(CurDAG, DL, Ptr);
899 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
900 SDValue &VAddr, SDValue &Offset,
901 SDValue &SLC) const {
902 SLC = CurDAG->getTargetConstant(0, MVT::i1);
904 return SelectMUBUFAddr64(Addr, SRsrc, VAddr, Offset);
907 static SDValue buildRSRC(SelectionDAG *DAG, SDLoc DL, SDValue Ptr,
908 uint32_t RsrcDword1, uint64_t RsrcDword2And3) {
910 SDValue PtrLo = DAG->getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
911 SDValue PtrHi = DAG->getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
913 PtrHi = SDValue(DAG->getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
914 DAG->getConstant(RsrcDword1, MVT::i32)), 0);
916 SDValue DataLo = DAG->getTargetConstant(
917 RsrcDword2And3 & APInt::getAllOnesValue(32).getZExtValue(), MVT::i32);
918 SDValue DataHi = DAG->getTargetConstant(RsrcDword2And3 >> 32, MVT::i32);
920 const SDValue Ops[] = { PtrLo, PtrHi, DataLo, DataHi };
921 return SDValue(DAG->getMachineNode(AMDGPU::SI_BUFFER_RSRC, DL,
922 MVT::v4i32, Ops), 0);
925 /// \brief Return a resource descriptor with the 'Add TID' bit enabled
926 /// The TID (Thread ID) is multipled by the stride value (bits [61:48]
927 /// of the resource descriptor) to create an offset, which is added to the
929 static SDValue buildScratchRSRC(SelectionDAG *DAG, SDLoc DL, SDValue Ptr) {
931 uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE |
934 return buildRSRC(DAG, DL, Ptr, 0, Rsrc);
937 bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
938 SDValue &VAddr, SDValue &SOffset,
939 SDValue &ImmOffset) const {
942 MachineFunction &MF = CurDAG->getMachineFunction();
943 const SIRegisterInfo *TRI =
944 static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
945 MachineRegisterInfo &MRI = MF.getRegInfo();
946 const SITargetLowering& Lowering =
947 *static_cast<const SITargetLowering*>(getTargetLowering());
949 unsigned ScratchPtrReg =
950 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
951 unsigned ScratchOffsetReg =
952 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET);
953 Lowering.CreateLiveInRegister(*CurDAG, &AMDGPU::SReg_32RegClass,
954 ScratchOffsetReg, MVT::i32);
956 Rsrc = buildScratchRSRC(CurDAG, DL,
957 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
958 MRI.getLiveInVirtReg(ScratchPtrReg), MVT::i64));
959 SOffset = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
960 MRI.getLiveInVirtReg(ScratchOffsetReg), MVT::i32);
963 if (CurDAG->isBaseWithConstantOffset(Addr)) {
964 SDValue N1 = Addr.getOperand(1);
965 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
967 if (isLegalMUBUFImmOffset(C1)) {
968 VAddr = Addr.getOperand(0);
969 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
975 if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
976 isa<FrameIndexSDNode>(Addr.getOperand(0))) {
977 VAddr = Addr.getOperand(1);
978 ImmOffset = Addr.getOperand(0);
983 if (isa<FrameIndexSDNode>(Addr)) {
984 VAddr = SDValue(CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32, DL, MVT::i32,
985 CurDAG->getConstant(0, MVT::i32)), 0);
992 ImmOffset = CurDAG->getTargetConstant(0, MVT::i16);
996 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
997 SDValue &SOffset, SDValue &Offset,
998 SDValue &GLC, SDValue &SLC,
999 SDValue &TFE) const {
1000 SDValue Ptr, VAddr, Offen, Idxen, Addr64;
1002 SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1005 if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
1006 !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
1007 !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
1008 uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT |
1009 APInt::getAllOnesValue(32).getZExtValue(); // Size
1011 SRsrc = buildRSRC(CurDAG, DL, Ptr, 0, Rsrc);
1017 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1018 SDValue &Soffset, SDValue &Offset,
1019 SDValue &GLC) const {
1022 return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
1025 // FIXME: This is incorrect and only enough to be able to compile.
1026 SDNode *AMDGPUDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
1027 AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(N);
1030 assert(Subtarget.hasFlatAddressSpace() &&
1031 "addrspacecast only supported with flat address space!");
1033 assert((ASC->getSrcAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS &&
1034 ASC->getDestAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS) &&
1035 "Cannot cast address space to / from constant address!");
1037 assert((ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS ||
1038 ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) &&
1039 "Can only cast to / from flat address space!");
1041 // The flat instructions read the address as the index of the VGPR holding the
1042 // address, so casting should just be reinterpreting the base VGPR, so just
1043 // insert trunc / bitcast / zext.
1045 SDValue Src = ASC->getOperand(0);
1046 EVT DestVT = ASC->getValueType(0);
1047 EVT SrcVT = Src.getValueType();
1049 unsigned SrcSize = SrcVT.getSizeInBits();
1050 unsigned DestSize = DestVT.getSizeInBits();
1052 if (SrcSize > DestSize) {
1053 assert(SrcSize == 64 && DestSize == 32);
1054 return CurDAG->getMachineNode(
1055 TargetOpcode::EXTRACT_SUBREG,
1059 CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32));
1063 if (DestSize > SrcSize) {
1064 assert(SrcSize == 32 && DestSize == 64);
1066 SDValue RC = CurDAG->getTargetConstant(AMDGPU::VSrc_64RegClassID, MVT::i32);
1068 const SDValue Ops[] = {
1071 CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
1072 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
1073 CurDAG->getConstant(0, MVT::i32)), 0),
1074 CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32)
1077 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
1078 SDLoc(N), N->getValueType(0), Ops);
1081 assert(SrcSize == 64 && DestSize == 64);
1082 return CurDAG->getNode(ISD::BITCAST, DL, DestVT, Src).getNode();
1085 bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
1086 SDValue &SrcMods) const {
1092 if (Src.getOpcode() == ISD::FNEG) {
1093 Mods |= SISrcMods::NEG;
1094 Src = Src.getOperand(0);
1097 if (Src.getOpcode() == ISD::FABS) {
1098 Mods |= SISrcMods::ABS;
1099 Src = Src.getOperand(0);
1102 SrcMods = CurDAG->getTargetConstant(Mods, MVT::i32);
1107 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
1108 SDValue &SrcMods, SDValue &Clamp,
1109 SDValue &Omod) const {
1110 // FIXME: Handle Clamp and Omod
1111 Clamp = CurDAG->getTargetConstant(0, MVT::i32);
1112 Omod = CurDAG->getTargetConstant(0, MVT::i32);
1114 return SelectVOP3Mods(In, Src, SrcMods);
1117 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
1118 const AMDGPUTargetLowering& Lowering =
1119 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
1120 bool IsModified = false;
1123 // Go over all selected nodes and try to fold them a bit more
1124 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
1125 E = CurDAG->allnodes_end(); I != E; ++I) {
1129 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
1133 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
1134 if (ResNode != Node) {
1135 ReplaceUses(Node, ResNode);
1139 CurDAG->RemoveDeadNodes();
1140 } while (IsModified);