1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "AMDGPUSubtarget.h"
18 #include "R600InstrInfo.h"
19 #include "SIDefines.h"
20 #include "SIISelLowering.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/CodeGen/FunctionLoweringInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/IR/Function.h"
32 //===----------------------------------------------------------------------===//
33 // Instruction Selector Implementation
34 //===----------------------------------------------------------------------===//
37 /// AMDGPU specific code to select AMDGPU machine instructions for
38 /// SelectionDAG operations.
39 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
40 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
41 // make the right decision when generating code for different targets.
42 const AMDGPUSubtarget *Subtarget;
44 AMDGPUDAGToDAGISel(TargetMachine &TM);
45 virtual ~AMDGPUDAGToDAGISel();
46 bool runOnMachineFunction(MachineFunction &MF) override;
47 SDNode *Select(SDNode *N) override;
48 const char *getPassName() const override;
49 void PostprocessISelDAG() override;
52 bool isInlineImmediate(SDNode *N) const;
53 inline SDValue getSmallIPtrImm(unsigned Imm);
54 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
55 const R600InstrInfo *TII);
56 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
57 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
59 // Complex pattern selectors
60 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
61 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
62 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
64 static bool checkType(const Value *ptr, unsigned int addrspace);
65 static bool checkPrivateAddress(const MachineMemOperand *Op);
67 static bool isGlobalStore(const StoreSDNode *N);
68 static bool isFlatStore(const StoreSDNode *N);
69 static bool isPrivateStore(const StoreSDNode *N);
70 static bool isLocalStore(const StoreSDNode *N);
71 static bool isRegionStore(const StoreSDNode *N);
73 bool isCPLoad(const LoadSDNode *N) const;
74 bool isConstantLoad(const LoadSDNode *N, int cbID) const;
75 bool isGlobalLoad(const LoadSDNode *N) const;
76 bool isFlatLoad(const LoadSDNode *N) const;
77 bool isParamLoad(const LoadSDNode *N) const;
78 bool isPrivateLoad(const LoadSDNode *N) const;
79 bool isLocalLoad(const LoadSDNode *N) const;
80 bool isRegionLoad(const LoadSDNode *N) const;
82 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
83 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
84 bool SelectGlobalValueVariableOffset(SDValue Addr, SDValue &BaseReg,
86 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
87 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
88 bool isDSOffsetLegal(const SDValue &Base, unsigned Offset,
89 unsigned OffsetBits) const;
90 bool SelectDS1Addr1Offset(SDValue Ptr, SDValue &Base, SDValue &Offset) const;
91 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0,
92 SDValue &Offset1) const;
93 void SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
94 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
95 SDValue &Idxen, SDValue &Addr64, SDValue &GLC, SDValue &SLC,
97 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
98 SDValue &SOffset, SDValue &Offset) const;
99 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
100 SDValue &VAddr, SDValue &SOffset, SDValue &Offset,
102 bool SelectMUBUFScratch(SDValue Addr, SDValue &RSrc, SDValue &VAddr,
103 SDValue &SOffset, SDValue &ImmOffset) const;
104 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
105 SDValue &Offset, SDValue &GLC, SDValue &SLC,
107 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
108 SDValue &Offset, SDValue &GLC) const;
109 SDNode *SelectAddrSpaceCast(SDNode *N);
110 bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
111 bool SelectVOP3Mods0(SDValue In, SDValue &Src, SDValue &SrcMods,
112 SDValue &Clamp, SDValue &Omod) const;
114 bool SelectVOP3Mods0Clamp(SDValue In, SDValue &Src, SDValue &SrcMods,
115 SDValue &Omod) const;
116 bool SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src, SDValue &SrcMods,
118 SDValue &Omod) const;
120 SDNode *SelectADD_SUB_I64(SDNode *N);
121 SDNode *SelectDIV_SCALE(SDNode *N);
123 // Include the pieces autogenerated from the target description.
124 #include "AMDGPUGenDAGISel.inc"
126 } // end anonymous namespace
128 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
129 // DAG, ready for instruction scheduling.
130 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM) {
131 return new AMDGPUDAGToDAGISel(TM);
134 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
135 : SelectionDAGISel(TM) {}
137 bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
138 Subtarget = &static_cast<const AMDGPUSubtarget &>(MF.getSubtarget());
139 return SelectionDAGISel::runOnMachineFunction(MF);
142 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
145 bool AMDGPUDAGToDAGISel::isInlineImmediate(SDNode *N) const {
146 const SITargetLowering *TL
147 = static_cast<const SITargetLowering *>(getTargetLowering());
148 return TL->analyzeImmediate(N) == 0;
151 /// \brief Determine the register class for \p OpNo
152 /// \returns The register class of the virtual register that will be used for
153 /// the given operand number \OpNo or NULL if the register class cannot be
155 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
156 unsigned OpNo) const {
157 if (!N->isMachineOpcode())
160 switch (N->getMachineOpcode()) {
162 const MCInstrDesc &Desc =
163 Subtarget->getInstrInfo()->get(N->getMachineOpcode());
164 unsigned OpIdx = Desc.getNumDefs() + OpNo;
165 if (OpIdx >= Desc.getNumOperands())
167 int RegClass = Desc.OpInfo[OpIdx].RegClass;
171 return Subtarget->getRegisterInfo()->getRegClass(RegClass);
173 case AMDGPU::REG_SEQUENCE: {
174 unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
175 const TargetRegisterClass *SuperRC =
176 Subtarget->getRegisterInfo()->getRegClass(RCID);
178 SDValue SubRegOp = N->getOperand(OpNo + 1);
179 unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
180 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
186 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
187 return CurDAG->getTargetConstant(Imm, MVT::i32);
190 bool AMDGPUDAGToDAGISel::SelectADDRParam(
191 SDValue Addr, SDValue& R1, SDValue& R2) {
193 if (Addr.getOpcode() == ISD::FrameIndex) {
194 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
195 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
196 R2 = CurDAG->getTargetConstant(0, MVT::i32);
199 R2 = CurDAG->getTargetConstant(0, MVT::i32);
201 } else if (Addr.getOpcode() == ISD::ADD) {
202 R1 = Addr.getOperand(0);
203 R2 = Addr.getOperand(1);
206 R2 = CurDAG->getTargetConstant(0, MVT::i32);
211 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
212 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
213 Addr.getOpcode() == ISD::TargetGlobalAddress) {
216 return SelectADDRParam(Addr, R1, R2);
220 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
221 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
222 Addr.getOpcode() == ISD::TargetGlobalAddress) {
226 if (Addr.getOpcode() == ISD::FrameIndex) {
227 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
228 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
229 R2 = CurDAG->getTargetConstant(0, MVT::i64);
232 R2 = CurDAG->getTargetConstant(0, MVT::i64);
234 } else if (Addr.getOpcode() == ISD::ADD) {
235 R1 = Addr.getOperand(0);
236 R2 = Addr.getOperand(1);
239 R2 = CurDAG->getTargetConstant(0, MVT::i64);
244 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
245 unsigned int Opc = N->getOpcode();
246 if (N->isMachineOpcode()) {
248 return nullptr; // Already selected.
253 // We are selecting i64 ADD here instead of custom lower it during
254 // DAG legalization, so we can fold some i64 ADDs used for address
255 // calculation into the LOAD and STORE instructions.
258 if (N->getValueType(0) != MVT::i64 ||
259 Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
262 return SelectADD_SUB_I64(N);
264 case ISD::SCALAR_TO_VECTOR:
265 case AMDGPUISD::BUILD_VERTICAL_VECTOR:
266 case ISD::BUILD_VECTOR: {
268 const AMDGPURegisterInfo *TRI = Subtarget->getRegisterInfo();
269 EVT VT = N->getValueType(0);
270 unsigned NumVectorElts = VT.getVectorNumElements();
271 EVT EltVT = VT.getVectorElementType();
272 assert(EltVT.bitsEq(MVT::i32));
273 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
275 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
277 if (!U->isMachineOpcode()) {
280 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
284 if (static_cast<const SIRegisterInfo *>(TRI)->isSGPRClass(RC)) {
288 switch(NumVectorElts) {
289 case 1: RegClassID = UseVReg ? AMDGPU::VGPR_32RegClassID :
290 AMDGPU::SReg_32RegClassID;
292 case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID :
293 AMDGPU::SReg_64RegClassID;
295 case 4: RegClassID = UseVReg ? AMDGPU::VReg_128RegClassID :
296 AMDGPU::SReg_128RegClassID;
298 case 8: RegClassID = UseVReg ? AMDGPU::VReg_256RegClassID :
299 AMDGPU::SReg_256RegClassID;
301 case 16: RegClassID = UseVReg ? AMDGPU::VReg_512RegClassID :
302 AMDGPU::SReg_512RegClassID;
304 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
307 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
308 // that adds a 128 bits reg copy when going through TwoAddressInstructions
309 // pass. We want to avoid 128 bits copies as much as possible because they
310 // can't be bundled by our scheduler.
311 switch(NumVectorElts) {
312 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
314 if (Opc == AMDGPUISD::BUILD_VERTICAL_VECTOR)
315 RegClassID = AMDGPU::R600_Reg128VerticalRegClassID;
317 RegClassID = AMDGPU::R600_Reg128RegClassID;
319 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
323 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, MVT::i32);
325 if (NumVectorElts == 1) {
326 return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS, EltVT,
327 N->getOperand(0), RegClass);
330 assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
332 // 16 = Max Num Vector Elements
333 // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
334 // 1 = Vector Register Class
335 SmallVector<SDValue, 16 * 2 + 1> RegSeqArgs(NumVectorElts * 2 + 1);
337 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, MVT::i32);
338 bool IsRegSeq = true;
339 unsigned NOps = N->getNumOperands();
340 for (unsigned i = 0; i < NOps; i++) {
341 // XXX: Why is this here?
342 if (dyn_cast<RegisterSDNode>(N->getOperand(i))) {
346 RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
347 RegSeqArgs[1 + (2 * i) + 1] =
348 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
351 if (NOps != NumVectorElts) {
352 // Fill in the missing undef elements if this was a scalar_to_vector.
353 assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
355 MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
357 for (unsigned i = NOps; i < NumVectorElts; ++i) {
358 RegSeqArgs[1 + (2 * i)] = SDValue(ImpDef, 0);
359 RegSeqArgs[1 + (2 * i) + 1] =
360 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
366 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
369 case ISD::BUILD_PAIR: {
370 SDValue RC, SubReg0, SubReg1;
371 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
374 if (N->getValueType(0) == MVT::i128) {
375 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
376 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
377 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
378 } else if (N->getValueType(0) == MVT::i64) {
379 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
380 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
381 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
383 llvm_unreachable("Unhandled value type for BUILD_PAIR");
385 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
386 N->getOperand(1), SubReg1 };
387 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
388 SDLoc(N), N->getValueType(0), Ops);
392 case ISD::ConstantFP: {
393 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
394 N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
398 if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
399 Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
401 ConstantSDNode *C = cast<ConstantSDNode>(N);
402 Imm = C->getZExtValue();
405 SDNode *Lo = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
406 CurDAG->getConstant(Imm & 0xFFFFFFFF, MVT::i32));
407 SDNode *Hi = CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
408 CurDAG->getConstant(Imm >> 32, MVT::i32));
409 const SDValue Ops[] = {
410 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
411 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
412 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32)
415 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, SDLoc(N),
416 N->getValueType(0), Ops);
420 // To simplify the TableGen patters, we replace all i64 loads with
421 // v2i32 loads. Alternatively, we could promote i64 loads to v2i32
422 // during DAG legalization, however, so places (ExpandUnalignedLoad)
423 // in the DAG legalizer assume that if i64 is legal, so doing this
424 // promotion early can cause problems.
425 EVT VT = N->getValueType(0);
426 LoadSDNode *LD = cast<LoadSDNode>(N);
427 if (VT != MVT::i64 || LD->getExtensionType() != ISD::NON_EXTLOAD)
430 SDValue NewLoad = CurDAG->getLoad(MVT::v2i32, SDLoc(N), LD->getChain(),
431 LD->getBasePtr(), LD->getMemOperand());
432 SDValue BitCast = CurDAG->getNode(ISD::BITCAST, SDLoc(N),
434 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLoad.getValue(1));
435 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), BitCast);
436 SelectCode(NewLoad.getNode());
437 N = BitCast.getNode();
442 // Handle i64 stores here for the same reason mentioned above for loads.
443 StoreSDNode *ST = cast<StoreSDNode>(N);
444 SDValue Value = ST->getValue();
445 if (Value.getValueType() != MVT::i64 || ST->isTruncatingStore())
448 SDValue NewValue = CurDAG->getNode(ISD::BITCAST, SDLoc(N),
450 SDValue NewStore = CurDAG->getStore(ST->getChain(), SDLoc(N), NewValue,
451 ST->getBasePtr(), ST->getMemOperand());
453 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), NewStore);
455 if (NewValue.getOpcode() == ISD::BITCAST) {
456 Select(NewStore.getNode());
457 return SelectCode(NewValue.getNode());
460 // getNode() may fold the bitcast if its input was another bitcast. If that
461 // happens we should only select the new store.
462 N = NewStore.getNode();
466 case AMDGPUISD::REGISTER_LOAD: {
467 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
469 SDValue Addr, Offset;
471 SelectADDRIndirect(N->getOperand(1), Addr, Offset);
472 const SDValue Ops[] = {
475 CurDAG->getTargetConstant(0, MVT::i32),
478 return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, SDLoc(N),
479 CurDAG->getVTList(MVT::i32, MVT::i64, MVT::Other),
482 case AMDGPUISD::REGISTER_STORE: {
483 if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
485 SDValue Addr, Offset;
486 SelectADDRIndirect(N->getOperand(2), Addr, Offset);
487 const SDValue Ops[] = {
491 CurDAG->getTargetConstant(0, MVT::i32),
494 return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, SDLoc(N),
495 CurDAG->getVTList(MVT::Other),
499 case AMDGPUISD::BFE_I32:
500 case AMDGPUISD::BFE_U32: {
501 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
504 // There is a scalar version available, but unlike the vector version which
505 // has a separate operand for the offset and width, the scalar version packs
506 // the width and offset into a single operand. Try to move to the scalar
507 // version if the offsets are constant, so that we can try to keep extended
508 // loads of kernel arguments in SGPRs.
510 // TODO: Technically we could try to pattern match scalar bitshifts of
511 // dynamic values, but it's probably not useful.
512 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
516 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
520 bool Signed = Opc == AMDGPUISD::BFE_I32;
522 // Transformation function, pack the offset and width of a BFE into
523 // the format expected by the S_BFE_I32 / S_BFE_U32. In the second
524 // source, bits [5:0] contain the offset and bits [22:16] the width.
526 uint32_t OffsetVal = Offset->getZExtValue();
527 uint32_t WidthVal = Width->getZExtValue();
529 uint32_t PackedVal = OffsetVal | WidthVal << 16;
531 SDValue PackedOffsetWidth = CurDAG->getTargetConstant(PackedVal, MVT::i32);
532 return CurDAG->getMachineNode(Signed ? AMDGPU::S_BFE_I32 : AMDGPU::S_BFE_U32,
539 case AMDGPUISD::DIV_SCALE: {
540 return SelectDIV_SCALE(N);
542 case ISD::CopyToReg: {
543 const SITargetLowering& Lowering =
544 *static_cast<const SITargetLowering*>(getTargetLowering());
545 Lowering.legalizeTargetIndependentNode(N, *CurDAG);
548 case ISD::ADDRSPACECAST:
549 return SelectAddrSpaceCast(N);
552 return SelectCode(N);
556 bool AMDGPUDAGToDAGISel::checkType(const Value *Ptr, unsigned AS) {
557 assert(AS != 0 && "Use checkPrivateAddress instead.");
561 return Ptr->getType()->getPointerAddressSpace() == AS;
564 bool AMDGPUDAGToDAGISel::checkPrivateAddress(const MachineMemOperand *Op) {
565 if (Op->getPseudoValue())
568 if (PointerType *PT = dyn_cast<PointerType>(Op->getValue()->getType()))
569 return PT->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
574 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
575 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
578 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
579 const Value *MemVal = N->getMemOperand()->getValue();
580 return (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
581 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
582 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS));
585 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
586 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
589 bool AMDGPUDAGToDAGISel::isFlatStore(const StoreSDNode *N) {
590 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
593 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
594 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
597 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
598 const Value *MemVal = N->getMemOperand()->getValue();
600 return checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS);
602 return checkType(MemVal, AMDGPUAS::CONSTANT_BUFFER_0 + CbId);
605 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
606 if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS)
607 if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
608 N->getMemoryVT().bitsLT(MVT::i32))
611 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
614 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
615 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::PARAM_I_ADDRESS);
618 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
619 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::LOCAL_ADDRESS);
622 bool AMDGPUDAGToDAGISel::isFlatLoad(const LoadSDNode *N) const {
623 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::FLAT_ADDRESS);
626 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
627 return checkType(N->getMemOperand()->getValue(), AMDGPUAS::REGION_ADDRESS);
630 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
631 MachineMemOperand *MMO = N->getMemOperand();
632 if (checkPrivateAddress(N->getMemOperand())) {
634 const PseudoSourceValue *PSV = MMO->getPseudoValue();
635 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
643 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
644 if (checkPrivateAddress(N->getMemOperand())) {
645 // Check to make sure we are not a constant pool load or a constant load
646 // that is marked as a private load
647 if (isCPLoad(N) || isConstantLoad(N, -1)) {
652 const Value *MemVal = N->getMemOperand()->getValue();
653 if (!checkType(MemVal, AMDGPUAS::LOCAL_ADDRESS) &&
654 !checkType(MemVal, AMDGPUAS::GLOBAL_ADDRESS) &&
655 !checkType(MemVal, AMDGPUAS::FLAT_ADDRESS) &&
656 !checkType(MemVal, AMDGPUAS::REGION_ADDRESS) &&
657 !checkType(MemVal, AMDGPUAS::CONSTANT_ADDRESS) &&
658 !checkType(MemVal, AMDGPUAS::PARAM_D_ADDRESS) &&
659 !checkType(MemVal, AMDGPUAS::PARAM_I_ADDRESS)) {
665 const char *AMDGPUDAGToDAGISel::getPassName() const {
666 return "AMDGPU DAG->DAG Pattern Instruction Selection";
674 //===----------------------------------------------------------------------===//
676 //===----------------------------------------------------------------------===//
678 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
680 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
681 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
687 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
688 SDValue& BaseReg, SDValue &Offset) {
689 if (!isa<ConstantSDNode>(Addr)) {
691 Offset = CurDAG->getIntPtrConstant(0, true);
697 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
699 ConstantSDNode *IMMOffset;
701 if (Addr.getOpcode() == ISD::ADD
702 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
703 && isInt<16>(IMMOffset->getZExtValue())) {
705 Base = Addr.getOperand(0);
706 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
708 // If the pointer address is constant, we can move it to the offset field.
709 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
710 && isInt<16>(IMMOffset->getZExtValue())) {
711 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
712 SDLoc(CurDAG->getEntryNode()),
713 AMDGPU::ZERO, MVT::i32);
714 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
718 // Default case, no offset
720 Offset = CurDAG->getTargetConstant(0, MVT::i32);
724 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
728 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
729 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
730 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
731 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
732 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
733 Base = Addr.getOperand(0);
734 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
737 Offset = CurDAG->getTargetConstant(0, MVT::i32);
743 SDNode *AMDGPUDAGToDAGISel::SelectADD_SUB_I64(SDNode *N) {
745 SDValue LHS = N->getOperand(0);
746 SDValue RHS = N->getOperand(1);
748 bool IsAdd = (N->getOpcode() == ISD::ADD);
750 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
751 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
753 SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
754 DL, MVT::i32, LHS, Sub0);
755 SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
756 DL, MVT::i32, LHS, Sub1);
758 SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
759 DL, MVT::i32, RHS, Sub0);
760 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
761 DL, MVT::i32, RHS, Sub1);
763 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
764 SDValue AddLoArgs[] = { SDValue(Lo0, 0), SDValue(Lo1, 0) };
767 unsigned Opc = IsAdd ? AMDGPU::S_ADD_U32 : AMDGPU::S_SUB_U32;
768 unsigned CarryOpc = IsAdd ? AMDGPU::S_ADDC_U32 : AMDGPU::S_SUBB_U32;
770 SDNode *AddLo = CurDAG->getMachineNode( Opc, DL, VTList, AddLoArgs);
771 SDValue Carry(AddLo, 1);
773 = CurDAG->getMachineNode(CarryOpc, DL, MVT::i32,
774 SDValue(Hi0, 0), SDValue(Hi1, 0), Carry);
777 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
783 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args);
786 // We need to handle this here because tablegen doesn't support matching
787 // instructions with multiple outputs.
788 SDNode *AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
790 EVT VT = N->getValueType(0);
792 assert(VT == MVT::f32 || VT == MVT::f64);
795 = (VT == MVT::f64) ? AMDGPU::V_DIV_SCALE_F64 : AMDGPU::V_DIV_SCALE_F32;
797 // src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp, omod
800 SelectVOP3Mods0(N->getOperand(0), Ops[1], Ops[0], Ops[6], Ops[7]);
801 SelectVOP3Mods(N->getOperand(1), Ops[3], Ops[2]);
802 SelectVOP3Mods(N->getOperand(2), Ops[5], Ops[4]);
803 return CurDAG->SelectNodeTo(N, Opc, VT, MVT::i1, Ops);
806 bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
807 unsigned OffsetBits) const {
808 if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
809 (OffsetBits == 8 && !isUInt<8>(Offset)))
812 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
815 // On Southern Islands instruction with a negative base value and an offset
816 // don't seem to work.
817 return CurDAG->SignBitIsZero(Base);
820 bool AMDGPUDAGToDAGISel::SelectDS1Addr1Offset(SDValue Addr, SDValue &Base,
821 SDValue &Offset) const {
822 if (CurDAG->isBaseWithConstantOffset(Addr)) {
823 SDValue N0 = Addr.getOperand(0);
824 SDValue N1 = Addr.getOperand(1);
825 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
826 if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
834 // If we have a constant address, prefer to put the constant into the
835 // offset. This can save moves to load the constant address since multiple
836 // operations can share the zero base address register, and enables merging
837 // into read2 / write2 instructions.
838 if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
839 if (isUInt<16>(CAddr->getZExtValue())) {
840 SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
841 MachineSDNode *MovZero = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
842 SDLoc(Addr), MVT::i32, Zero);
843 Base = SDValue(MovZero, 0);
851 Offset = CurDAG->getTargetConstant(0, MVT::i16);
855 bool AMDGPUDAGToDAGISel::SelectDS64Bit4ByteAligned(SDValue Addr, SDValue &Base,
857 SDValue &Offset1) const {
858 if (CurDAG->isBaseWithConstantOffset(Addr)) {
859 SDValue N0 = Addr.getOperand(0);
860 SDValue N1 = Addr.getOperand(1);
861 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
862 unsigned DWordOffset0 = C1->getZExtValue() / 4;
863 unsigned DWordOffset1 = DWordOffset0 + 1;
865 if (isDSOffsetLegal(N0, DWordOffset1, 8)) {
867 Offset0 = CurDAG->getTargetConstant(DWordOffset0, MVT::i8);
868 Offset1 = CurDAG->getTargetConstant(DWordOffset1, MVT::i8);
873 if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
874 unsigned DWordOffset0 = CAddr->getZExtValue() / 4;
875 unsigned DWordOffset1 = DWordOffset0 + 1;
876 assert(4 * DWordOffset0 == CAddr->getZExtValue());
878 if (isUInt<8>(DWordOffset0) && isUInt<8>(DWordOffset1)) {
879 SDValue Zero = CurDAG->getTargetConstant(0, MVT::i32);
880 MachineSDNode *MovZero
881 = CurDAG->getMachineNode(AMDGPU::V_MOV_B32_e32,
882 SDLoc(Addr), MVT::i32, Zero);
883 Base = SDValue(MovZero, 0);
884 Offset0 = CurDAG->getTargetConstant(DWordOffset0, MVT::i8);
885 Offset1 = CurDAG->getTargetConstant(DWordOffset1, MVT::i8);
892 Offset0 = CurDAG->getTargetConstant(0, MVT::i8);
893 Offset1 = CurDAG->getTargetConstant(1, MVT::i8);
897 static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) {
898 return isUInt<12>(Imm->getZExtValue());
901 void AMDGPUDAGToDAGISel::SelectMUBUF(SDValue Addr, SDValue &Ptr,
902 SDValue &VAddr, SDValue &SOffset,
903 SDValue &Offset, SDValue &Offen,
904 SDValue &Idxen, SDValue &Addr64,
905 SDValue &GLC, SDValue &SLC,
906 SDValue &TFE) const {
909 GLC = CurDAG->getTargetConstant(0, MVT::i1);
910 SLC = CurDAG->getTargetConstant(0, MVT::i1);
911 TFE = CurDAG->getTargetConstant(0, MVT::i1);
913 Idxen = CurDAG->getTargetConstant(0, MVT::i1);
914 Offen = CurDAG->getTargetConstant(0, MVT::i1);
915 Addr64 = CurDAG->getTargetConstant(0, MVT::i1);
916 SOffset = CurDAG->getTargetConstant(0, MVT::i32);
918 if (CurDAG->isBaseWithConstantOffset(Addr)) {
919 SDValue N0 = Addr.getOperand(0);
920 SDValue N1 = Addr.getOperand(1);
921 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
923 if (N0.getOpcode() == ISD::ADD) {
924 // (add (add N2, N3), C1) -> addr64
925 SDValue N2 = N0.getOperand(0);
926 SDValue N3 = N0.getOperand(1);
927 Addr64 = CurDAG->getTargetConstant(1, MVT::i1);
932 // (add N0, C1) -> offset
933 VAddr = CurDAG->getTargetConstant(0, MVT::i32);
937 if (isLegalMUBUFImmOffset(C1)) {
938 Offset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
940 } else if (isUInt<32>(C1->getZExtValue())) {
941 // Illegal offset, store it in soffset.
942 Offset = CurDAG->getTargetConstant(0, MVT::i16);
943 SOffset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32,
944 CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i32)), 0);
949 if (Addr.getOpcode() == ISD::ADD) {
950 // (add N0, N1) -> addr64
951 SDValue N0 = Addr.getOperand(0);
952 SDValue N1 = Addr.getOperand(1);
953 Addr64 = CurDAG->getTargetConstant(1, MVT::i1);
956 Offset = CurDAG->getTargetConstant(0, MVT::i16);
960 // default case -> offset
961 VAddr = CurDAG->getTargetConstant(0, MVT::i32);
963 Offset = CurDAG->getTargetConstant(0, MVT::i16);
967 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
968 SDValue &VAddr, SDValue &SOffset,
969 SDValue &Offset) const {
970 SDValue Ptr, Offen, Idxen, Addr64, GLC, SLC, TFE;
972 SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
975 ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
976 if (C->getSExtValue()) {
979 const SITargetLowering& Lowering =
980 *static_cast<const SITargetLowering*>(getTargetLowering());
982 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0);
989 bool AMDGPUDAGToDAGISel::SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
990 SDValue &VAddr, SDValue &SOffset,
992 SDValue &SLC) const {
993 SLC = CurDAG->getTargetConstant(0, MVT::i1);
995 return SelectMUBUFAddr64(Addr, SRsrc, VAddr, SOffset, Offset);
998 bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
999 SDValue &VAddr, SDValue &SOffset,
1000 SDValue &ImmOffset) const {
1003 MachineFunction &MF = CurDAG->getMachineFunction();
1004 const SIRegisterInfo *TRI =
1005 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
1006 MachineRegisterInfo &MRI = MF.getRegInfo();
1007 const SITargetLowering& Lowering =
1008 *static_cast<const SITargetLowering*>(getTargetLowering());
1010 unsigned ScratchOffsetReg =
1011 TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET);
1012 Lowering.CreateLiveInRegister(*CurDAG, &AMDGPU::SReg_32RegClass,
1013 ScratchOffsetReg, MVT::i32);
1014 SDValue Sym0 = CurDAG->getExternalSymbol("SCRATCH_RSRC_DWORD0", MVT::i32);
1015 SDValue ScratchRsrcDword0 =
1016 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, Sym0), 0);
1018 SDValue Sym1 = CurDAG->getExternalSymbol("SCRATCH_RSRC_DWORD1", MVT::i32);
1019 SDValue ScratchRsrcDword1 =
1020 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, Sym1), 0);
1022 const SDValue RsrcOps[] = {
1023 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
1025 CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
1027 CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32),
1029 SDValue ScratchPtr = SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, DL,
1030 MVT::v2i32, RsrcOps), 0);
1031 Rsrc = SDValue(Lowering.buildScratchRSRC(*CurDAG, DL, ScratchPtr), 0);
1032 SOffset = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
1033 MRI.getLiveInVirtReg(ScratchOffsetReg), MVT::i32);
1036 if (CurDAG->isBaseWithConstantOffset(Addr)) {
1037 SDValue N1 = Addr.getOperand(1);
1038 ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
1040 if (isLegalMUBUFImmOffset(C1)) {
1041 VAddr = Addr.getOperand(0);
1042 ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), MVT::i16);
1049 ImmOffset = CurDAG->getTargetConstant(0, MVT::i16);
1053 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1054 SDValue &SOffset, SDValue &Offset,
1055 SDValue &GLC, SDValue &SLC,
1056 SDValue &TFE) const {
1057 SDValue Ptr, VAddr, Offen, Idxen, Addr64;
1058 const SIInstrInfo *TII =
1059 static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
1061 SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
1064 if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
1065 !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
1066 !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
1067 uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
1068 APInt::getAllOnesValue(32).getZExtValue(); // Size
1071 const SITargetLowering& Lowering =
1072 *static_cast<const SITargetLowering*>(getTargetLowering());
1074 SRsrc = SDValue(Lowering.buildRSRC(*CurDAG, DL, Ptr, 0, Rsrc), 0);
1080 bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
1081 SDValue &Soffset, SDValue &Offset,
1082 SDValue &GLC) const {
1085 return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
1088 // FIXME: This is incorrect and only enough to be able to compile.
1089 SDNode *AMDGPUDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
1090 AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(N);
1093 assert(Subtarget->hasFlatAddressSpace() &&
1094 "addrspacecast only supported with flat address space!");
1096 assert((ASC->getSrcAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS &&
1097 ASC->getDestAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS) &&
1098 "Cannot cast address space to / from constant address!");
1100 assert((ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS ||
1101 ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) &&
1102 "Can only cast to / from flat address space!");
1104 // The flat instructions read the address as the index of the VGPR holding the
1105 // address, so casting should just be reinterpreting the base VGPR, so just
1106 // insert trunc / bitcast / zext.
1108 SDValue Src = ASC->getOperand(0);
1109 EVT DestVT = ASC->getValueType(0);
1110 EVT SrcVT = Src.getValueType();
1112 unsigned SrcSize = SrcVT.getSizeInBits();
1113 unsigned DestSize = DestVT.getSizeInBits();
1115 if (SrcSize > DestSize) {
1116 assert(SrcSize == 64 && DestSize == 32);
1117 return CurDAG->getMachineNode(
1118 TargetOpcode::EXTRACT_SUBREG,
1122 CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32));
1126 if (DestSize > SrcSize) {
1127 assert(SrcSize == 32 && DestSize == 64);
1129 // FIXME: This is probably wrong, we should never be defining
1130 // a register class with both VGPRs and SGPRs
1131 SDValue RC = CurDAG->getTargetConstant(AMDGPU::VS_64RegClassID, MVT::i32);
1133 const SDValue Ops[] = {
1136 CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
1137 SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SDLoc(N), MVT::i32,
1138 CurDAG->getConstant(0, MVT::i32)), 0),
1139 CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32)
1142 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
1143 SDLoc(N), N->getValueType(0), Ops);
1146 assert(SrcSize == 64 && DestSize == 64);
1147 return CurDAG->getNode(ISD::BITCAST, DL, DestVT, Src).getNode();
1150 bool AMDGPUDAGToDAGISel::SelectVOP3Mods(SDValue In, SDValue &Src,
1151 SDValue &SrcMods) const {
1157 if (Src.getOpcode() == ISD::FNEG) {
1158 Mods |= SISrcMods::NEG;
1159 Src = Src.getOperand(0);
1162 if (Src.getOpcode() == ISD::FABS) {
1163 Mods |= SISrcMods::ABS;
1164 Src = Src.getOperand(0);
1167 SrcMods = CurDAG->getTargetConstant(Mods, MVT::i32);
1172 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
1173 SDValue &SrcMods, SDValue &Clamp,
1174 SDValue &Omod) const {
1175 // FIXME: Handle Clamp and Omod
1176 Clamp = CurDAG->getTargetConstant(0, MVT::i32);
1177 Omod = CurDAG->getTargetConstant(0, MVT::i32);
1179 return SelectVOP3Mods(In, Src, SrcMods);
1182 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp(SDValue In, SDValue &Src,
1184 SDValue &Omod) const {
1185 // FIXME: Handle Omod
1186 Omod = CurDAG->getTargetConstant(0, MVT::i32);
1188 return SelectVOP3Mods(In, Src, SrcMods);
1191 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp0OMod(SDValue In, SDValue &Src,
1194 SDValue &Omod) const {
1195 Clamp = Omod = CurDAG->getTargetConstant(0, MVT::i32);
1196 return SelectVOP3Mods(In, Src, SrcMods);
1199 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
1200 const AMDGPUTargetLowering& Lowering =
1201 *static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
1202 bool IsModified = false;
1205 // Go over all selected nodes and try to fold them a bit more
1206 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
1207 E = CurDAG->allnodes_end(); I != E; ++I) {
1211 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
1215 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
1216 if (ResNode != Node) {
1217 ReplaceUses(Node, ResNode);
1221 CurDAG->RemoveDeadNodes();
1222 } while (IsModified);