1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "R600InstrInfo.h"
18 #include "SIISelLowering.h"
19 #include "llvm/Analysis/ValueTracking.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/IR/ValueMap.h"
25 #include "llvm/Support/Compiler.h"
31 //===----------------------------------------------------------------------===//
32 // Instruction Selector Implementation
33 //===----------------------------------------------------------------------===//
36 /// AMDGPU specific code to select AMDGPU machine instructions for
37 /// SelectionDAG operations.
38 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
39 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
40 // make the right decision when generating code for different targets.
41 const AMDGPUSubtarget &Subtarget;
43 AMDGPUDAGToDAGISel(TargetMachine &TM);
44 virtual ~AMDGPUDAGToDAGISel();
46 SDNode *Select(SDNode *N);
47 virtual const char *getPassName() const;
48 virtual void PostprocessISelDAG();
51 inline SDValue getSmallIPtrImm(unsigned Imm);
52 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
53 const R600InstrInfo *TII);
54 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
55 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
57 // Complex pattern selectors
58 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
59 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
60 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
61 SDValue SimplifyI24(SDValue &Op);
62 bool SelectI24(SDValue Addr, SDValue &Op);
63 bool SelectU24(SDValue Addr, SDValue &Op);
65 static bool checkType(const Value *ptr, unsigned int addrspace);
67 static bool isGlobalStore(const StoreSDNode *N);
68 static bool isPrivateStore(const StoreSDNode *N);
69 static bool isLocalStore(const StoreSDNode *N);
70 static bool isRegionStore(const StoreSDNode *N);
72 bool isCPLoad(const LoadSDNode *N) const;
73 bool isConstantLoad(const LoadSDNode *N, int cbID) const;
74 bool isGlobalLoad(const LoadSDNode *N) const;
75 bool isParamLoad(const LoadSDNode *N) const;
76 bool isPrivateLoad(const LoadSDNode *N) const;
77 bool isLocalLoad(const LoadSDNode *N) const;
78 bool isRegionLoad(const LoadSDNode *N) const;
80 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
81 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
82 bool SelectGlobalValueVariableOffset(SDValue Addr,
83 SDValue &BaseReg, SDValue& Offset);
84 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
85 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
87 // Include the pieces autogenerated from the target description.
88 #include "AMDGPUGenDAGISel.inc"
90 } // end anonymous namespace
92 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
93 // DAG, ready for instruction scheduling.
94 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
96 return new AMDGPUDAGToDAGISel(TM);
99 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
100 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
103 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
106 /// \brief Determine the register class for \p OpNo
107 /// \returns The register class of the virtual register that will be used for
108 /// the given operand number \OpNo or NULL if the register class cannot be
110 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
111 unsigned OpNo) const {
112 if (!N->isMachineOpcode()) {
115 switch (N->getMachineOpcode()) {
117 const MCInstrDesc &Desc = TM.getInstrInfo()->get(N->getMachineOpcode());
118 unsigned OpIdx = Desc.getNumDefs() + OpNo;
119 if (OpIdx >= Desc.getNumOperands())
121 int RegClass = Desc.OpInfo[OpIdx].RegClass;
122 if (RegClass == -1) {
125 return TM.getRegisterInfo()->getRegClass(RegClass);
127 case AMDGPU::REG_SEQUENCE: {
128 const TargetRegisterClass *SuperRC = TM.getRegisterInfo()->getRegClass(
129 cast<ConstantSDNode>(N->getOperand(0))->getZExtValue());
131 dyn_cast<ConstantSDNode>(N->getOperand(OpNo + 1))->getZExtValue();
132 return TM.getRegisterInfo()->getSubClassWithSubReg(SuperRC, SubRegIdx);
137 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
138 return CurDAG->getTargetConstant(Imm, MVT::i32);
141 bool AMDGPUDAGToDAGISel::SelectADDRParam(
142 SDValue Addr, SDValue& R1, SDValue& R2) {
144 if (Addr.getOpcode() == ISD::FrameIndex) {
145 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
146 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
147 R2 = CurDAG->getTargetConstant(0, MVT::i32);
150 R2 = CurDAG->getTargetConstant(0, MVT::i32);
152 } else if (Addr.getOpcode() == ISD::ADD) {
153 R1 = Addr.getOperand(0);
154 R2 = Addr.getOperand(1);
157 R2 = CurDAG->getTargetConstant(0, MVT::i32);
162 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
163 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
164 Addr.getOpcode() == ISD::TargetGlobalAddress) {
167 return SelectADDRParam(Addr, R1, R2);
171 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
172 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
173 Addr.getOpcode() == ISD::TargetGlobalAddress) {
177 if (Addr.getOpcode() == ISD::FrameIndex) {
178 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
179 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
180 R2 = CurDAG->getTargetConstant(0, MVT::i64);
183 R2 = CurDAG->getTargetConstant(0, MVT::i64);
185 } else if (Addr.getOpcode() == ISD::ADD) {
186 R1 = Addr.getOperand(0);
187 R2 = Addr.getOperand(1);
190 R2 = CurDAG->getTargetConstant(0, MVT::i64);
195 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
196 unsigned int Opc = N->getOpcode();
197 if (N->isMachineOpcode()) {
199 return NULL; // Already selected.
203 // We are selecting i64 ADD here instead of custom lower it during
204 // DAG legalization, so we can fold some i64 ADDs used for address
205 // calculation into the LOAD and STORE instructions.
207 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
208 if (N->getValueType(0) != MVT::i64 ||
209 ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
213 SDValue LHS = N->getOperand(0);
214 SDValue RHS = N->getOperand(1);
216 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
217 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
219 SDNode *Lo0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
220 DL, MVT::i32, LHS, Sub0);
221 SDNode *Hi0 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
222 DL, MVT::i32, LHS, Sub1);
224 SDNode *Lo1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
225 DL, MVT::i32, RHS, Sub0);
226 SDNode *Hi1 = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
227 DL, MVT::i32, RHS, Sub1);
229 SDVTList VTList = CurDAG->getVTList(MVT::i32, MVT::Glue);
231 SmallVector<SDValue, 8> AddLoArgs;
232 AddLoArgs.push_back(SDValue(Lo0, 0));
233 AddLoArgs.push_back(SDValue(Lo1, 0));
235 SDNode *AddLo = CurDAG->getMachineNode(AMDGPU::S_ADD_I32, DL,
237 SDValue Carry = SDValue(AddLo, 1);
238 SDNode *AddHi = CurDAG->getMachineNode(AMDGPU::S_ADDC_U32, DL,
239 MVT::i32, SDValue(Hi0, 0),
240 SDValue(Hi1, 0), Carry);
243 CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32),
249 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, MVT::i64, Args, 5);
251 case ISD::BUILD_VECTOR: {
253 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
254 const AMDGPURegisterInfo *TRI =
255 static_cast<const AMDGPURegisterInfo*>(TM.getRegisterInfo());
256 const SIRegisterInfo *SIRI =
257 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
258 EVT VT = N->getValueType(0);
259 unsigned NumVectorElts = VT.getVectorNumElements();
260 assert(VT.getVectorElementType().bitsEq(MVT::i32));
261 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
263 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
265 if (!U->isMachineOpcode()) {
268 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
272 if (SIRI->isSGPRClass(RC)) {
276 switch(NumVectorElts) {
277 case 1: RegClassID = UseVReg ? AMDGPU::VReg_32RegClassID :
278 AMDGPU::SReg_32RegClassID;
280 case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID :
281 AMDGPU::SReg_64RegClassID;
283 case 4: RegClassID = UseVReg ? AMDGPU::VReg_128RegClassID :
284 AMDGPU::SReg_128RegClassID;
286 case 8: RegClassID = UseVReg ? AMDGPU::VReg_256RegClassID :
287 AMDGPU::SReg_256RegClassID;
289 case 16: RegClassID = UseVReg ? AMDGPU::VReg_512RegClassID :
290 AMDGPU::SReg_512RegClassID;
292 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
295 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
296 // that adds a 128 bits reg copy when going through TwoAddressInstructions
297 // pass. We want to avoid 128 bits copies as much as possible because they
298 // can't be bundled by our scheduler.
299 switch(NumVectorElts) {
300 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
301 case 4: RegClassID = AMDGPU::R600_Reg128RegClassID; break;
302 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
306 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, MVT::i32);
308 if (NumVectorElts == 1) {
309 return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS,
310 VT.getVectorElementType(),
311 N->getOperand(0), RegClass);
314 assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
316 // 16 = Max Num Vector Elements
317 // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
318 // 1 = Vector Register Class
319 SDValue RegSeqArgs[16 * 2 + 1];
321 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, MVT::i32);
322 bool IsRegSeq = true;
323 for (unsigned i = 0; i < N->getNumOperands(); i++) {
324 // XXX: Why is this here?
325 if (dyn_cast<RegisterSDNode>(N->getOperand(i))) {
329 RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
330 RegSeqArgs[1 + (2 * i) + 1] =
331 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
335 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
336 RegSeqArgs, 2 * N->getNumOperands() + 1);
338 case ISD::BUILD_PAIR: {
339 SDValue RC, SubReg0, SubReg1;
340 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
341 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
344 if (N->getValueType(0) == MVT::i128) {
345 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
346 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
347 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
348 } else if (N->getValueType(0) == MVT::i64) {
349 RC = CurDAG->getTargetConstant(AMDGPU::VSrc_64RegClassID, MVT::i32);
350 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
351 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
353 llvm_unreachable("Unhandled value type for BUILD_PAIR");
355 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
356 N->getOperand(1), SubReg1 };
357 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
358 SDLoc(N), N->getValueType(0), Ops);
360 case AMDGPUISD::REGISTER_LOAD: {
361 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
362 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
364 SDValue Addr, Offset;
366 SelectADDRIndirect(N->getOperand(1), Addr, Offset);
367 const SDValue Ops[] = {
370 CurDAG->getTargetConstant(0, MVT::i32),
373 return CurDAG->getMachineNode(AMDGPU::SI_RegisterLoad, SDLoc(N),
374 CurDAG->getVTList(MVT::i32, MVT::i64, MVT::Other),
377 case AMDGPUISD::REGISTER_STORE: {
378 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
379 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
381 SDValue Addr, Offset;
382 SelectADDRIndirect(N->getOperand(2), Addr, Offset);
383 const SDValue Ops[] = {
387 CurDAG->getTargetConstant(0, MVT::i32),
390 return CurDAG->getMachineNode(AMDGPU::SI_RegisterStorePseudo, SDLoc(N),
391 CurDAG->getVTList(MVT::Other),
395 return SelectCode(N);
399 bool AMDGPUDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
403 Type *ptrType = ptr->getType();
404 return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
407 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
408 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
411 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
412 return (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
413 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
414 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS));
417 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
418 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
421 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
422 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
425 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
427 return checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS);
429 return checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_BUFFER_0 + CbId);
432 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
433 if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) {
434 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
435 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
436 N->getMemoryVT().bitsLT(MVT::i32)) {
440 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
443 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
444 return checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS);
447 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
448 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
451 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
452 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
455 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
456 MachineMemOperand *MMO = N->getMemOperand();
457 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
459 const Value *V = MMO->getValue();
460 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
461 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
469 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
470 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
471 // Check to make sure we are not a constant pool load or a constant load
472 // that is marked as a private load
473 if (isCPLoad(N) || isConstantLoad(N, -1)) {
477 if (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
478 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
479 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS)
480 && !checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)
481 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_D_ADDRESS)
482 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS)) {
488 const char *AMDGPUDAGToDAGISel::getPassName() const {
489 return "AMDGPU DAG->DAG Pattern Instruction Selection";
497 //===----------------------------------------------------------------------===//
499 //===----------------------------------------------------------------------===//
501 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
503 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
504 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
510 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
511 SDValue& BaseReg, SDValue &Offset) {
512 if (!dyn_cast<ConstantSDNode>(Addr)) {
514 Offset = CurDAG->getIntPtrConstant(0, true);
520 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
522 ConstantSDNode * IMMOffset;
524 if (Addr.getOpcode() == ISD::ADD
525 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
526 && isInt<16>(IMMOffset->getZExtValue())) {
528 Base = Addr.getOperand(0);
529 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
531 // If the pointer address is constant, we can move it to the offset field.
532 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
533 && isInt<16>(IMMOffset->getZExtValue())) {
534 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
535 SDLoc(CurDAG->getEntryNode()),
536 AMDGPU::ZERO, MVT::i32);
537 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
541 // Default case, no offset
543 Offset = CurDAG->getTargetConstant(0, MVT::i32);
547 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
551 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
552 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
553 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
554 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
555 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
556 Base = Addr.getOperand(0);
557 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
560 Offset = CurDAG->getTargetConstant(0, MVT::i32);
566 SDValue AMDGPUDAGToDAGISel::SimplifyI24(SDValue &Op) {
567 APInt Demanded = APInt(32, 0x00FFFFFF);
568 APInt KnownZero, KnownOne;
569 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true);
570 const TargetLowering *TLI = getTargetLowering();
571 if (TLI->SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) {
572 CurDAG->ReplaceAllUsesWith(Op, TLO.New);
573 CurDAG->RepositionNode(Op.getNode(), TLO.New.getNode());
574 return SimplifyI24(TLO.New);
580 bool AMDGPUDAGToDAGISel::SelectI24(SDValue Op, SDValue &I24) {
582 assert(Op.getValueType() == MVT::i32);
584 if (CurDAG->ComputeNumSignBits(Op) == 9) {
585 I24 = SimplifyI24(Op);
591 bool AMDGPUDAGToDAGISel::SelectU24(SDValue Op, SDValue &U24) {
594 CurDAG->ComputeMaskedBits(Op, KnownZero, KnownOne);
596 assert (Op.getValueType() == MVT::i32);
598 // ANY_EXTEND and EXTLOAD operations can only be done on types smaller than
599 // i32. These smaller types are legal to use with the i24 instructions.
600 if ((KnownZero & APInt(KnownZero.getBitWidth(), 0xFF000000)) == 0xFF000000 ||
601 Op.getOpcode() == ISD::ANY_EXTEND ||
602 ISD::isEXTLoad(Op.getNode())) {
603 U24 = SimplifyI24(Op);
609 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
610 const AMDGPUTargetLowering& Lowering =
611 (*(const AMDGPUTargetLowering*)getTargetLowering());
612 bool IsModified = false;
615 // Go over all selected nodes and try to fold them a bit more
616 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
617 E = CurDAG->allnodes_end(); I != E; ++I) {
621 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
625 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
626 if (ResNode != Node) {
627 ReplaceUses(Node, ResNode);
631 CurDAG->RemoveDeadNodes();
632 } while (IsModified);