1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "R600InstrInfo.h"
18 #include "SIISelLowering.h"
19 #include "llvm/ADT/ValueMap.h"
20 #include "llvm/Analysis/ValueTracking.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Support/Compiler.h"
31 //===----------------------------------------------------------------------===//
32 // Instruction Selector Implementation
33 //===----------------------------------------------------------------------===//
36 /// AMDGPU specific code to select AMDGPU machine instructions for
37 /// SelectionDAG operations.
38 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
39 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
40 // make the right decision when generating code for different targets.
41 const AMDGPUSubtarget &Subtarget;
43 AMDGPUDAGToDAGISel(TargetMachine &TM);
44 virtual ~AMDGPUDAGToDAGISel();
46 SDNode *Select(SDNode *N);
47 virtual const char *getPassName() const;
48 virtual void PostprocessISelDAG();
51 inline SDValue getSmallIPtrImm(unsigned Imm);
52 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
53 const R600InstrInfo *TII);
54 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
55 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
57 // Complex pattern selectors
58 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
59 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
60 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
61 SDValue SimplifyI24(SDValue &Op);
62 bool SelectI24(SDValue Addr, SDValue &Op);
63 bool SelectU24(SDValue Addr, SDValue &Op);
65 static bool checkType(const Value *ptr, unsigned int addrspace);
67 static bool isGlobalStore(const StoreSDNode *N);
68 static bool isPrivateStore(const StoreSDNode *N);
69 static bool isLocalStore(const StoreSDNode *N);
70 static bool isRegionStore(const StoreSDNode *N);
72 bool isCPLoad(const LoadSDNode *N) const;
73 bool isConstantLoad(const LoadSDNode *N, int cbID) const;
74 bool isGlobalLoad(const LoadSDNode *N) const;
75 bool isParamLoad(const LoadSDNode *N) const;
76 bool isPrivateLoad(const LoadSDNode *N) const;
77 bool isLocalLoad(const LoadSDNode *N) const;
78 bool isRegionLoad(const LoadSDNode *N) const;
80 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
81 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
82 bool SelectGlobalValueVariableOffset(SDValue Addr,
83 SDValue &BaseReg, SDValue& Offset);
84 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
85 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
87 // Include the pieces autogenerated from the target description.
88 #include "AMDGPUGenDAGISel.inc"
90 } // end anonymous namespace
92 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
93 // DAG, ready for instruction scheduling.
94 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
96 return new AMDGPUDAGToDAGISel(TM);
99 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
100 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
103 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
106 /// \brief Determine the register class for \p OpNo
107 /// \returns The register class of the virtual register that will be used for
108 /// the given operand number \OpNo or NULL if the register class cannot be
110 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
111 unsigned OpNo) const {
112 if (!N->isMachineOpcode()) {
115 switch (N->getMachineOpcode()) {
117 const MCInstrDesc &Desc = TM.getInstrInfo()->get(N->getMachineOpcode());
118 unsigned OpIdx = Desc.getNumDefs() + OpNo;
119 if (OpIdx >= Desc.getNumOperands())
121 int RegClass = Desc.OpInfo[OpIdx].RegClass;
122 if (RegClass == -1) {
125 return TM.getRegisterInfo()->getRegClass(RegClass);
127 case AMDGPU::REG_SEQUENCE: {
128 const TargetRegisterClass *SuperRC = TM.getRegisterInfo()->getRegClass(
129 cast<ConstantSDNode>(N->getOperand(0))->getZExtValue());
131 dyn_cast<ConstantSDNode>(N->getOperand(OpNo + 1))->getZExtValue();
132 return TM.getRegisterInfo()->getSubClassWithSubReg(SuperRC, SubRegIdx);
137 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
138 return CurDAG->getTargetConstant(Imm, MVT::i32);
141 bool AMDGPUDAGToDAGISel::SelectADDRParam(
142 SDValue Addr, SDValue& R1, SDValue& R2) {
144 if (Addr.getOpcode() == ISD::FrameIndex) {
145 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
146 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
147 R2 = CurDAG->getTargetConstant(0, MVT::i32);
150 R2 = CurDAG->getTargetConstant(0, MVT::i32);
152 } else if (Addr.getOpcode() == ISD::ADD) {
153 R1 = Addr.getOperand(0);
154 R2 = Addr.getOperand(1);
157 R2 = CurDAG->getTargetConstant(0, MVT::i32);
162 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
163 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
164 Addr.getOpcode() == ISD::TargetGlobalAddress) {
167 return SelectADDRParam(Addr, R1, R2);
171 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
172 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
173 Addr.getOpcode() == ISD::TargetGlobalAddress) {
177 if (Addr.getOpcode() == ISD::FrameIndex) {
178 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
179 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
180 R2 = CurDAG->getTargetConstant(0, MVT::i64);
183 R2 = CurDAG->getTargetConstant(0, MVT::i64);
185 } else if (Addr.getOpcode() == ISD::ADD) {
186 R1 = Addr.getOperand(0);
187 R2 = Addr.getOperand(1);
190 R2 = CurDAG->getTargetConstant(0, MVT::i64);
195 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
196 unsigned int Opc = N->getOpcode();
197 if (N->isMachineOpcode()) {
199 return NULL; // Already selected.
203 case ISD::BUILD_VECTOR: {
205 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
206 const AMDGPURegisterInfo *TRI =
207 static_cast<const AMDGPURegisterInfo*>(TM.getRegisterInfo());
208 const SIRegisterInfo *SIRI =
209 static_cast<const SIRegisterInfo*>(TM.getRegisterInfo());
210 EVT VT = N->getValueType(0);
211 unsigned NumVectorElts = VT.getVectorNumElements();
212 assert(VT.getVectorElementType().bitsEq(MVT::i32));
213 if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
215 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
217 if (!U->isMachineOpcode()) {
220 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
224 if (SIRI->isSGPRClass(RC)) {
228 switch(NumVectorElts) {
229 case 1: RegClassID = UseVReg ? AMDGPU::VReg_32RegClassID :
230 AMDGPU::SReg_32RegClassID;
232 case 2: RegClassID = UseVReg ? AMDGPU::VReg_64RegClassID :
233 AMDGPU::SReg_64RegClassID;
235 case 4: RegClassID = UseVReg ? AMDGPU::VReg_128RegClassID :
236 AMDGPU::SReg_128RegClassID;
238 case 8: RegClassID = UseVReg ? AMDGPU::VReg_256RegClassID :
239 AMDGPU::SReg_256RegClassID;
241 case 16: RegClassID = UseVReg ? AMDGPU::VReg_512RegClassID :
242 AMDGPU::SReg_512RegClassID;
244 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
247 // BUILD_VECTOR was lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
248 // that adds a 128 bits reg copy when going through TwoAddressInstructions
249 // pass. We want to avoid 128 bits copies as much as possible because they
250 // can't be bundled by our scheduler.
251 switch(NumVectorElts) {
252 case 2: RegClassID = AMDGPU::R600_Reg64RegClassID; break;
253 case 4: RegClassID = AMDGPU::R600_Reg128RegClassID; break;
254 default: llvm_unreachable("Do not know how to lower this BUILD_VECTOR");
258 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, MVT::i32);
260 if (NumVectorElts == 1) {
261 return CurDAG->SelectNodeTo(N, AMDGPU::COPY_TO_REGCLASS,
262 VT.getVectorElementType(),
263 N->getOperand(0), RegClass);
266 assert(NumVectorElts <= 16 && "Vectors with more than 16 elements not "
268 // 16 = Max Num Vector Elements
269 // 2 = 2 REG_SEQUENCE operands per element (value, subreg index)
270 // 1 = Vector Register Class
271 SDValue RegSeqArgs[16 * 2 + 1];
273 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, MVT::i32);
274 bool IsRegSeq = true;
275 for (unsigned i = 0; i < N->getNumOperands(); i++) {
276 // XXX: Why is this here?
277 if (dyn_cast<RegisterSDNode>(N->getOperand(i))) {
281 RegSeqArgs[1 + (2 * i)] = N->getOperand(i);
282 RegSeqArgs[1 + (2 * i) + 1] =
283 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), MVT::i32);
287 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
288 RegSeqArgs, 2 * N->getNumOperands() + 1);
290 case ISD::BUILD_PAIR: {
291 SDValue RC, SubReg0, SubReg1;
292 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
293 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
296 if (N->getValueType(0) == MVT::i128) {
297 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
298 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
299 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
300 } else if (N->getValueType(0) == MVT::i64) {
301 RC = CurDAG->getTargetConstant(AMDGPU::VSrc_64RegClassID, MVT::i32);
302 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
303 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
305 llvm_unreachable("Unhandled value type for BUILD_PAIR");
307 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
308 N->getOperand(1), SubReg1 };
309 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
310 SDLoc(N), N->getValueType(0), Ops);
313 return SelectCode(N);
317 bool AMDGPUDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
321 Type *ptrType = ptr->getType();
322 return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
325 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
326 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
329 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
330 return (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
331 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
332 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS));
335 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
336 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
339 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
340 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
343 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
345 return checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS);
347 return checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_BUFFER_0 + CbId);
350 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
351 if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) {
352 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
353 if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
354 N->getMemoryVT().bitsLT(MVT::i32)) {
358 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
361 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
362 return checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS);
365 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
366 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
369 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
370 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
373 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
374 MachineMemOperand *MMO = N->getMemOperand();
375 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
377 const Value *V = MMO->getValue();
378 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
379 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
387 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
388 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
389 // Check to make sure we are not a constant pool load or a constant load
390 // that is marked as a private load
391 if (isCPLoad(N) || isConstantLoad(N, -1)) {
395 if (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
396 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
397 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS)
398 && !checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)
399 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_D_ADDRESS)
400 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS)) {
406 const char *AMDGPUDAGToDAGISel::getPassName() const {
407 return "AMDGPU DAG->DAG Pattern Instruction Selection";
415 //===----------------------------------------------------------------------===//
417 //===----------------------------------------------------------------------===//
419 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
421 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
422 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
428 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
429 SDValue& BaseReg, SDValue &Offset) {
430 if (!dyn_cast<ConstantSDNode>(Addr)) {
432 Offset = CurDAG->getIntPtrConstant(0, true);
438 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
440 ConstantSDNode * IMMOffset;
442 if (Addr.getOpcode() == ISD::ADD
443 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
444 && isInt<16>(IMMOffset->getZExtValue())) {
446 Base = Addr.getOperand(0);
447 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
449 // If the pointer address is constant, we can move it to the offset field.
450 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
451 && isInt<16>(IMMOffset->getZExtValue())) {
452 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
453 SDLoc(CurDAG->getEntryNode()),
454 AMDGPU::ZERO, MVT::i32);
455 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
459 // Default case, no offset
461 Offset = CurDAG->getTargetConstant(0, MVT::i32);
465 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
469 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
470 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
471 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
472 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
473 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
474 Base = Addr.getOperand(0);
475 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
478 Offset = CurDAG->getTargetConstant(0, MVT::i32);
484 SDValue AMDGPUDAGToDAGISel::SimplifyI24(SDValue &Op) {
485 APInt Demanded = APInt(32, 0x00FFFFFF);
486 APInt KnownZero, KnownOne;
487 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true);
488 const TargetLowering *TLI = getTargetLowering();
489 if (TLI->SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) {
490 CurDAG->ReplaceAllUsesWith(Op, TLO.New);
491 CurDAG->RepositionNode(Op.getNode(), TLO.New.getNode());
492 return SimplifyI24(TLO.New);
498 bool AMDGPUDAGToDAGISel::SelectI24(SDValue Op, SDValue &I24) {
500 assert(Op.getValueType() == MVT::i32);
502 if (CurDAG->ComputeNumSignBits(Op) == 9) {
503 I24 = SimplifyI24(Op);
509 bool AMDGPUDAGToDAGISel::SelectU24(SDValue Op, SDValue &U24) {
512 CurDAG->ComputeMaskedBits(Op, KnownZero, KnownOne);
514 assert (Op.getValueType() == MVT::i32);
516 // ANY_EXTEND and EXTLOAD operations can only be done on types smaller than
517 // i32. These smaller types are legal to use with the i24 instructions.
518 if ((KnownZero & APInt(KnownZero.getBitWidth(), 0xFF000000)) == 0xFF000000 ||
519 Op.getOpcode() == ISD::ANY_EXTEND ||
520 ISD::isEXTLoad(Op.getNode())) {
521 U24 = SimplifyI24(Op);
527 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
528 const AMDGPUTargetLowering& Lowering =
529 (*(const AMDGPUTargetLowering*)getTargetLowering());
530 bool IsModified = false;
533 // Go over all selected nodes and try to fold them a bit more
534 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
535 E = CurDAG->allnodes_end(); I != E; ++I) {
539 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
543 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
544 if (ResNode != Node) {
545 ReplaceUses(Node, ResNode);
549 CurDAG->RemoveDeadNodes();
550 } while (IsModified);