1 //===-- AMDILISelDAGToDAG.cpp - A dag to dag inst selector for AMDIL ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
11 /// \brief Defines an instruction selector for the AMDGPU target.
13 //===----------------------------------------------------------------------===//
14 #include "AMDGPUInstrInfo.h"
15 #include "AMDGPUISelLowering.h" // For AMDGPUISD
16 #include "AMDGPURegisterInfo.h"
17 #include "R600InstrInfo.h"
18 #include "SIISelLowering.h"
19 #include "llvm/ADT/ValueMap.h"
20 #include "llvm/Analysis/ValueTracking.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Support/Compiler.h"
31 //===----------------------------------------------------------------------===//
32 // Instruction Selector Implementation
33 //===----------------------------------------------------------------------===//
36 /// AMDGPU specific code to select AMDGPU machine instructions for
37 /// SelectionDAG operations.
38 class AMDGPUDAGToDAGISel : public SelectionDAGISel {
39 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
40 // make the right decision when generating code for different targets.
41 const AMDGPUSubtarget &Subtarget;
43 AMDGPUDAGToDAGISel(TargetMachine &TM);
44 virtual ~AMDGPUDAGToDAGISel();
46 SDNode *Select(SDNode *N);
47 virtual const char *getPassName() const;
48 virtual void PostprocessISelDAG();
51 inline SDValue getSmallIPtrImm(unsigned Imm);
52 bool FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg, SDValue &Abs,
53 const R600InstrInfo *TII);
54 bool FoldOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
55 bool FoldDotOperands(unsigned, const R600InstrInfo *, std::vector<SDValue> &);
57 // Complex pattern selectors
58 bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
59 bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
60 bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
61 SDValue SimplifyI24(SDValue &Op);
62 bool SelectI24(SDValue Addr, SDValue &Op);
63 bool SelectU24(SDValue Addr, SDValue &Op);
65 static bool checkType(const Value *ptr, unsigned int addrspace);
67 static bool isGlobalStore(const StoreSDNode *N);
68 static bool isPrivateStore(const StoreSDNode *N);
69 static bool isLocalStore(const StoreSDNode *N);
70 static bool isRegionStore(const StoreSDNode *N);
72 bool isCPLoad(const LoadSDNode *N) const;
73 bool isConstantLoad(const LoadSDNode *N, int cbID) const;
74 bool isGlobalLoad(const LoadSDNode *N) const;
75 bool isParamLoad(const LoadSDNode *N) const;
76 bool isPrivateLoad(const LoadSDNode *N) const;
77 bool isLocalLoad(const LoadSDNode *N) const;
78 bool isRegionLoad(const LoadSDNode *N) const;
80 bool SelectGlobalValueConstantOffset(SDValue Addr, SDValue& IntPtr);
81 bool SelectGlobalValueVariableOffset(SDValue Addr,
82 SDValue &BaseReg, SDValue& Offset);
83 bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
84 bool SelectADDRIndirect(SDValue Addr, SDValue &Base, SDValue &Offset);
86 // Include the pieces autogenerated from the target description.
87 #include "AMDGPUGenDAGISel.inc"
89 } // end anonymous namespace
91 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
92 // DAG, ready for instruction scheduling.
93 FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM
95 return new AMDGPUDAGToDAGISel(TM);
98 AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
99 : SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) {
102 AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
105 SDValue AMDGPUDAGToDAGISel::getSmallIPtrImm(unsigned int Imm) {
106 return CurDAG->getTargetConstant(Imm, MVT::i32);
109 bool AMDGPUDAGToDAGISel::SelectADDRParam(
110 SDValue Addr, SDValue& R1, SDValue& R2) {
112 if (Addr.getOpcode() == ISD::FrameIndex) {
113 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
114 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
115 R2 = CurDAG->getTargetConstant(0, MVT::i32);
118 R2 = CurDAG->getTargetConstant(0, MVT::i32);
120 } else if (Addr.getOpcode() == ISD::ADD) {
121 R1 = Addr.getOperand(0);
122 R2 = Addr.getOperand(1);
125 R2 = CurDAG->getTargetConstant(0, MVT::i32);
130 bool AMDGPUDAGToDAGISel::SelectADDR(SDValue Addr, SDValue& R1, SDValue& R2) {
131 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
132 Addr.getOpcode() == ISD::TargetGlobalAddress) {
135 return SelectADDRParam(Addr, R1, R2);
139 bool AMDGPUDAGToDAGISel::SelectADDR64(SDValue Addr, SDValue& R1, SDValue& R2) {
140 if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
141 Addr.getOpcode() == ISD::TargetGlobalAddress) {
145 if (Addr.getOpcode() == ISD::FrameIndex) {
146 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
147 R1 = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i64);
148 R2 = CurDAG->getTargetConstant(0, MVT::i64);
151 R2 = CurDAG->getTargetConstant(0, MVT::i64);
153 } else if (Addr.getOpcode() == ISD::ADD) {
154 R1 = Addr.getOperand(0);
155 R2 = Addr.getOperand(1);
158 R2 = CurDAG->getTargetConstant(0, MVT::i64);
163 SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
164 const R600InstrInfo *TII =
165 static_cast<const R600InstrInfo*>(TM.getInstrInfo());
166 unsigned int Opc = N->getOpcode();
167 if (N->isMachineOpcode()) {
168 return NULL; // Already selected.
172 case AMDGPUISD::CONST_ADDRESS: {
173 for (SDNode::use_iterator I = N->use_begin(), Next = llvm::next(I);
174 I != SDNode::use_end(); I = Next) {
175 Next = llvm::next(I);
176 if (!I->isMachineOpcode()) {
179 unsigned Opcode = I->getMachineOpcode();
180 bool HasDst = TII->getOperandIdx(Opcode, AMDGPU::OpName::dst) > -1;
181 int SrcIdx = I.getOperandNo();
183 // Unlike MachineInstrs, SDNodes do not have results in their operand
184 // list, so we need to increment the SrcIdx, since
185 // R600InstrInfo::getOperandIdx is based on the MachineInstr indices.
190 SelIdx = TII->getSelIdx(I->getMachineOpcode(), SrcIdx);
196 if (N->getValueType(0).isVector() ||
197 !SelectGlobalValueConstantOffset(N->getOperand(0), CstOffset))
200 // Gather constants values
202 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
203 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
204 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2),
205 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
206 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
207 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
208 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
209 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
210 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
211 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
212 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
214 std::vector<unsigned> Consts;
215 for (unsigned i = 0; i < sizeof(SrcIndices) / sizeof(int); i++) {
216 int OtherSrcIdx = SrcIndices[i];
217 int OtherSelIdx = TII->getSelIdx(Opcode, OtherSrcIdx);
218 if (OtherSrcIdx < 0 || OtherSelIdx < 0) {
225 if (RegisterSDNode *Reg =
226 dyn_cast<RegisterSDNode>(I->getOperand(OtherSrcIdx))) {
227 if (Reg->getReg() == AMDGPU::ALU_CONST) {
228 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(I->getOperand(OtherSelIdx));
229 Consts.push_back(Cst->getZExtValue());
234 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(CstOffset);
235 Consts.push_back(Cst->getZExtValue());
236 if (!TII->fitsConstReadLimitations(Consts))
239 // Convert back to SDNode indices
244 std::vector<SDValue> Ops;
245 for (int i = 0, e = I->getNumOperands(); i != e; ++i) {
247 Ops.push_back(CurDAG->getRegister(AMDGPU::ALU_CONST, MVT::f32));
248 } else if (i == SelIdx) {
249 Ops.push_back(CstOffset);
251 Ops.push_back(I->getOperand(i));
254 CurDAG->UpdateNodeOperands(*I, Ops.data(), Ops.size());
258 case ISD::BUILD_VECTOR: {
259 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
260 if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
263 // BUILD_VECTOR is usually lowered into an IMPLICIT_DEF + 4 INSERT_SUBREG
264 // that adds a 128 bits reg copy when going through TwoAddressInstructions
265 // pass. We want to avoid 128 bits copies as much as possible because they
266 // can't be bundled by our scheduler.
267 SDValue RegSeqArgs[9] = {
268 CurDAG->getTargetConstant(AMDGPU::R600_Reg128RegClassID, MVT::i32),
269 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
270 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32),
271 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub2, MVT::i32),
272 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub3, MVT::i32)
274 bool IsRegSeq = true;
275 for (unsigned i = 0; i < N->getNumOperands(); i++) {
276 if (dyn_cast<RegisterSDNode>(N->getOperand(i))) {
280 RegSeqArgs[2 * i + 1] = N->getOperand(i);
284 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
285 RegSeqArgs, 2 * N->getNumOperands() + 1);
287 case ISD::BUILD_PAIR: {
288 SDValue RC, SubReg0, SubReg1;
289 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
290 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
293 if (N->getValueType(0) == MVT::i128) {
294 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, MVT::i32);
295 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0_sub1, MVT::i32);
296 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub2_sub3, MVT::i32);
297 } else if (N->getValueType(0) == MVT::i64) {
298 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, MVT::i32);
299 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32);
300 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32);
302 llvm_unreachable("Unhandled value type for BUILD_PAIR");
304 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0,
305 N->getOperand(1), SubReg1 };
306 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE,
307 SDLoc(N), N->getValueType(0), Ops);
310 case ISD::ConstantFP:
311 case ISD::Constant: {
312 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
313 // XXX: Custom immediate lowering not implemented yet. Instead we use
314 // pseudo instructions defined in SIInstructions.td
315 if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
319 uint64_t ImmValue = 0;
320 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
322 if (N->getOpcode() == ISD::ConstantFP) {
323 // XXX: 64-bit Immediates not supported yet
324 assert(N->getValueType(0) != MVT::f64);
326 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N);
327 APFloat Value = C->getValueAPF();
328 float FloatValue = Value.convertToFloat();
329 if (FloatValue == 0.0) {
330 ImmReg = AMDGPU::ZERO;
331 } else if (FloatValue == 0.5) {
332 ImmReg = AMDGPU::HALF;
333 } else if (FloatValue == 1.0) {
334 ImmReg = AMDGPU::ONE;
336 ImmValue = Value.bitcastToAPInt().getZExtValue();
339 // XXX: 64-bit Immediates not supported yet
340 assert(N->getValueType(0) != MVT::i64);
342 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
343 if (C->getZExtValue() == 0) {
344 ImmReg = AMDGPU::ZERO;
345 } else if (C->getZExtValue() == 1) {
346 ImmReg = AMDGPU::ONE_INT;
348 ImmValue = C->getZExtValue();
352 for (SDNode::use_iterator Use = N->use_begin(), Next = llvm::next(Use);
353 Use != SDNode::use_end(); Use = Next) {
354 Next = llvm::next(Use);
355 std::vector<SDValue> Ops;
356 for (unsigned i = 0; i < Use->getNumOperands(); ++i) {
357 Ops.push_back(Use->getOperand(i));
360 if (!Use->isMachineOpcode()) {
361 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
362 // We can only use literal constants (e.g. AMDGPU::ZERO,
363 // AMDGPU::ONE, etc) in machine opcodes.
367 if (!TII->isALUInstr(Use->getMachineOpcode()) ||
368 (TII->get(Use->getMachineOpcode()).TSFlags &
369 R600_InstFlag::VECTOR)) {
373 int ImmIdx = TII->getOperandIdx(Use->getMachineOpcode(),
374 AMDGPU::OpName::literal);
379 if (TII->getOperandIdx(Use->getMachineOpcode(),
380 AMDGPU::OpName::dst) != -1) {
381 // subtract one from ImmIdx, because the DST operand is usually index
382 // 0 for MachineInstrs, but we have no DST in the Ops vector.
386 // Check that we aren't already using an immediate.
387 // XXX: It's possible for an instruction to have more than one
388 // immediate operand, but this is not supported yet.
389 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
390 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Use->getOperand(ImmIdx));
393 if (C->getZExtValue() != 0) {
394 // This instruction is already using an immediate.
398 // Set the immediate value
399 Ops[ImmIdx] = CurDAG->getTargetConstant(ImmValue, MVT::i32);
402 // Set the immediate register
403 Ops[Use.getOperandNo()] = CurDAG->getRegister(ImmReg, MVT::i32);
405 CurDAG->UpdateNodeOperands(*Use, Ops.data(), Use->getNumOperands());
410 SDNode *Result = SelectCode(N);
412 // Fold operands of selected node
414 const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
415 if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
416 const R600InstrInfo *TII =
417 static_cast<const R600InstrInfo*>(TM.getInstrInfo());
418 if (Result && Result->isMachineOpcode() && Result->getMachineOpcode() == AMDGPU::DOT_4) {
419 bool IsModified = false;
421 std::vector<SDValue> Ops;
422 for(SDNode::op_iterator I = Result->op_begin(), E = Result->op_end();
425 IsModified = FoldDotOperands(Result->getMachineOpcode(), TII, Ops);
427 Result = CurDAG->UpdateNodeOperands(Result, Ops.data(), Ops.size());
429 } while (IsModified);
432 if (Result && Result->isMachineOpcode() &&
433 !(TII->get(Result->getMachineOpcode()).TSFlags & R600_InstFlag::VECTOR)
434 && TII->hasInstrModifiers(Result->getMachineOpcode())) {
436 // TODO: Isel can generate multiple MachineInst, we need to recursively
438 bool IsModified = false;
440 std::vector<SDValue> Ops;
441 for(SDNode::op_iterator I = Result->op_begin(), E = Result->op_end();
444 IsModified = FoldOperands(Result->getMachineOpcode(), TII, Ops);
446 Result = CurDAG->UpdateNodeOperands(Result, Ops.data(), Ops.size());
448 } while (IsModified);
450 // If node has a single use which is CLAMP_R600, folds it
451 if (Result->hasOneUse() && Result->isMachineOpcode()) {
452 SDNode *PotentialClamp = *Result->use_begin();
453 if (PotentialClamp->isMachineOpcode() &&
454 PotentialClamp->getMachineOpcode() == AMDGPU::CLAMP_R600) {
456 TII->getOperandIdx(Result->getMachineOpcode(), AMDGPU::OpName::clamp);
457 std::vector<SDValue> Ops;
458 unsigned NumOp = Result->getNumOperands();
459 for (unsigned i = 0; i < NumOp; ++i) {
460 Ops.push_back(Result->getOperand(i));
462 Ops[ClampIdx - 1] = CurDAG->getTargetConstant(1, MVT::i32);
463 Result = CurDAG->SelectNodeTo(PotentialClamp,
464 Result->getMachineOpcode(), PotentialClamp->getVTList(),
474 bool AMDGPUDAGToDAGISel::FoldOperand(SDValue &Src, SDValue &Sel, SDValue &Neg,
475 SDValue &Abs, const R600InstrInfo *TII) {
476 switch (Src.getOpcode()) {
478 Src = Src.getOperand(0);
479 Neg = CurDAG->getTargetConstant(1, MVT::i32);
484 Src = Src.getOperand(0);
485 Abs = CurDAG->getTargetConstant(1, MVT::i32);
488 Src = Src.getOperand(0);
495 bool AMDGPUDAGToDAGISel::FoldOperands(unsigned Opcode,
496 const R600InstrInfo *TII, std::vector<SDValue> &Ops) {
498 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0),
499 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1),
500 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2)
503 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_sel),
504 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_sel),
505 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2_sel)
508 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg),
509 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg),
510 TII->getOperandIdx(Opcode, AMDGPU::OpName::src2_neg)
513 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs),
514 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs),
519 for (unsigned i = 0; i < 3; i++) {
520 if (OperandIdx[i] < 0)
522 SDValue &Src = Ops[OperandIdx[i] - 1];
523 SDValue &Sel = Ops[SelIdx[i] - 1];
524 SDValue &Neg = Ops[NegIdx[i] - 1];
526 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs;
527 if (FoldOperand(Src, Sel, Neg, Abs, TII))
533 bool AMDGPUDAGToDAGISel::FoldDotOperands(unsigned Opcode,
534 const R600InstrInfo *TII, std::vector<SDValue> &Ops) {
536 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_X),
537 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Y),
538 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_Z),
539 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_W),
540 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_X),
541 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y),
542 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z),
543 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W)
546 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_sel_X),
547 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_sel_Y),
548 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_sel_Z),
549 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_sel_W),
550 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_sel_X),
551 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_sel_Y),
552 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_sel_Z),
553 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_sel_W)
556 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_X),
557 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Y),
558 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Z),
559 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_W),
560 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_X),
561 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Y),
562 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_Z),
563 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_neg_W)
566 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_X),
567 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Y),
568 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_Z),
569 TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_abs_W),
570 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_X),
571 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Y),
572 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_Z),
573 TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_abs_W)
576 for (unsigned i = 0; i < 8; i++) {
577 if (OperandIdx[i] < 0)
579 SDValue &Src = Ops[OperandIdx[i] - 1];
580 SDValue &Sel = Ops[SelIdx[i] - 1];
581 SDValue &Neg = Ops[NegIdx[i] - 1];
582 SDValue &Abs = Ops[AbsIdx[i] - 1];
583 if (FoldOperand(Src, Sel, Neg, Abs, TII))
589 bool AMDGPUDAGToDAGISel::checkType(const Value *ptr, unsigned int addrspace) {
593 Type *ptrType = ptr->getType();
594 return dyn_cast<PointerType>(ptrType)->getAddressSpace() == addrspace;
597 bool AMDGPUDAGToDAGISel::isGlobalStore(const StoreSDNode *N) {
598 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
601 bool AMDGPUDAGToDAGISel::isPrivateStore(const StoreSDNode *N) {
602 return (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
603 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
604 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS));
607 bool AMDGPUDAGToDAGISel::isLocalStore(const StoreSDNode *N) {
608 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
611 bool AMDGPUDAGToDAGISel::isRegionStore(const StoreSDNode *N) {
612 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
615 bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
617 return checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS);
619 return checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_BUFFER_0 + CbId);
622 bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
623 return checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS);
626 bool AMDGPUDAGToDAGISel::isParamLoad(const LoadSDNode *N) const {
627 return checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS);
630 bool AMDGPUDAGToDAGISel::isLocalLoad(const LoadSDNode *N) const {
631 return checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS);
634 bool AMDGPUDAGToDAGISel::isRegionLoad(const LoadSDNode *N) const {
635 return checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS);
638 bool AMDGPUDAGToDAGISel::isCPLoad(const LoadSDNode *N) const {
639 MachineMemOperand *MMO = N->getMemOperand();
640 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
642 const Value *V = MMO->getValue();
643 const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V);
644 if (PSV && PSV == PseudoSourceValue::getConstantPool()) {
652 bool AMDGPUDAGToDAGISel::isPrivateLoad(const LoadSDNode *N) const {
653 if (checkType(N->getSrcValue(), AMDGPUAS::PRIVATE_ADDRESS)) {
654 // Check to make sure we are not a constant pool load or a constant load
655 // that is marked as a private load
656 if (isCPLoad(N) || isConstantLoad(N, -1)) {
660 if (!checkType(N->getSrcValue(), AMDGPUAS::LOCAL_ADDRESS)
661 && !checkType(N->getSrcValue(), AMDGPUAS::GLOBAL_ADDRESS)
662 && !checkType(N->getSrcValue(), AMDGPUAS::REGION_ADDRESS)
663 && !checkType(N->getSrcValue(), AMDGPUAS::CONSTANT_ADDRESS)
664 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_D_ADDRESS)
665 && !checkType(N->getSrcValue(), AMDGPUAS::PARAM_I_ADDRESS)) {
671 const char *AMDGPUDAGToDAGISel::getPassName() const {
672 return "AMDGPU DAG->DAG Pattern Instruction Selection";
680 //===----------------------------------------------------------------------===//
682 //===----------------------------------------------------------------------===//
684 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
686 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
687 IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, true);
693 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
694 SDValue& BaseReg, SDValue &Offset) {
695 if (!dyn_cast<ConstantSDNode>(Addr)) {
697 Offset = CurDAG->getIntPtrConstant(0, true);
703 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
705 ConstantSDNode * IMMOffset;
707 if (Addr.getOpcode() == ISD::ADD
708 && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
709 && isInt<16>(IMMOffset->getZExtValue())) {
711 Base = Addr.getOperand(0);
712 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
714 // If the pointer address is constant, we can move it to the offset field.
715 } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
716 && isInt<16>(IMMOffset->getZExtValue())) {
717 Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
718 SDLoc(CurDAG->getEntryNode()),
719 AMDGPU::ZERO, MVT::i32);
720 Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), MVT::i32);
724 // Default case, no offset
726 Offset = CurDAG->getTargetConstant(0, MVT::i32);
730 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
734 if ((C = dyn_cast<ConstantSDNode>(Addr))) {
735 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
736 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
737 } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
738 (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
739 Base = Addr.getOperand(0);
740 Offset = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);
743 Offset = CurDAG->getTargetConstant(0, MVT::i32);
749 SDValue AMDGPUDAGToDAGISel::SimplifyI24(SDValue &Op) {
750 APInt Demanded = APInt(32, 0x00FFFFFF);
751 APInt KnownZero, KnownOne;
752 TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true);
753 const TargetLowering *TLI = getTargetLowering();
754 if (TLI->SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) {
755 CurDAG->ReplaceAllUsesWith(Op, TLO.New);
756 CurDAG->RepositionNode(Op.getNode(), TLO.New.getNode());
757 return SimplifyI24(TLO.New);
763 bool AMDGPUDAGToDAGISel::SelectI24(SDValue Op, SDValue &I24) {
765 assert(Op.getValueType() == MVT::i32);
767 if (CurDAG->ComputeNumSignBits(Op) == 9) {
768 I24 = SimplifyI24(Op);
774 bool AMDGPUDAGToDAGISel::SelectU24(SDValue Op, SDValue &U24) {
777 CurDAG->ComputeMaskedBits(Op, KnownZero, KnownOne);
779 assert (Op.getValueType() == MVT::i32);
781 // ANY_EXTEND and EXTLOAD operations can only be done on types smaller than
782 // i32. These smaller types are legal to use with the i24 instructions.
783 if ((KnownZero & APInt(KnownZero.getBitWidth(), 0xFF000000)) == 0xFF000000 ||
784 Op.getOpcode() == ISD::ANY_EXTEND ||
785 ISD::isEXTLoad(Op.getNode())) {
786 U24 = SimplifyI24(Op);
792 void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
794 if (Subtarget.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
798 // Go over all selected nodes and try to fold them a bit more
799 const AMDGPUTargetLowering& Lowering =
800 (*(const AMDGPUTargetLowering*)getTargetLowering());
801 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
802 E = CurDAG->allnodes_end(); I != E; ++I) {
805 switch (Node->getOpcode()) {
806 // Fix the register class in copy to CopyToReg nodes - ISel will always
807 // use SReg classes for 64-bit copies, but this is not always what we want.
808 case ISD::CopyToReg: {
809 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
810 SDValue Val = Node->getOperand(2);
811 const TargetRegisterClass *RC = RegInfo->getRegClass(Reg);
812 if (RC != &AMDGPU::SReg_64RegClass) {
816 if (!Val.getNode()->isMachineOpcode() ||
817 Val.getNode()->getMachineOpcode() == AMDGPU::IMPLICIT_DEF) {
821 const MCInstrDesc Desc = TM.getInstrInfo()->get(Val.getNode()->getMachineOpcode());
822 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
823 RegInfo->setRegClass(Reg, TRI->getRegClass(Desc.OpInfo[0].RegClass));
828 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
832 SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
833 if (ResNode != Node) {
834 ReplaceUses(Node, ResNode);