1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPURegisterInfo.h"
20 #include "AMDGPUSubtarget.h"
21 #include "AMDILIntrinsicInfo.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DiagnosticInfo.h"
32 #include "llvm/IR/DiagnosticPrinter.h"
38 /// Diagnostic information for unimplemented or unsupported feature reporting.
39 class DiagnosticInfoUnsupported : public DiagnosticInfo {
41 const Twine &Description;
46 static int getKindID() {
48 KindID = llvm::getNextAvailablePluginDiagnosticKind();
53 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
54 DiagnosticSeverity Severity = DS_Error)
55 : DiagnosticInfo(getKindID(), Severity),
59 const Function &getFunction() const { return Fn; }
60 const Twine &getDescription() const { return Description; }
62 void print(DiagnosticPrinter &DP) const override {
63 DP << "unsupported " << getDescription() << " in " << Fn.getName();
66 static bool classof(const DiagnosticInfo *DI) {
67 return DI->getKind() == getKindID();
71 int DiagnosticInfoUnsupported::KindID = 0;
75 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
76 CCValAssign::LocInfo LocInfo,
77 ISD::ArgFlagsTy ArgFlags, CCState &State) {
78 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
79 ArgFlags.getOrigAlign());
80 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
85 #include "AMDGPUGenCallingConv.inc"
87 // Find a larger type to do a load / store of a vector with.
88 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
89 unsigned StoreSize = VT.getStoreSizeInBits();
91 return EVT::getIntegerVT(Ctx, StoreSize);
93 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
94 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
97 // Type for a vector that will be loaded to.
98 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
99 unsigned StoreSize = VT.getStoreSizeInBits();
101 return EVT::getIntegerVT(Ctx, 32);
103 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
106 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
107 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
109 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
111 // Initialize target lowering borrowed from AMDIL
114 // We need to custom lower some of the intrinsics
115 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
117 // Library functions. These default to Expand, but we have instructions
119 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
120 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
121 setOperationAction(ISD::FPOW, MVT::f32, Legal);
122 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
123 setOperationAction(ISD::FABS, MVT::f32, Legal);
124 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
125 setOperationAction(ISD::FRINT, MVT::f32, Legal);
126 setOperationAction(ISD::FROUND, MVT::f32, Legal);
127 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
129 // Lower floating point store/load to integer store/load to reduce the number
130 // of patterns in tablegen.
131 setOperationAction(ISD::STORE, MVT::f32, Promote);
132 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
134 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
135 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
137 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
138 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
140 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
141 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
143 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
144 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
146 setOperationAction(ISD::STORE, MVT::f64, Promote);
147 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
149 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
150 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
152 // Custom lowering of vector stores is required for local address space
154 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
155 // XXX: Native v2i32 local address space stores are possible, but not
156 // currently implemented.
157 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
159 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
160 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
161 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
163 // XXX: This can be change to Custom, once ExpandVectorStores can
164 // handle 64-bit stores.
165 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
167 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
168 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
169 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
170 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
171 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
174 setOperationAction(ISD::LOAD, MVT::f32, Promote);
175 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
177 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
178 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
180 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
181 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
183 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
184 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
186 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
187 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
189 setOperationAction(ISD::LOAD, MVT::f64, Promote);
190 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
192 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
193 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
195 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
196 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
197 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
198 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
199 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
200 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
201 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
202 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
203 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
204 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
206 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
207 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
209 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
210 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
212 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
213 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
214 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
215 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
216 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
217 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
219 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
221 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
222 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
223 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
224 setOperationAction(ISD::FRINT, MVT::f64, Custom);
225 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
228 if (!Subtarget->hasBFI()) {
229 // fcopysign can be done in a single instruction with BFI.
230 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
231 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
234 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
235 for (MVT VT : ScalarIntVTs) {
236 setOperationAction(ISD::SREM, VT, Expand);
237 setOperationAction(ISD::SDIV, VT, Custom);
239 // GPU does not have divrem function for signed or unsigned.
240 setOperationAction(ISD::SDIVREM, VT, Expand);
241 setOperationAction(ISD::UDIVREM, VT, Custom);
243 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
244 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
245 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
247 setOperationAction(ISD::BSWAP, VT, Expand);
248 setOperationAction(ISD::CTTZ, VT, Expand);
249 setOperationAction(ISD::CTLZ, VT, Expand);
252 if (!Subtarget->hasBCNT(32))
253 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
255 if (!Subtarget->hasBCNT(64))
256 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
258 // The hardware supports 32-bit ROTR, but not ROTL.
259 setOperationAction(ISD::ROTL, MVT::i32, Expand);
260 setOperationAction(ISD::ROTL, MVT::i64, Expand);
261 setOperationAction(ISD::ROTR, MVT::i64, Expand);
263 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
264 setOperationAction(ISD::MUL, MVT::i64, Expand);
265 setOperationAction(ISD::MULHU, MVT::i64, Expand);
266 setOperationAction(ISD::MULHS, MVT::i64, Expand);
267 setOperationAction(ISD::SUB, MVT::i64, Expand);
268 setOperationAction(ISD::UDIV, MVT::i32, Expand);
269 setOperationAction(ISD::UREM, MVT::i32, Expand);
270 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
271 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
273 static const MVT::SimpleValueType VectorIntTypes[] = {
274 MVT::v2i32, MVT::v4i32
277 for (MVT VT : VectorIntTypes) {
278 // Expand the following operations for the current type by default.
279 setOperationAction(ISD::ADD, VT, Expand);
280 setOperationAction(ISD::AND, VT, Expand);
281 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
282 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
283 setOperationAction(ISD::MUL, VT, Expand);
284 setOperationAction(ISD::OR, VT, Expand);
285 setOperationAction(ISD::SHL, VT, Expand);
286 setOperationAction(ISD::SRA, VT, Expand);
287 setOperationAction(ISD::SRL, VT, Expand);
288 setOperationAction(ISD::ROTL, VT, Expand);
289 setOperationAction(ISD::ROTR, VT, Expand);
290 setOperationAction(ISD::SUB, VT, Expand);
291 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
292 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
293 // TODO: Implement custom UREM / SREM routines.
294 setOperationAction(ISD::SDIV, VT, Custom);
295 setOperationAction(ISD::UDIV, VT, Expand);
296 setOperationAction(ISD::SREM, VT, Expand);
297 setOperationAction(ISD::UREM, VT, Expand);
298 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
299 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
300 setOperationAction(ISD::SDIVREM, VT, Expand);
301 setOperationAction(ISD::UDIVREM, VT, Custom);
302 setOperationAction(ISD::SELECT, VT, Expand);
303 setOperationAction(ISD::VSELECT, VT, Expand);
304 setOperationAction(ISD::XOR, VT, Expand);
305 setOperationAction(ISD::BSWAP, VT, Expand);
306 setOperationAction(ISD::CTPOP, VT, Expand);
307 setOperationAction(ISD::CTTZ, VT, Expand);
308 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
309 setOperationAction(ISD::CTLZ, VT, Expand);
310 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
313 static const MVT::SimpleValueType FloatVectorTypes[] = {
314 MVT::v2f32, MVT::v4f32
317 for (MVT VT : FloatVectorTypes) {
318 setOperationAction(ISD::FABS, VT, Expand);
319 setOperationAction(ISD::FADD, VT, Expand);
320 setOperationAction(ISD::FCEIL, VT, Expand);
321 setOperationAction(ISD::FCOS, VT, Expand);
322 setOperationAction(ISD::FDIV, VT, Expand);
323 setOperationAction(ISD::FPOW, VT, Expand);
324 setOperationAction(ISD::FFLOOR, VT, Expand);
325 setOperationAction(ISD::FTRUNC, VT, Expand);
326 setOperationAction(ISD::FMUL, VT, Expand);
327 setOperationAction(ISD::FRINT, VT, Expand);
328 setOperationAction(ISD::FNEARBYINT, VT, Expand);
329 setOperationAction(ISD::FSQRT, VT, Expand);
330 setOperationAction(ISD::FSIN, VT, Expand);
331 setOperationAction(ISD::FSUB, VT, Expand);
332 setOperationAction(ISD::FNEG, VT, Expand);
333 setOperationAction(ISD::SELECT, VT, Expand);
334 setOperationAction(ISD::VSELECT, VT, Expand);
335 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
338 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
339 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
341 setTargetDAGCombine(ISD::MUL);
342 setTargetDAGCombine(ISD::SELECT_CC);
344 setSchedulingPreference(Sched::RegPressure);
345 setJumpIsExpensive(true);
347 // There are no integer divide instructions, and these expand to a pretty
348 // large sequence of instructions.
349 setIntDivIsCheap(false);
351 // TODO: Investigate this when 64-bit divides are implemented.
352 addBypassSlowDiv(64, 32);
354 // FIXME: Need to really handle these.
355 MaxStoresPerMemcpy = 4096;
356 MaxStoresPerMemmove = 4096;
357 MaxStoresPerMemset = 4096;
360 //===----------------------------------------------------------------------===//
361 // Target Information
362 //===----------------------------------------------------------------------===//
364 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
368 // The backend supports 32 and 64 bit floating point immediates.
369 // FIXME: Why are we reporting vectors of FP immediates as legal?
370 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
371 EVT ScalarVT = VT.getScalarType();
372 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
375 // We don't want to shrink f64 / f32 constants.
376 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
377 EVT ScalarVT = VT.getScalarType();
378 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
381 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
383 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
386 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
387 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
389 return ((LScalarSize <= CastScalarSize) ||
390 (CastScalarSize >= 32) ||
394 //===---------------------------------------------------------------------===//
396 //===---------------------------------------------------------------------===//
398 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
399 assert(VT.isFloatingPoint());
400 return VT == MVT::f32;
403 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
404 assert(VT.isFloatingPoint());
405 return VT == MVT::f32;
408 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
409 // Truncate is just accessing a subregister.
410 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
413 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
414 // Truncate is just accessing a subregister.
415 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
416 (Dest->getPrimitiveSizeInBits() % 32 == 0);
419 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
420 const DataLayout *DL = getDataLayout();
421 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
422 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
424 return SrcSize == 32 && DestSize == 64;
427 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
428 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
429 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
430 // this will enable reducing 64-bit operations the 32-bit, which is always
432 return Src == MVT::i32 && Dest == MVT::i64;
435 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
436 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
437 // limited number of native 64-bit operations. Shrinking an operation to fit
438 // in a single 32-bit register should always be helpful. As currently used,
439 // this is much less general than the name suggests, and is only used in
440 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
441 // not profitable, and may actually be harmful.
442 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
445 //===---------------------------------------------------------------------===//
446 // TargetLowering Callbacks
447 //===---------------------------------------------------------------------===//
449 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
450 const SmallVectorImpl<ISD::InputArg> &Ins) const {
452 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
455 SDValue AMDGPUTargetLowering::LowerReturn(
457 CallingConv::ID CallConv,
459 const SmallVectorImpl<ISD::OutputArg> &Outs,
460 const SmallVectorImpl<SDValue> &OutVals,
461 SDLoc DL, SelectionDAG &DAG) const {
462 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
465 //===---------------------------------------------------------------------===//
466 // Target specific lowering
467 //===---------------------------------------------------------------------===//
469 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
470 SmallVectorImpl<SDValue> &InVals) const {
471 SDValue Callee = CLI.Callee;
472 SelectionDAG &DAG = CLI.DAG;
474 const Function &Fn = *DAG.getMachineFunction().getFunction();
476 StringRef FuncName("<unknown>");
478 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
479 FuncName = G->getSymbol();
480 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
481 FuncName = G->getGlobal()->getName();
483 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
484 DAG.getContext()->diagnose(NoCalls);
488 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
489 SelectionDAG &DAG) const {
490 switch (Op.getOpcode()) {
492 Op.getNode()->dump();
493 llvm_unreachable("Custom lowering code for this"
494 "instruction is not implemented yet!");
496 // AMDGPU DAG lowering.
497 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
498 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
499 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
500 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
501 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
502 case ISD::SDIV: return LowerSDIV(Op, DAG);
503 case ISD::SREM: return LowerSREM(Op, DAG);
504 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
505 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
506 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
507 case ISD::FRINT: return LowerFRINT(Op, DAG);
508 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
509 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
510 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
512 // AMDIL DAG lowering.
513 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
518 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
519 SmallVectorImpl<SDValue> &Results,
520 SelectionDAG &DAG) const {
521 switch (N->getOpcode()) {
522 case ISD::SIGN_EXTEND_INREG:
523 // Different parts of legalization seem to interpret which type of
524 // sign_extend_inreg is the one to check for custom lowering. The extended
525 // from type is what really matters, but some places check for custom
526 // lowering of the result type. This results in trying to use
527 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
528 // nothing here and let the illegal result integer be handled normally.
531 SDValue Op = SDValue(N, 0);
533 EVT VT = Op.getValueType();
534 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
535 N->getOperand(0), N->getOperand(1));
536 Results.push_back(UDIVREM);
540 SDValue Op = SDValue(N, 0);
542 EVT VT = Op.getValueType();
543 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
544 N->getOperand(0), N->getOperand(1));
545 Results.push_back(UDIVREM.getValue(1));
549 SDValue Op = SDValue(N, 0);
551 EVT VT = Op.getValueType();
552 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
554 SDValue one = DAG.getConstant(1, HalfVT);
555 SDValue zero = DAG.getConstant(0, HalfVT);
558 SDValue LHS = N->getOperand(0);
559 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
560 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
562 SDValue RHS = N->getOperand(1);
563 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
564 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
566 // Get Speculative values
567 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
568 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
570 SDValue REM_Hi = zero;
571 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
573 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
574 SDValue DIV_Lo = zero;
576 const unsigned halfBitWidth = HalfVT.getSizeInBits();
578 for (unsigned i = 0; i < halfBitWidth; ++i) {
579 SDValue POS = DAG.getConstant(halfBitWidth - i - 1, HalfVT);
580 // Get Value of high bit
582 if (halfBitWidth == 32 && Subtarget->hasBFE()) {
583 HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
585 HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
586 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
589 SDValue Carry = DAG.getNode(ISD::SRL, DL, HalfVT, REM_Lo,
590 DAG.getConstant(halfBitWidth - 1, HalfVT));
591 REM_Hi = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Hi, one);
592 REM_Hi = DAG.getNode(ISD::OR, DL, HalfVT, REM_Hi, Carry);
594 REM_Lo = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Lo, one);
595 REM_Lo = DAG.getNode(ISD::OR, DL, HalfVT, REM_Lo, HBit);
598 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
600 SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
601 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETGE);
603 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
607 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
609 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETGE);
610 REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
611 REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
614 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
615 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
616 Results.push_back(DIV);
617 Results.push_back(REM);
625 // FIXME: This implements accesses to initialized globals in the constant
626 // address space by copying them to private and accessing that. It does not
627 // properly handle illegal types or vectors. The private vector loads are not
628 // scalarized, and the illegal scalars hit an assertion. This technique will not
629 // work well with large initializers, and this should eventually be
630 // removed. Initialized globals should be placed into a data section that the
631 // runtime will load into a buffer before the kernel is executed. Uses of the
632 // global need to be replaced with a pointer loaded from an implicit kernel
633 // argument into this buffer holding the copy of the data, which will remove the
634 // need for any of this.
635 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
636 const GlobalValue *GV,
637 const SDValue &InitPtr,
639 SelectionDAG &DAG) const {
640 const DataLayout *TD = getTargetMachine().getDataLayout();
642 Type *InitTy = Init->getType();
644 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
645 EVT VT = EVT::getEVT(InitTy);
646 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
647 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
648 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
649 TD->getPrefTypeAlignment(InitTy));
652 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
653 EVT VT = EVT::getEVT(CFP->getType());
654 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
655 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
656 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
657 TD->getPrefTypeAlignment(CFP->getType()));
660 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
661 const StructLayout *SL = TD->getStructLayout(ST);
663 EVT PtrVT = InitPtr.getValueType();
664 SmallVector<SDValue, 8> Chains;
666 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
667 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
668 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
670 Constant *Elt = Init->getAggregateElement(I);
671 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
674 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
677 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
678 EVT PtrVT = InitPtr.getValueType();
680 unsigned NumElements;
681 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
682 NumElements = AT->getNumElements();
683 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
684 NumElements = VT->getNumElements();
686 llvm_unreachable("Unexpected type");
688 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
689 SmallVector<SDValue, 8> Chains;
690 for (unsigned i = 0; i < NumElements; ++i) {
691 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
692 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
694 Constant *Elt = Init->getAggregateElement(i);
695 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
698 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
701 if (isa<UndefValue>(Init)) {
702 EVT VT = EVT::getEVT(InitTy);
703 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
704 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
705 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
706 TD->getPrefTypeAlignment(InitTy));
710 llvm_unreachable("Unhandled constant initializer");
713 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
715 SelectionDAG &DAG) const {
717 const DataLayout *TD = getTargetMachine().getDataLayout();
718 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
719 const GlobalValue *GV = G->getGlobal();
721 switch (G->getAddressSpace()) {
722 default: llvm_unreachable("Global Address lowering not implemented for this "
724 case AMDGPUAS::LOCAL_ADDRESS: {
725 // XXX: What does the value of G->getOffset() mean?
726 assert(G->getOffset() == 0 &&
727 "Do not know what to do with an non-zero offset");
730 if (MFI->LocalMemoryObjects.count(GV) == 0) {
731 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
732 Offset = MFI->LDSSize;
733 MFI->LocalMemoryObjects[GV] = Offset;
734 // XXX: Account for alignment?
735 MFI->LDSSize += Size;
737 Offset = MFI->LocalMemoryObjects[GV];
740 return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
742 case AMDGPUAS::CONSTANT_ADDRESS: {
743 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
744 Type *EltType = GV->getType()->getElementType();
745 unsigned Size = TD->getTypeAllocSize(EltType);
746 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
748 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
749 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
751 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
752 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
754 const GlobalVariable *Var = cast<GlobalVariable>(GV);
755 if (!Var->hasInitializer()) {
756 // This has no use, but bugpoint will hit it.
757 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
760 const Constant *Init = Var->getInitializer();
761 SmallVector<SDNode*, 8> WorkList;
763 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
764 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
765 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
767 WorkList.push_back(*I);
769 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
770 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
771 E = WorkList.end(); I != E; ++I) {
772 SmallVector<SDValue, 8> Ops;
773 Ops.push_back(Chain);
774 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
775 Ops.push_back((*I)->getOperand(i));
777 DAG.UpdateNodeOperands(*I, Ops);
779 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
784 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
785 SelectionDAG &DAG) const {
786 SmallVector<SDValue, 8> Args;
787 SDValue A = Op.getOperand(0);
788 SDValue B = Op.getOperand(1);
790 DAG.ExtractVectorElements(A, Args);
791 DAG.ExtractVectorElements(B, Args);
793 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
796 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
797 SelectionDAG &DAG) const {
799 SmallVector<SDValue, 8> Args;
800 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
801 EVT VT = Op.getValueType();
802 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
803 VT.getVectorNumElements());
805 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
808 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
809 SelectionDAG &DAG) const {
811 MachineFunction &MF = DAG.getMachineFunction();
812 const AMDGPUFrameLowering *TFL =
813 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
815 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
817 unsigned FrameIndex = FIN->getIndex();
818 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
819 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
823 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
824 SelectionDAG &DAG) const {
825 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
827 EVT VT = Op.getValueType();
829 switch (IntrinsicID) {
831 case AMDGPUIntrinsic::AMDGPU_abs:
832 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
833 return LowerIntrinsicIABS(Op, DAG);
834 case AMDGPUIntrinsic::AMDGPU_lrp:
835 return LowerIntrinsicLRP(Op, DAG);
836 case AMDGPUIntrinsic::AMDGPU_fract:
837 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
838 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
840 case AMDGPUIntrinsic::AMDGPU_clamp:
841 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
842 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
843 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
845 case Intrinsic::AMDGPU_div_scale:
846 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, VT,
847 Op.getOperand(1), Op.getOperand(2));
849 case Intrinsic::AMDGPU_div_fmas:
850 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
851 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
853 case Intrinsic::AMDGPU_div_fixup:
854 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
855 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
857 case Intrinsic::AMDGPU_trig_preop:
858 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
859 Op.getOperand(1), Op.getOperand(2));
861 case Intrinsic::AMDGPU_rcp:
862 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
864 case Intrinsic::AMDGPU_rsq:
865 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
867 case AMDGPUIntrinsic::AMDGPU_imax:
868 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
870 case AMDGPUIntrinsic::AMDGPU_umax:
871 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
873 case AMDGPUIntrinsic::AMDGPU_imin:
874 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
876 case AMDGPUIntrinsic::AMDGPU_umin:
877 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
880 case AMDGPUIntrinsic::AMDGPU_umul24:
881 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
882 Op.getOperand(1), Op.getOperand(2));
884 case AMDGPUIntrinsic::AMDGPU_imul24:
885 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
886 Op.getOperand(1), Op.getOperand(2));
888 case AMDGPUIntrinsic::AMDGPU_umad24:
889 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
890 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
892 case AMDGPUIntrinsic::AMDGPU_imad24:
893 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
894 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
896 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
897 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
899 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
900 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
902 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
903 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
905 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
906 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
908 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
909 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
914 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
915 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
920 case AMDGPUIntrinsic::AMDGPU_bfi:
921 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
926 case AMDGPUIntrinsic::AMDGPU_bfm:
927 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
931 case AMDGPUIntrinsic::AMDGPU_brev:
932 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
934 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
935 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
937 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
938 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
942 ///IABS(a) = SMAX(sub(0, a), a)
943 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
944 SelectionDAG &DAG) const {
946 EVT VT = Op.getValueType();
947 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
950 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
953 /// Linear Interpolation
954 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
955 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
956 SelectionDAG &DAG) const {
958 EVT VT = Op.getValueType();
959 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
960 DAG.getConstantFP(1.0f, MVT::f32),
962 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
964 return DAG.getNode(ISD::FADD, DL, VT,
965 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
969 /// \brief Generate Min/Max node
970 SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
971 SelectionDAG &DAG) const {
973 EVT VT = N->getValueType(0);
975 SDValue LHS = N->getOperand(0);
976 SDValue RHS = N->getOperand(1);
977 SDValue True = N->getOperand(2);
978 SDValue False = N->getOperand(3);
979 SDValue CC = N->getOperand(4);
981 if (VT != MVT::f32 ||
982 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
986 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1000 llvm_unreachable("Operation should already be optimised!");
1007 unsigned Opc = (LHS == True) ? AMDGPUISD::FMIN : AMDGPUISD::FMAX;
1008 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1016 unsigned Opc = (LHS == True) ? AMDGPUISD::FMAX : AMDGPUISD::FMIN;
1017 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1019 case ISD::SETCC_INVALID:
1020 llvm_unreachable("Invalid setcc condcode!");
1025 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
1026 SelectionDAG &DAG) const {
1027 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
1028 EVT MemEltVT = Load->getMemoryVT().getVectorElementType();
1029 EVT EltVT = Op.getValueType().getVectorElementType();
1030 EVT PtrVT = Load->getBasePtr().getValueType();
1031 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1032 SmallVector<SDValue, 8> Loads;
1035 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1036 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1037 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), PtrVT));
1038 Loads.push_back(DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1039 Load->getChain(), Ptr,
1040 MachinePointerInfo(Load->getMemOperand()->getValue()),
1041 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1042 Load->getAlignment()));
1044 return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(), Loads);
1047 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1048 SelectionDAG &DAG) const {
1049 StoreSDNode *Store = cast<StoreSDNode>(Op);
1050 EVT MemVT = Store->getMemoryVT();
1051 unsigned MemBits = MemVT.getSizeInBits();
1053 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1054 // truncating store into an i32 store.
1055 // XXX: We could also handle optimize other vector bitwidths.
1056 if (!MemVT.isVector() || MemBits > 32) {
1061 SDValue Value = Store->getValue();
1062 EVT VT = Value.getValueType();
1063 EVT ElemVT = VT.getVectorElementType();
1064 SDValue Ptr = Store->getBasePtr();
1065 EVT MemEltVT = MemVT.getVectorElementType();
1066 unsigned MemEltBits = MemEltVT.getSizeInBits();
1067 unsigned MemNumElements = MemVT.getVectorNumElements();
1068 unsigned PackedSize = MemVT.getStoreSizeInBits();
1069 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1071 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1073 SDValue PackedValue;
1074 for (unsigned i = 0; i < MemNumElements; ++i) {
1075 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1076 DAG.getConstant(i, MVT::i32));
1077 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1078 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1080 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1081 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1086 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1090 if (PackedSize < 32) {
1091 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1092 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1093 Store->getMemOperand()->getPointerInfo(),
1095 Store->isNonTemporal(), Store->isVolatile(),
1096 Store->getAlignment());
1099 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1100 Store->getMemOperand()->getPointerInfo(),
1101 Store->isVolatile(), Store->isNonTemporal(),
1102 Store->getAlignment());
1105 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1106 SelectionDAG &DAG) const {
1107 StoreSDNode *Store = cast<StoreSDNode>(Op);
1108 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1109 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1110 EVT PtrVT = Store->getBasePtr().getValueType();
1111 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1114 SmallVector<SDValue, 8> Chains;
1116 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1117 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1118 Store->getValue(), DAG.getConstant(i, MVT::i32));
1119 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT,
1120 Store->getBasePtr(),
1121 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
1123 Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1124 MachinePointerInfo(Store->getMemOperand()->getValue()),
1125 MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
1126 Store->getAlignment()));
1128 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1131 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1133 LoadSDNode *Load = cast<LoadSDNode>(Op);
1134 ISD::LoadExtType ExtType = Load->getExtensionType();
1135 EVT VT = Op.getValueType();
1136 EVT MemVT = Load->getMemoryVT();
1138 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1139 // We can do the extload to 32-bits, and then need to separately extend to
1142 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1146 Load->getMemOperand());
1147 return DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32);
1150 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1151 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1152 // FIXME: Copied from PPC
1153 // First, load into 32 bits, then truncate to 1 bit.
1155 SDValue Chain = Load->getChain();
1156 SDValue BasePtr = Load->getBasePtr();
1157 MachineMemOperand *MMO = Load->getMemOperand();
1159 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1160 BasePtr, MVT::i8, MMO);
1161 return DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
1164 // Lower loads constant address space global variable loads
1165 if (Load->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
1166 isa<GlobalVariable>(
1167 GetUnderlyingObject(Load->getMemOperand()->getValue()))) {
1169 SDValue Ptr = DAG.getZExtOrTrunc(Load->getBasePtr(), DL,
1170 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
1171 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1172 DAG.getConstant(2, MVT::i32));
1173 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1174 Load->getChain(), Ptr,
1175 DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2));
1178 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1179 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1183 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1184 DAG.getConstant(2, MVT::i32));
1185 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1186 Load->getChain(), Ptr,
1187 DAG.getTargetConstant(0, MVT::i32),
1189 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1191 DAG.getConstant(0x3, MVT::i32));
1192 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1193 DAG.getConstant(3, MVT::i32));
1195 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1197 EVT MemEltVT = MemVT.getScalarType();
1198 if (ExtType == ISD::SEXTLOAD) {
1199 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1200 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
1203 return DAG.getZeroExtendInReg(Ret, DL, MemEltVT);
1206 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1208 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1209 if (Result.getNode()) {
1213 StoreSDNode *Store = cast<StoreSDNode>(Op);
1214 SDValue Chain = Store->getChain();
1215 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1216 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1217 Store->getValue().getValueType().isVector()) {
1218 return SplitVectorStore(Op, DAG);
1221 EVT MemVT = Store->getMemoryVT();
1222 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1223 MemVT.bitsLT(MVT::i32)) {
1225 if (Store->getMemoryVT() == MVT::i8) {
1227 } else if (Store->getMemoryVT() == MVT::i16) {
1230 SDValue BasePtr = Store->getBasePtr();
1231 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1232 DAG.getConstant(2, MVT::i32));
1233 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1234 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1236 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1237 DAG.getConstant(0x3, MVT::i32));
1239 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1240 DAG.getConstant(3, MVT::i32));
1242 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1245 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1247 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1248 MaskedValue, ShiftAmt);
1250 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1252 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1253 DAG.getConstant(0xffffffff, MVT::i32));
1254 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1256 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1257 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1258 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1263 SDValue AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const {
1265 EVT OVT = Op.getValueType();
1266 SDValue LHS = Op.getOperand(0);
1267 SDValue RHS = Op.getOperand(1);
1270 if (!OVT.isVector()) {
1273 } else if (OVT.getVectorNumElements() == 2) {
1276 } else if (OVT.getVectorNumElements() == 4) {
1280 unsigned bitsize = OVT.getScalarType().getSizeInBits();
1281 // char|short jq = ia ^ ib;
1282 SDValue jq = DAG.getNode(ISD::XOR, DL, OVT, LHS, RHS);
1284 // jq = jq >> (bitsize - 2)
1285 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
1288 jq = DAG.getNode(ISD::OR, DL, OVT, jq, DAG.getConstant(1, OVT));
1291 jq = DAG.getSExtOrTrunc(jq, DL, INTTY);
1293 // int ia = (int)LHS;
1294 SDValue ia = DAG.getSExtOrTrunc(LHS, DL, INTTY);
1296 // int ib, (int)RHS;
1297 SDValue ib = DAG.getSExtOrTrunc(RHS, DL, INTTY);
1299 // float fa = (float)ia;
1300 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);
1302 // float fb = (float)ib;
1303 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
1305 // float fq = native_divide(fa, fb);
1306 SDValue fq = DAG.getNode(AMDGPUISD::DIV_INF, DL, FLTTY, fa, fb);
1309 fq = DAG.getNode(ISD::FTRUNC, DL, FLTTY, fq);
1311 // float fqneg = -fq;
1312 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq);
1314 // float fr = mad(fqneg, fb, fa);
1315 SDValue fr = DAG.getNode(ISD::FADD, DL, FLTTY,
1316 DAG.getNode(ISD::MUL, DL, FLTTY, fqneg, fb), fa);
1318 // int iq = (int)fq;
1319 SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);
1322 fr = DAG.getNode(ISD::FABS, DL, FLTTY, fr);
1325 fb = DAG.getNode(ISD::FABS, DL, FLTTY, fb);
1327 // int cv = fr >= fb;
1329 if (INTTY == MVT::i32) {
1330 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
1332 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
1334 // jq = (cv ? jq : 0);
1335 jq = DAG.getNode(ISD::SELECT, DL, OVT, cv, jq,
1336 DAG.getConstant(0, OVT));
1338 iq = DAG.getSExtOrTrunc(iq, DL, OVT);
1339 iq = DAG.getNode(ISD::ADD, DL, OVT, iq, jq);
1343 SDValue AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const {
1345 EVT OVT = Op.getValueType();
1346 SDValue LHS = Op.getOperand(0);
1347 SDValue RHS = Op.getOperand(1);
1348 // The LowerSDIV32 function generates equivalent to the following IL.
1358 // ixor r10, r10, r11
1360 // ixor DST, r0, r10
1369 SDValue r10 = DAG.getSelectCC(DL,
1370 r0, DAG.getConstant(0, OVT),
1371 DAG.getConstant(-1, OVT),
1372 DAG.getConstant(0, OVT),
1376 SDValue r11 = DAG.getSelectCC(DL,
1377 r1, DAG.getConstant(0, OVT),
1378 DAG.getConstant(-1, OVT),
1379 DAG.getConstant(0, OVT),
1383 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1386 r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
1389 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1392 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
1395 r0 = DAG.getNode(ISD::UDIV, DL, OVT, r0, r1);
1397 // ixor r10, r10, r11
1398 r10 = DAG.getNode(ISD::XOR, DL, OVT, r10, r11);
1401 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1403 // ixor DST, r0, r10
1404 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1408 SDValue AMDGPUTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const {
1409 return SDValue(Op.getNode(), 0);
1412 SDValue AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
1413 EVT OVT = Op.getValueType().getScalarType();
1415 if (OVT == MVT::i64)
1416 return LowerSDIV64(Op, DAG);
1418 if (OVT.getScalarType() == MVT::i32)
1419 return LowerSDIV32(Op, DAG);
1421 if (OVT == MVT::i16 || OVT == MVT::i8) {
1422 // FIXME: We should be checking for the masked bits. This isn't reached
1423 // because i8 and i16 are not legal types.
1424 return LowerSDIV24(Op, DAG);
1427 return SDValue(Op.getNode(), 0);
1430 SDValue AMDGPUTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const {
1432 EVT OVT = Op.getValueType();
1433 SDValue LHS = Op.getOperand(0);
1434 SDValue RHS = Op.getOperand(1);
1435 // The LowerSREM32 function generates equivalent to the following IL.
1445 // umul r20, r20, r1
1448 // ixor DST, r0, r10
1457 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT);
1460 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT);
1463 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1466 r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
1469 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1472 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
1475 SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1);
1477 // umul r20, r20, r1
1478 r20 = DAG.getNode(AMDGPUISD::UMUL, DL, OVT, r20, r1);
1481 r0 = DAG.getNode(ISD::SUB, DL, OVT, r0, r20);
1484 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1486 // ixor DST, r0, r10
1487 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1491 SDValue AMDGPUTargetLowering::LowerSREM64(SDValue Op, SelectionDAG &DAG) const {
1492 return SDValue(Op.getNode(), 0);
1495 SDValue AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const {
1496 EVT OVT = Op.getValueType();
1498 if (OVT.getScalarType() == MVT::i64)
1499 return LowerSREM64(Op, DAG);
1501 if (OVT.getScalarType() == MVT::i32)
1502 return LowerSREM32(Op, DAG);
1504 return SDValue(Op.getNode(), 0);
1507 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1508 SelectionDAG &DAG) const {
1510 EVT VT = Op.getValueType();
1512 SDValue Num = Op.getOperand(0);
1513 SDValue Den = Op.getOperand(1);
1515 // RCP = URECIP(Den) = 2^32 / Den + e
1516 // e is rounding error.
1517 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1519 // RCP_LO = umulo(RCP, Den) */
1520 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
1522 // RCP_HI = mulhu (RCP, Den) */
1523 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1525 // NEG_RCP_LO = -RCP_LO
1526 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1529 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1530 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1533 // Calculate the rounding error from the URECIP instruction
1534 // E = mulhu(ABS_RCP_LO, RCP)
1535 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1537 // RCP_A_E = RCP + E
1538 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1540 // RCP_S_E = RCP - E
1541 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1543 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1544 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1547 // Quotient = mulhu(Tmp0, Num)
1548 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1550 // Num_S_Remainder = Quotient * Den
1551 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
1553 // Remainder = Num - Num_S_Remainder
1554 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1556 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1557 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1558 DAG.getConstant(-1, VT),
1559 DAG.getConstant(0, VT),
1561 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1562 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1564 DAG.getConstant(-1, VT),
1565 DAG.getConstant(0, VT),
1567 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1568 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1571 // Calculate Division result:
1573 // Quotient_A_One = Quotient + 1
1574 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1575 DAG.getConstant(1, VT));
1577 // Quotient_S_One = Quotient - 1
1578 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1579 DAG.getConstant(1, VT));
1581 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1582 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1583 Quotient, Quotient_A_One, ISD::SETEQ);
1585 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1586 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1587 Quotient_S_One, Div, ISD::SETEQ);
1589 // Calculate Rem result:
1591 // Remainder_S_Den = Remainder - Den
1592 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1594 // Remainder_A_Den = Remainder + Den
1595 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1597 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1598 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1599 Remainder, Remainder_S_Den, ISD::SETEQ);
1601 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1602 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1603 Remainder_A_Den, Rem, ISD::SETEQ);
1608 return DAG.getMergeValues(Ops, DL);
1611 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1613 SDValue Src = Op.getOperand(0);
1615 // result = trunc(src)
1616 // if (src > 0.0 && src != result)
1619 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1621 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1622 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1624 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1626 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1627 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1628 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1630 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1631 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1634 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1636 SDValue Src = Op.getOperand(0);
1638 assert(Op.getValueType() == MVT::f64);
1640 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1641 const SDValue One = DAG.getConstant(1, MVT::i32);
1643 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1645 // Extract the upper half, since this is where we will find the sign and
1647 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1649 const unsigned FractBits = 52;
1650 const unsigned ExpBits = 11;
1652 // Extract the exponent.
1653 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_I32, SL, MVT::i32,
1655 DAG.getConstant(FractBits - 32, MVT::i32),
1656 DAG.getConstant(ExpBits, MVT::i32));
1657 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1658 DAG.getConstant(1023, MVT::i32));
1660 // Extract the sign bit.
1661 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1662 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1664 // Extend back to to 64-bits.
1665 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1667 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1669 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1670 const SDValue FractMask
1671 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1673 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1674 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1675 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1677 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1679 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1681 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1682 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1684 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1685 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1687 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1690 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1692 SDValue Src = Op.getOperand(0);
1694 assert(Op.getValueType() == MVT::f64);
1696 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1697 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1698 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1700 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1701 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1703 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1705 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1706 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
1708 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1709 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1711 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1714 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1715 // FNEARBYINT and FRINT are the same, except in their handling of FP
1716 // exceptions. Those aren't really meaningful for us, and OpenCL only has
1717 // rint, so just treat them as equivalent.
1718 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1721 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1723 SDValue Src = Op.getOperand(0);
1725 // result = trunc(src);
1726 // if (src < 0.0 && src != result)
1729 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1731 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1732 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
1734 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1736 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
1737 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1738 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1740 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
1741 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1744 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1745 SelectionDAG &DAG) const {
1746 SDValue S0 = Op.getOperand(0);
1748 if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64)
1751 // f32 uint_to_fp i64
1752 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1753 DAG.getConstant(0, MVT::i32));
1754 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1755 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1756 DAG.getConstant(1, MVT::i32));
1757 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1758 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1759 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1760 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1763 SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
1765 SelectionDAG &DAG) const {
1766 MVT VT = Op.getSimpleValueType();
1768 SDValue Shift = DAG.getConstant(BitsDiff, VT);
1769 // Shift left by 'Shift' bits.
1770 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
1771 // Signed shift Right by 'Shift' bits.
1772 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
1775 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1776 SelectionDAG &DAG) const {
1777 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1778 MVT VT = Op.getSimpleValueType();
1779 MVT ScalarVT = VT.getScalarType();
1784 SDValue Src = Op.getOperand(0);
1787 // TODO: Don't scalarize on Evergreen?
1788 unsigned NElts = VT.getVectorNumElements();
1789 SmallVector<SDValue, 8> Args;
1790 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1792 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1793 for (unsigned I = 0; I < NElts; ++I)
1794 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1796 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1799 //===----------------------------------------------------------------------===//
1800 // Custom DAG optimizations
1801 //===----------------------------------------------------------------------===//
1803 static bool isU24(SDValue Op, SelectionDAG &DAG) {
1804 APInt KnownZero, KnownOne;
1805 EVT VT = Op.getValueType();
1806 DAG.computeKnownBits(Op, KnownZero, KnownOne);
1808 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1811 static bool isI24(SDValue Op, SelectionDAG &DAG) {
1812 EVT VT = Op.getValueType();
1814 // In order for this to be a signed 24-bit value, bit 23, must
1816 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1817 // as unsigned 24-bit values.
1818 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1821 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
1823 SelectionDAG &DAG = DCI.DAG;
1824 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1825 EVT VT = Op.getValueType();
1827 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
1828 APInt KnownZero, KnownOne;
1829 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
1830 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
1831 DCI.CommitTargetLoweringOpt(TLO);
1834 template <typename IntTy>
1835 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
1836 uint32_t Offset, uint32_t Width) {
1837 if (Width + Offset < 32) {
1838 IntTy Result = (Src0 << (32 - Offset - Width)) >> (32 - Width);
1839 return DAG.getConstant(Result, MVT::i32);
1842 return DAG.getConstant(Src0 >> Offset, MVT::i32);
1845 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
1846 DAGCombinerInfo &DCI) const {
1847 SelectionDAG &DAG = DCI.DAG;
1850 switch(N->getOpcode()) {
1853 EVT VT = N->getValueType(0);
1854 SDValue N0 = N->getOperand(0);
1855 SDValue N1 = N->getOperand(1);
1858 // FIXME: Add support for 24-bit multiply with 64-bit output on SI.
1859 if (VT.isVector() || VT.getSizeInBits() > 32)
1862 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
1863 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
1864 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
1865 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
1866 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
1867 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
1868 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
1869 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
1874 // We need to use sext even for MUL_U24, because MUL_U24 is used
1875 // for signed multiply of 8 and 16-bit types.
1876 SDValue Reg = DAG.getSExtOrTrunc(Mul, DL, VT);
1880 case AMDGPUISD::MUL_I24:
1881 case AMDGPUISD::MUL_U24: {
1882 SDValue N0 = N->getOperand(0);
1883 SDValue N1 = N->getOperand(1);
1884 simplifyI24(N0, DCI);
1885 simplifyI24(N1, DCI);
1888 case ISD::SELECT_CC: {
1889 return CombineMinMax(N, DAG);
1891 case AMDGPUISD::BFE_I32:
1892 case AMDGPUISD::BFE_U32: {
1893 assert(!N->getValueType(0).isVector() &&
1894 "Vector handling of BFE not implemented");
1895 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
1899 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
1901 return DAG.getConstant(0, MVT::i32);
1903 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
1907 SDValue BitsFrom = N->getOperand(0);
1908 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
1910 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
1912 if (OffsetVal == 0) {
1913 // This is already sign / zero extended, so try to fold away extra BFEs.
1914 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
1916 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
1917 if (OpSignBits >= SignBits)
1920 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
1922 // This is a sign_extend_inreg. Replace it to take advantage of existing
1923 // DAG Combines. If not eliminated, we will match back to BFE during
1926 // TODO: The sext_inreg of extended types ends, although we can could
1927 // handle them in a single BFE.
1928 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
1929 DAG.getValueType(SmallVT));
1932 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
1935 if (ConstantSDNode *Val = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
1937 return constantFoldBFE<int32_t>(DAG,
1938 Val->getSExtValue(),
1943 return constantFoldBFE<uint32_t>(DAG,
1944 Val->getZExtValue(),
1949 APInt Demanded = APInt::getBitsSet(32,
1951 OffsetVal + WidthVal);
1953 if ((OffsetVal + WidthVal) >= 32) {
1954 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
1955 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1956 BitsFrom, ShiftVal);
1959 APInt KnownZero, KnownOne;
1960 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1961 !DCI.isBeforeLegalizeOps());
1962 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1963 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
1964 TLI.SimplifyDemandedBits(BitsFrom, Demanded, KnownZero, KnownOne, TLO)) {
1965 DCI.CommitTargetLoweringOpt(TLO);
1974 //===----------------------------------------------------------------------===//
1976 //===----------------------------------------------------------------------===//
1978 void AMDGPUTargetLowering::getOriginalFunctionArgs(
1981 const SmallVectorImpl<ISD::InputArg> &Ins,
1982 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
1984 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1985 if (Ins[i].ArgVT == Ins[i].VT) {
1986 OrigIns.push_back(Ins[i]);
1991 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
1992 // Vector has been split into scalars.
1993 VT = Ins[i].ArgVT.getVectorElementType();
1994 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
1995 Ins[i].ArgVT.getVectorElementType() !=
1996 Ins[i].VT.getVectorElementType()) {
1997 // Vector elements have been promoted
2000 // Vector has been spilt into smaller vectors.
2004 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2005 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2006 OrigIns.push_back(Arg);
2010 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2011 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2012 return CFP->isExactlyValue(1.0);
2014 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2015 return C->isAllOnesValue();
2020 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2021 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2022 return CFP->getValueAPF().isZero();
2024 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2025 return C->isNullValue();
2030 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2031 const TargetRegisterClass *RC,
2032 unsigned Reg, EVT VT) const {
2033 MachineFunction &MF = DAG.getMachineFunction();
2034 MachineRegisterInfo &MRI = MF.getRegInfo();
2035 unsigned VirtualRegister;
2036 if (!MRI.isLiveIn(Reg)) {
2037 VirtualRegister = MRI.createVirtualRegister(RC);
2038 MRI.addLiveIn(Reg, VirtualRegister);
2040 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2042 return DAG.getRegister(VirtualRegister, VT);
2045 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2047 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2049 default: return nullptr;
2051 NODE_NAME_CASE(CALL);
2052 NODE_NAME_CASE(UMUL);
2053 NODE_NAME_CASE(DIV_INF);
2054 NODE_NAME_CASE(RET_FLAG);
2055 NODE_NAME_CASE(BRANCH_COND);
2058 NODE_NAME_CASE(DWORDADDR)
2059 NODE_NAME_CASE(FRACT)
2060 NODE_NAME_CASE(CLAMP)
2061 NODE_NAME_CASE(FMAX)
2062 NODE_NAME_CASE(SMAX)
2063 NODE_NAME_CASE(UMAX)
2064 NODE_NAME_CASE(FMIN)
2065 NODE_NAME_CASE(SMIN)
2066 NODE_NAME_CASE(UMIN)
2067 NODE_NAME_CASE(URECIP)
2068 NODE_NAME_CASE(DIV_SCALE)
2069 NODE_NAME_CASE(DIV_FMAS)
2070 NODE_NAME_CASE(DIV_FIXUP)
2071 NODE_NAME_CASE(TRIG_PREOP)
2074 NODE_NAME_CASE(DOT4)
2075 NODE_NAME_CASE(BFE_U32)
2076 NODE_NAME_CASE(BFE_I32)
2079 NODE_NAME_CASE(BREV)
2080 NODE_NAME_CASE(MUL_U24)
2081 NODE_NAME_CASE(MUL_I24)
2082 NODE_NAME_CASE(MAD_U24)
2083 NODE_NAME_CASE(MAD_I24)
2084 NODE_NAME_CASE(EXPORT)
2085 NODE_NAME_CASE(CONST_ADDRESS)
2086 NODE_NAME_CASE(REGISTER_LOAD)
2087 NODE_NAME_CASE(REGISTER_STORE)
2088 NODE_NAME_CASE(LOAD_CONSTANT)
2089 NODE_NAME_CASE(LOAD_INPUT)
2090 NODE_NAME_CASE(SAMPLE)
2091 NODE_NAME_CASE(SAMPLEB)
2092 NODE_NAME_CASE(SAMPLED)
2093 NODE_NAME_CASE(SAMPLEL)
2094 NODE_NAME_CASE(CVT_F32_UBYTE0)
2095 NODE_NAME_CASE(CVT_F32_UBYTE1)
2096 NODE_NAME_CASE(CVT_F32_UBYTE2)
2097 NODE_NAME_CASE(CVT_F32_UBYTE3)
2098 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2099 NODE_NAME_CASE(STORE_MSKOR)
2100 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2104 static void computeKnownBitsForMinMax(const SDValue Op0,
2108 const SelectionDAG &DAG,
2110 APInt Op0Zero, Op0One;
2111 APInt Op1Zero, Op1One;
2112 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2113 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2115 KnownZero = Op0Zero & Op1Zero;
2116 KnownOne = Op0One & Op1One;
2119 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2123 const SelectionDAG &DAG,
2124 unsigned Depth) const {
2126 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2130 unsigned Opc = Op.getOpcode();
2135 case ISD::INTRINSIC_WO_CHAIN: {
2136 // FIXME: The intrinsic should just use the node.
2137 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2138 case AMDGPUIntrinsic::AMDGPU_imax:
2139 case AMDGPUIntrinsic::AMDGPU_umax:
2140 case AMDGPUIntrinsic::AMDGPU_imin:
2141 case AMDGPUIntrinsic::AMDGPU_umin:
2142 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2143 KnownZero, KnownOne, DAG, Depth);
2151 case AMDGPUISD::SMAX:
2152 case AMDGPUISD::UMAX:
2153 case AMDGPUISD::SMIN:
2154 case AMDGPUISD::UMIN:
2155 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2156 KnownZero, KnownOne, DAG, Depth);
2159 case AMDGPUISD::BFE_I32:
2160 case AMDGPUISD::BFE_U32: {
2161 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2165 unsigned BitWidth = 32;
2166 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2168 KnownZero = APInt::getAllOnesValue(BitWidth);
2169 KnownOne = APInt::getNullValue(BitWidth);
2173 // FIXME: This could do a lot more. If offset is 0, should be the same as
2174 // sign_extend_inreg implementation, but that involves duplicating it.
2175 if (Opc == AMDGPUISD::BFE_I32)
2176 KnownOne = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2178 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2185 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2187 const SelectionDAG &DAG,
2188 unsigned Depth) const {
2189 switch (Op.getOpcode()) {
2190 case AMDGPUISD::BFE_I32: {
2191 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2195 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2196 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2197 if (!Offset || !Offset->isNullValue())
2200 // TODO: Could probably figure something out with non-0 offsets.
2201 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2202 return std::max(SignBits, Op0SignBits);
2205 case AMDGPUISD::BFE_U32: {
2206 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2207 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;