1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
108 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
110 setOperationAction(ISD::Constant, MVT::i32, Legal);
111 setOperationAction(ISD::Constant, MVT::i64, Legal);
112 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
113 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
115 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
116 setOperationAction(ISD::BRIND, MVT::Other, Expand);
118 // We need to custom lower some of the intrinsics
119 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
121 // Library functions. These default to Expand, but we have instructions
123 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
124 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
125 setOperationAction(ISD::FPOW, MVT::f32, Legal);
126 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
127 setOperationAction(ISD::FABS, MVT::f32, Legal);
128 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
129 setOperationAction(ISD::FRINT, MVT::f32, Legal);
130 setOperationAction(ISD::FROUND, MVT::f32, Legal);
131 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
133 setOperationAction(ISD::FREM, MVT::f32, Custom);
134 setOperationAction(ISD::FREM, MVT::f64, Custom);
136 // Lower floating point store/load to integer store/load to reduce the number
137 // of patterns in tablegen.
138 setOperationAction(ISD::STORE, MVT::f32, Promote);
139 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
141 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
142 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
144 setOperationAction(ISD::STORE, MVT::i64, Promote);
145 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
147 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
148 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
150 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
153 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
154 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
156 setOperationAction(ISD::STORE, MVT::f64, Promote);
157 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
159 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
160 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
162 // Custom lowering of vector stores is required for local address space
164 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
165 // XXX: Native v2i32 local address space stores are possible, but not
166 // currently implemented.
167 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
169 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
170 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
171 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
173 // XXX: This can be change to Custom, once ExpandVectorStores can
174 // handle 64-bit stores.
175 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
177 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
178 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
179 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
180 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
181 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
184 setOperationAction(ISD::LOAD, MVT::f32, Promote);
185 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
187 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
190 setOperationAction(ISD::LOAD, MVT::i64, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
193 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
196 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
199 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
200 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
202 setOperationAction(ISD::LOAD, MVT::f64, Promote);
203 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
205 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
206 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
210 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
211 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
216 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
217 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
219 // There are no 64-bit extloads. These should be done as a 32-bit extload and
220 // an extension to 64-bit.
221 for (MVT VT : MVT::integer_valuetypes()) {
222 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
223 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
224 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
227 for (MVT VT : MVT::integer_vector_valuetypes()) {
228 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
229 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
230 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
231 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
232 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
233 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
234 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
235 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
236 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
237 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
238 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
239 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
242 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
244 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
245 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
246 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
247 setOperationAction(ISD::FRINT, MVT::f64, Custom);
248 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
251 if (!Subtarget->hasBFI()) {
252 // fcopysign can be done in a single instruction with BFI.
253 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
254 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
257 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
259 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
260 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
261 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
262 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
264 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
265 for (MVT VT : ScalarIntVTs) {
266 setOperationAction(ISD::SREM, VT, Expand);
267 setOperationAction(ISD::SDIV, VT, Expand);
269 // GPU does not have divrem function for signed or unsigned.
270 setOperationAction(ISD::SDIVREM, VT, Custom);
271 setOperationAction(ISD::UDIVREM, VT, Custom);
273 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
274 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
275 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
277 setOperationAction(ISD::BSWAP, VT, Expand);
278 setOperationAction(ISD::CTTZ, VT, Expand);
279 setOperationAction(ISD::CTLZ, VT, Expand);
282 if (!Subtarget->hasBCNT(32))
283 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
285 if (!Subtarget->hasBCNT(64))
286 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
288 // The hardware supports 32-bit ROTR, but not ROTL.
289 setOperationAction(ISD::ROTL, MVT::i32, Expand);
290 setOperationAction(ISD::ROTL, MVT::i64, Expand);
291 setOperationAction(ISD::ROTR, MVT::i64, Expand);
293 setOperationAction(ISD::MUL, MVT::i64, Expand);
294 setOperationAction(ISD::MULHU, MVT::i64, Expand);
295 setOperationAction(ISD::MULHS, MVT::i64, Expand);
296 setOperationAction(ISD::UDIV, MVT::i32, Expand);
297 setOperationAction(ISD::UREM, MVT::i32, Expand);
298 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
299 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
300 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
301 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
302 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
304 if (!Subtarget->hasFFBH())
305 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
307 if (!Subtarget->hasFFBL())
308 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
310 static const MVT::SimpleValueType VectorIntTypes[] = {
311 MVT::v2i32, MVT::v4i32
314 for (MVT VT : VectorIntTypes) {
315 // Expand the following operations for the current type by default.
316 setOperationAction(ISD::ADD, VT, Expand);
317 setOperationAction(ISD::AND, VT, Expand);
318 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
319 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
320 setOperationAction(ISD::MUL, VT, Expand);
321 setOperationAction(ISD::OR, VT, Expand);
322 setOperationAction(ISD::SHL, VT, Expand);
323 setOperationAction(ISD::SRA, VT, Expand);
324 setOperationAction(ISD::SRL, VT, Expand);
325 setOperationAction(ISD::ROTL, VT, Expand);
326 setOperationAction(ISD::ROTR, VT, Expand);
327 setOperationAction(ISD::SUB, VT, Expand);
328 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
329 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
330 setOperationAction(ISD::SDIV, VT, Expand);
331 setOperationAction(ISD::UDIV, VT, Expand);
332 setOperationAction(ISD::SREM, VT, Expand);
333 setOperationAction(ISD::UREM, VT, Expand);
334 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
335 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
336 setOperationAction(ISD::SDIVREM, VT, Custom);
337 setOperationAction(ISD::UDIVREM, VT, Custom);
338 setOperationAction(ISD::ADDC, VT, Expand);
339 setOperationAction(ISD::SUBC, VT, Expand);
340 setOperationAction(ISD::ADDE, VT, Expand);
341 setOperationAction(ISD::SUBE, VT, Expand);
342 setOperationAction(ISD::SELECT, VT, Expand);
343 setOperationAction(ISD::VSELECT, VT, Expand);
344 setOperationAction(ISD::SELECT_CC, VT, Expand);
345 setOperationAction(ISD::XOR, VT, Expand);
346 setOperationAction(ISD::BSWAP, VT, Expand);
347 setOperationAction(ISD::CTPOP, VT, Expand);
348 setOperationAction(ISD::CTTZ, VT, Expand);
349 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
350 setOperationAction(ISD::CTLZ, VT, Expand);
351 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
352 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
355 static const MVT::SimpleValueType FloatVectorTypes[] = {
356 MVT::v2f32, MVT::v4f32
359 for (MVT VT : FloatVectorTypes) {
360 setOperationAction(ISD::FABS, VT, Expand);
361 setOperationAction(ISD::FMINNUM, VT, Expand);
362 setOperationAction(ISD::FMAXNUM, VT, Expand);
363 setOperationAction(ISD::FADD, VT, Expand);
364 setOperationAction(ISD::FCEIL, VT, Expand);
365 setOperationAction(ISD::FCOS, VT, Expand);
366 setOperationAction(ISD::FDIV, VT, Expand);
367 setOperationAction(ISD::FEXP2, VT, Expand);
368 setOperationAction(ISD::FLOG2, VT, Expand);
369 setOperationAction(ISD::FREM, VT, Expand);
370 setOperationAction(ISD::FPOW, VT, Expand);
371 setOperationAction(ISD::FFLOOR, VT, Expand);
372 setOperationAction(ISD::FTRUNC, VT, Expand);
373 setOperationAction(ISD::FMUL, VT, Expand);
374 setOperationAction(ISD::FMA, VT, Expand);
375 setOperationAction(ISD::FRINT, VT, Expand);
376 setOperationAction(ISD::FNEARBYINT, VT, Expand);
377 setOperationAction(ISD::FSQRT, VT, Expand);
378 setOperationAction(ISD::FSIN, VT, Expand);
379 setOperationAction(ISD::FSUB, VT, Expand);
380 setOperationAction(ISD::FNEG, VT, Expand);
381 setOperationAction(ISD::SELECT, VT, Expand);
382 setOperationAction(ISD::VSELECT, VT, Expand);
383 setOperationAction(ISD::SELECT_CC, VT, Expand);
384 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
385 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
388 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
389 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
391 setTargetDAGCombine(ISD::MUL);
392 setTargetDAGCombine(ISD::SELECT);
393 setTargetDAGCombine(ISD::SELECT_CC);
394 setTargetDAGCombine(ISD::STORE);
396 setBooleanContents(ZeroOrNegativeOneBooleanContent);
397 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
399 setSchedulingPreference(Sched::RegPressure);
400 setJumpIsExpensive(true);
402 // SI at least has hardware support for floating point exceptions, but no way
403 // of using or handling them is implemented. They are also optional in OpenCL
405 setHasFloatingPointExceptions(false);
407 setSelectIsExpensive(false);
408 PredictableSelectIsExpensive = false;
410 // There are no integer divide instructions, and these expand to a pretty
411 // large sequence of instructions.
412 setIntDivIsCheap(false);
413 setPow2SDivIsCheap(false);
414 setFsqrtIsCheap(true);
416 // FIXME: Need to really handle these.
417 MaxStoresPerMemcpy = 4096;
418 MaxStoresPerMemmove = 4096;
419 MaxStoresPerMemset = 4096;
422 //===----------------------------------------------------------------------===//
423 // Target Information
424 //===----------------------------------------------------------------------===//
426 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
430 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
434 // The backend supports 32 and 64 bit floating point immediates.
435 // FIXME: Why are we reporting vectors of FP immediates as legal?
436 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
437 EVT ScalarVT = VT.getScalarType();
438 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
441 // We don't want to shrink f64 / f32 constants.
442 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
443 EVT ScalarVT = VT.getScalarType();
444 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
447 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
451 unsigned NewSize = NewVT.getStoreSizeInBits();
453 // If we are reducing to a 32-bit load, this is always better.
457 EVT OldVT = N->getValueType(0);
458 unsigned OldSize = OldVT.getStoreSizeInBits();
460 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
461 // extloads, so doing one requires using a buffer_load. In cases where we
462 // still couldn't use a scalar load, using the wider load shouldn't really
465 // If the old size already had to be an extload, there's no harm in continuing
466 // to reduce the width.
467 return (OldSize < 32);
470 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
472 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
475 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
476 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
478 return ((LScalarSize <= CastScalarSize) ||
479 (CastScalarSize >= 32) ||
483 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
484 // profitable with the expansion for 64-bit since it's generally good to
486 // FIXME: These should really have the size as a parameter.
487 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
491 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
495 //===---------------------------------------------------------------------===//
497 //===---------------------------------------------------------------------===//
499 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
500 assert(VT.isFloatingPoint());
501 return VT == MVT::f32 || VT == MVT::f64;
504 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
505 assert(VT.isFloatingPoint());
506 return VT == MVT::f32 || VT == MVT::f64;
509 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
510 // Truncate is just accessing a subregister.
511 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
514 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
515 // Truncate is just accessing a subregister.
516 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
517 (Dest->getPrimitiveSizeInBits() % 32 == 0);
520 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
521 const DataLayout *DL = getDataLayout();
522 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
523 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
525 return SrcSize == 32 && DestSize == 64;
528 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
529 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
530 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
531 // this will enable reducing 64-bit operations the 32-bit, which is always
533 return Src == MVT::i32 && Dest == MVT::i64;
536 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
537 return isZExtFree(Val.getValueType(), VT2);
540 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
541 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
542 // limited number of native 64-bit operations. Shrinking an operation to fit
543 // in a single 32-bit register should always be helpful. As currently used,
544 // this is much less general than the name suggests, and is only used in
545 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
546 // not profitable, and may actually be harmful.
547 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
550 //===---------------------------------------------------------------------===//
551 // TargetLowering Callbacks
552 //===---------------------------------------------------------------------===//
554 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
555 const SmallVectorImpl<ISD::InputArg> &Ins) const {
557 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
560 SDValue AMDGPUTargetLowering::LowerReturn(
562 CallingConv::ID CallConv,
564 const SmallVectorImpl<ISD::OutputArg> &Outs,
565 const SmallVectorImpl<SDValue> &OutVals,
566 SDLoc DL, SelectionDAG &DAG) const {
567 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
570 //===---------------------------------------------------------------------===//
571 // Target specific lowering
572 //===---------------------------------------------------------------------===//
574 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
575 SmallVectorImpl<SDValue> &InVals) const {
576 SDValue Callee = CLI.Callee;
577 SelectionDAG &DAG = CLI.DAG;
579 const Function &Fn = *DAG.getMachineFunction().getFunction();
581 StringRef FuncName("<unknown>");
583 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
584 FuncName = G->getSymbol();
585 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
586 FuncName = G->getGlobal()->getName();
588 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
589 DAG.getContext()->diagnose(NoCalls);
593 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
594 SelectionDAG &DAG) const {
595 switch (Op.getOpcode()) {
597 Op.getNode()->dump();
598 llvm_unreachable("Custom lowering code for this"
599 "instruction is not implemented yet!");
601 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
602 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
603 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
604 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
605 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
606 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
607 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
608 case ISD::FREM: return LowerFREM(Op, DAG);
609 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
610 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
611 case ISD::FRINT: return LowerFRINT(Op, DAG);
612 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
613 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
614 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
615 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
616 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
617 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
622 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
623 SmallVectorImpl<SDValue> &Results,
624 SelectionDAG &DAG) const {
625 switch (N->getOpcode()) {
626 case ISD::SIGN_EXTEND_INREG:
627 // Different parts of legalization seem to interpret which type of
628 // sign_extend_inreg is the one to check for custom lowering. The extended
629 // from type is what really matters, but some places check for custom
630 // lowering of the result type. This results in trying to use
631 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
632 // nothing here and let the illegal result integer be handled normally.
635 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
639 Results.push_back(SDValue(Node, 0));
640 Results.push_back(SDValue(Node, 1));
641 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
643 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
647 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
648 if (Lowered.getNode())
649 Results.push_back(Lowered);
657 // FIXME: This implements accesses to initialized globals in the constant
658 // address space by copying them to private and accessing that. It does not
659 // properly handle illegal types or vectors. The private vector loads are not
660 // scalarized, and the illegal scalars hit an assertion. This technique will not
661 // work well with large initializers, and this should eventually be
662 // removed. Initialized globals should be placed into a data section that the
663 // runtime will load into a buffer before the kernel is executed. Uses of the
664 // global need to be replaced with a pointer loaded from an implicit kernel
665 // argument into this buffer holding the copy of the data, which will remove the
666 // need for any of this.
667 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
668 const GlobalValue *GV,
669 const SDValue &InitPtr,
671 SelectionDAG &DAG) const {
672 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
674 Type *InitTy = Init->getType();
676 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
677 EVT VT = EVT::getEVT(InitTy);
678 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
679 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
680 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
681 TD->getPrefTypeAlignment(InitTy));
684 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
685 EVT VT = EVT::getEVT(CFP->getType());
686 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
687 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
688 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
689 TD->getPrefTypeAlignment(CFP->getType()));
692 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
693 const StructLayout *SL = TD->getStructLayout(ST);
695 EVT PtrVT = InitPtr.getValueType();
696 SmallVector<SDValue, 8> Chains;
698 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
699 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
700 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
702 Constant *Elt = Init->getAggregateElement(I);
703 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
706 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
709 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
710 EVT PtrVT = InitPtr.getValueType();
712 unsigned NumElements;
713 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
714 NumElements = AT->getNumElements();
715 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
716 NumElements = VT->getNumElements();
718 llvm_unreachable("Unexpected type");
720 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
721 SmallVector<SDValue, 8> Chains;
722 for (unsigned i = 0; i < NumElements; ++i) {
723 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
724 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
726 Constant *Elt = Init->getAggregateElement(i);
727 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
730 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
733 if (isa<UndefValue>(Init)) {
734 EVT VT = EVT::getEVT(InitTy);
735 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
736 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
737 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
738 TD->getPrefTypeAlignment(InitTy));
742 llvm_unreachable("Unhandled constant initializer");
745 static bool hasDefinedInitializer(const GlobalValue *GV) {
746 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
747 if (!GVar || !GVar->hasInitializer())
750 if (isa<UndefValue>(GVar->getInitializer()))
756 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
758 SelectionDAG &DAG) const {
760 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
761 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
762 const GlobalValue *GV = G->getGlobal();
764 switch (G->getAddressSpace()) {
765 case AMDGPUAS::LOCAL_ADDRESS: {
766 // XXX: What does the value of G->getOffset() mean?
767 assert(G->getOffset() == 0 &&
768 "Do not know what to do with an non-zero offset");
770 // TODO: We could emit code to handle the initialization somewhere.
771 if (hasDefinedInitializer(GV))
775 if (MFI->LocalMemoryObjects.count(GV) == 0) {
776 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
777 Offset = MFI->LDSSize;
778 MFI->LocalMemoryObjects[GV] = Offset;
779 // XXX: Account for alignment?
780 MFI->LDSSize += Size;
782 Offset = MFI->LocalMemoryObjects[GV];
785 return DAG.getConstant(Offset, getPointerTy(AMDGPUAS::LOCAL_ADDRESS));
787 case AMDGPUAS::CONSTANT_ADDRESS: {
788 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
789 Type *EltType = GV->getType()->getElementType();
790 unsigned Size = TD->getTypeAllocSize(EltType);
791 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
793 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
794 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
796 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
797 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
799 const GlobalVariable *Var = cast<GlobalVariable>(GV);
800 if (!Var->hasInitializer()) {
801 // This has no use, but bugpoint will hit it.
802 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
805 const Constant *Init = Var->getInitializer();
806 SmallVector<SDNode*, 8> WorkList;
808 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
809 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
810 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
812 WorkList.push_back(*I);
814 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
815 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
816 E = WorkList.end(); I != E; ++I) {
817 SmallVector<SDValue, 8> Ops;
818 Ops.push_back(Chain);
819 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
820 Ops.push_back((*I)->getOperand(i));
822 DAG.UpdateNodeOperands(*I, Ops);
824 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
828 const Function &Fn = *DAG.getMachineFunction().getFunction();
829 DiagnosticInfoUnsupported BadInit(Fn,
830 "initializer for address space");
831 DAG.getContext()->diagnose(BadInit);
835 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
836 SelectionDAG &DAG) const {
837 SmallVector<SDValue, 8> Args;
838 SDValue A = Op.getOperand(0);
839 SDValue B = Op.getOperand(1);
841 DAG.ExtractVectorElements(A, Args);
842 DAG.ExtractVectorElements(B, Args);
844 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
847 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
848 SelectionDAG &DAG) const {
850 SmallVector<SDValue, 8> Args;
851 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
852 EVT VT = Op.getValueType();
853 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
854 VT.getVectorNumElements());
856 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
859 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
860 SelectionDAG &DAG) const {
862 MachineFunction &MF = DAG.getMachineFunction();
863 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
864 getTargetMachine().getSubtargetImpl()->getFrameLowering());
866 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
868 unsigned FrameIndex = FIN->getIndex();
869 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
870 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
874 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
875 SelectionDAG &DAG) const {
876 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
878 EVT VT = Op.getValueType();
880 switch (IntrinsicID) {
882 case AMDGPUIntrinsic::AMDGPU_abs:
883 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
884 return LowerIntrinsicIABS(Op, DAG);
885 case AMDGPUIntrinsic::AMDGPU_lrp:
886 return LowerIntrinsicLRP(Op, DAG);
887 case AMDGPUIntrinsic::AMDGPU_fract:
888 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
889 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
891 case AMDGPUIntrinsic::AMDGPU_clamp:
892 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
893 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
894 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
896 case Intrinsic::AMDGPU_div_scale: {
897 // 3rd parameter required to be a constant.
898 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
900 return DAG.getUNDEF(VT);
902 // Translate to the operands expected by the machine instruction. The
903 // first parameter must be the same as the first instruction.
904 SDValue Numerator = Op.getOperand(1);
905 SDValue Denominator = Op.getOperand(2);
907 // Note this order is opposite of the machine instruction's operations,
908 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
909 // intrinsic has the numerator as the first operand to match a normal
910 // division operation.
912 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
914 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
915 Denominator, Numerator);
918 case Intrinsic::AMDGPU_div_fmas:
919 // FIXME: Dropping bool parameter. Work is needed to support the implicit
921 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
922 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
924 case Intrinsic::AMDGPU_div_fixup:
925 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
926 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
928 case Intrinsic::AMDGPU_trig_preop:
929 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
930 Op.getOperand(1), Op.getOperand(2));
932 case Intrinsic::AMDGPU_rcp:
933 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
935 case Intrinsic::AMDGPU_rsq:
936 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
938 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
939 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
941 case Intrinsic::AMDGPU_rsq_clamped:
942 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
943 Type *Type = VT.getTypeForEVT(*DAG.getContext());
944 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
945 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
947 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
948 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
949 DAG.getConstantFP(Max, VT));
950 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
951 DAG.getConstantFP(Min, VT));
953 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
956 case Intrinsic::AMDGPU_ldexp:
957 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
960 case AMDGPUIntrinsic::AMDGPU_imax:
961 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
963 case AMDGPUIntrinsic::AMDGPU_umax:
964 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
966 case AMDGPUIntrinsic::AMDGPU_imin:
967 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
969 case AMDGPUIntrinsic::AMDGPU_umin:
970 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
973 case AMDGPUIntrinsic::AMDGPU_umul24:
974 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
975 Op.getOperand(1), Op.getOperand(2));
977 case AMDGPUIntrinsic::AMDGPU_imul24:
978 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
979 Op.getOperand(1), Op.getOperand(2));
981 case AMDGPUIntrinsic::AMDGPU_umad24:
982 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
983 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
985 case AMDGPUIntrinsic::AMDGPU_imad24:
986 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
987 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
989 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
990 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
992 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
993 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
995 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
996 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
998 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
999 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
1001 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
1002 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
1007 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
1008 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
1013 case AMDGPUIntrinsic::AMDGPU_bfi:
1014 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
1019 case AMDGPUIntrinsic::AMDGPU_bfm:
1020 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
1024 case AMDGPUIntrinsic::AMDGPU_brev:
1025 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
1027 case Intrinsic::AMDGPU_class:
1028 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
1029 Op.getOperand(1), Op.getOperand(2));
1031 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
1032 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
1034 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
1035 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
1036 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
1037 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
1041 ///IABS(a) = SMAX(sub(0, a), a)
1042 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
1043 SelectionDAG &DAG) const {
1045 EVT VT = Op.getValueType();
1046 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1049 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
1052 /// Linear Interpolation
1053 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
1054 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
1055 SelectionDAG &DAG) const {
1057 EVT VT = Op.getValueType();
1058 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
1059 DAG.getConstantFP(1.0f, MVT::f32),
1061 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
1063 return DAG.getNode(ISD::FADD, DL, VT,
1064 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1068 /// \brief Generate Min/Max node
1069 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
1076 DAGCombinerInfo &DCI) const {
1077 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1080 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1083 SelectionDAG &DAG = DCI.DAG;
1084 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1093 case ISD::SETFALSE2:
1102 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1103 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1109 // Ordered. Assume ordered for undefined.
1111 // Only do this after legalization to avoid interfering with other combines
1112 // which might occur.
1113 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1114 !DCI.isCalledByLegalizer())
1117 // We need to permute the operands to get the correct NaN behavior. The
1118 // selected operand is the second one based on the failing compare with NaN,
1119 // so permute it based on the compare type the hardware uses.
1121 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1122 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1127 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1128 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1134 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1135 !DCI.isCalledByLegalizer())
1139 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1140 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1142 case ISD::SETCC_INVALID:
1143 llvm_unreachable("Invalid setcc condcode!");
1148 /// \brief Generate Min/Max node
1149 SDValue AMDGPUTargetLowering::CombineIMinMax(SDLoc DL,
1156 SelectionDAG &DAG) const {
1157 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1160 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1164 unsigned Opc = (LHS == True) ? AMDGPUISD::UMIN : AMDGPUISD::UMAX;
1165 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1169 unsigned Opc = (LHS == True) ? AMDGPUISD::SMIN : AMDGPUISD::SMAX;
1170 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1174 unsigned Opc = (LHS == True) ? AMDGPUISD::SMAX : AMDGPUISD::SMIN;
1175 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1179 unsigned Opc = (LHS == True) ? AMDGPUISD::UMAX : AMDGPUISD::UMIN;
1180 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1187 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1188 SelectionDAG &DAG) const {
1189 LoadSDNode *Load = cast<LoadSDNode>(Op);
1190 EVT MemVT = Load->getMemoryVT();
1191 EVT MemEltVT = MemVT.getVectorElementType();
1193 EVT LoadVT = Op.getValueType();
1194 EVT EltVT = LoadVT.getVectorElementType();
1195 EVT PtrVT = Load->getBasePtr().getValueType();
1197 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1198 SmallVector<SDValue, 8> Loads;
1199 SmallVector<SDValue, 8> Chains;
1202 unsigned MemEltSize = MemEltVT.getStoreSize();
1203 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1205 for (unsigned i = 0; i < NumElts; ++i) {
1206 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1207 DAG.getConstant(i * MemEltSize, PtrVT));
1210 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1211 Load->getChain(), Ptr,
1212 SrcValue.getWithOffset(i * MemEltSize),
1213 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1214 Load->isInvariant(), Load->getAlignment());
1215 Loads.push_back(NewLoad.getValue(0));
1216 Chains.push_back(NewLoad.getValue(1));
1220 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1221 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1224 return DAG.getMergeValues(Ops, SL);
1227 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1228 SelectionDAG &DAG) const {
1229 EVT VT = Op.getValueType();
1231 // If this is a 2 element vector, we really want to scalarize and not create
1232 // weird 1 element vectors.
1233 if (VT.getVectorNumElements() == 2)
1234 return ScalarizeVectorLoad(Op, DAG);
1236 LoadSDNode *Load = cast<LoadSDNode>(Op);
1237 SDValue BasePtr = Load->getBasePtr();
1238 EVT PtrVT = BasePtr.getValueType();
1239 EVT MemVT = Load->getMemoryVT();
1241 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1244 EVT LoMemVT, HiMemVT;
1247 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1248 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1249 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1251 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1252 Load->getChain(), BasePtr,
1254 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1255 Load->isInvariant(), Load->getAlignment());
1257 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1258 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1261 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1262 Load->getChain(), HiPtr,
1263 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1264 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1265 Load->isInvariant(), Load->getAlignment());
1268 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1269 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1270 LoLoad.getValue(1), HiLoad.getValue(1))
1273 return DAG.getMergeValues(Ops, SL);
1276 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1277 SelectionDAG &DAG) const {
1278 StoreSDNode *Store = cast<StoreSDNode>(Op);
1279 EVT MemVT = Store->getMemoryVT();
1280 unsigned MemBits = MemVT.getSizeInBits();
1282 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1283 // truncating store into an i32 store.
1284 // XXX: We could also handle optimize other vector bitwidths.
1285 if (!MemVT.isVector() || MemBits > 32) {
1290 SDValue Value = Store->getValue();
1291 EVT VT = Value.getValueType();
1292 EVT ElemVT = VT.getVectorElementType();
1293 SDValue Ptr = Store->getBasePtr();
1294 EVT MemEltVT = MemVT.getVectorElementType();
1295 unsigned MemEltBits = MemEltVT.getSizeInBits();
1296 unsigned MemNumElements = MemVT.getVectorNumElements();
1297 unsigned PackedSize = MemVT.getStoreSizeInBits();
1298 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1300 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1302 SDValue PackedValue;
1303 for (unsigned i = 0; i < MemNumElements; ++i) {
1304 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1305 DAG.getConstant(i, MVT::i32));
1306 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1307 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1309 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1310 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1315 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1319 if (PackedSize < 32) {
1320 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1321 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1322 Store->getMemOperand()->getPointerInfo(),
1324 Store->isNonTemporal(), Store->isVolatile(),
1325 Store->getAlignment());
1328 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1329 Store->getMemOperand()->getPointerInfo(),
1330 Store->isVolatile(), Store->isNonTemporal(),
1331 Store->getAlignment());
1334 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1335 SelectionDAG &DAG) const {
1336 StoreSDNode *Store = cast<StoreSDNode>(Op);
1337 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1338 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1339 EVT PtrVT = Store->getBasePtr().getValueType();
1340 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1343 SmallVector<SDValue, 8> Chains;
1345 unsigned EltSize = MemEltVT.getStoreSize();
1346 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1348 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1349 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1351 DAG.getConstant(i, MVT::i32));
1353 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), PtrVT);
1354 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1356 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1357 SrcValue.getWithOffset(i * EltSize),
1358 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1359 Store->getAlignment());
1360 Chains.push_back(NewStore);
1363 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1366 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1367 SelectionDAG &DAG) const {
1368 StoreSDNode *Store = cast<StoreSDNode>(Op);
1369 SDValue Val = Store->getValue();
1370 EVT VT = Val.getValueType();
1372 // If this is a 2 element vector, we really want to scalarize and not create
1373 // weird 1 element vectors.
1374 if (VT.getVectorNumElements() == 2)
1375 return ScalarizeVectorStore(Op, DAG);
1377 EVT MemVT = Store->getMemoryVT();
1378 SDValue Chain = Store->getChain();
1379 SDValue BasePtr = Store->getBasePtr();
1383 EVT LoMemVT, HiMemVT;
1386 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1387 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1388 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1390 EVT PtrVT = BasePtr.getValueType();
1391 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1392 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1394 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1396 = DAG.getTruncStore(Chain, SL, Lo,
1400 Store->isNonTemporal(),
1401 Store->isVolatile(),
1402 Store->getAlignment());
1404 = DAG.getTruncStore(Chain, SL, Hi,
1406 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1408 Store->isNonTemporal(),
1409 Store->isVolatile(),
1410 Store->getAlignment());
1412 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1416 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1418 LoadSDNode *Load = cast<LoadSDNode>(Op);
1419 ISD::LoadExtType ExtType = Load->getExtensionType();
1420 EVT VT = Op.getValueType();
1421 EVT MemVT = Load->getMemoryVT();
1423 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1424 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1425 // FIXME: Copied from PPC
1426 // First, load into 32 bits, then truncate to 1 bit.
1428 SDValue Chain = Load->getChain();
1429 SDValue BasePtr = Load->getBasePtr();
1430 MachineMemOperand *MMO = Load->getMemOperand();
1432 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1433 BasePtr, MVT::i8, MMO);
1436 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1440 return DAG.getMergeValues(Ops, DL);
1443 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1444 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1445 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1449 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1450 DAG.getConstant(2, MVT::i32));
1451 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1452 Load->getChain(), Ptr,
1453 DAG.getTargetConstant(0, MVT::i32),
1455 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1457 DAG.getConstant(0x3, MVT::i32));
1458 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1459 DAG.getConstant(3, MVT::i32));
1461 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1463 EVT MemEltVT = MemVT.getScalarType();
1464 if (ExtType == ISD::SEXTLOAD) {
1465 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1468 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1472 return DAG.getMergeValues(Ops, DL);
1476 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1480 return DAG.getMergeValues(Ops, DL);
1483 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1485 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1486 if (Result.getNode()) {
1490 StoreSDNode *Store = cast<StoreSDNode>(Op);
1491 SDValue Chain = Store->getChain();
1492 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1493 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1494 Store->getValue().getValueType().isVector()) {
1495 return ScalarizeVectorStore(Op, DAG);
1498 EVT MemVT = Store->getMemoryVT();
1499 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1500 MemVT.bitsLT(MVT::i32)) {
1502 if (Store->getMemoryVT() == MVT::i8) {
1504 } else if (Store->getMemoryVT() == MVT::i16) {
1507 SDValue BasePtr = Store->getBasePtr();
1508 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1509 DAG.getConstant(2, MVT::i32));
1510 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1511 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1513 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1514 DAG.getConstant(0x3, MVT::i32));
1516 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1517 DAG.getConstant(3, MVT::i32));
1519 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1522 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1524 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1525 MaskedValue, ShiftAmt);
1527 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1529 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1530 DAG.getConstant(0xffffffff, MVT::i32));
1531 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1533 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1534 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1535 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1540 // This is a shortcut for integer division because we have fast i32<->f32
1541 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1542 // float is enough to accurately represent up to a 24-bit integer.
1543 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1545 EVT VT = Op.getValueType();
1546 SDValue LHS = Op.getOperand(0);
1547 SDValue RHS = Op.getOperand(1);
1548 MVT IntVT = MVT::i32;
1549 MVT FltVT = MVT::f32;
1551 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1552 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1554 if (VT.isVector()) {
1555 unsigned NElts = VT.getVectorNumElements();
1556 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1557 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1560 unsigned BitSize = VT.getScalarType().getSizeInBits();
1562 SDValue jq = DAG.getConstant(1, IntVT);
1565 // char|short jq = ia ^ ib;
1566 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1568 // jq = jq >> (bitsize - 2)
1569 jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
1572 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));
1575 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1578 // int ia = (int)LHS;
1580 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1582 // int ib, (int)RHS;
1584 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1586 // float fa = (float)ia;
1587 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1589 // float fb = (float)ib;
1590 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1592 // float fq = native_divide(fa, fb);
1593 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1594 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1597 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1599 // float fqneg = -fq;
1600 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1602 // float fr = mad(fqneg, fb, fa);
1603 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1604 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1606 // int iq = (int)fq;
1607 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1610 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1613 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1615 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), VT);
1617 // int cv = fr >= fb;
1618 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1620 // jq = (cv ? jq : 0);
1621 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
1623 // dst = trunc/extend to legal type
1624 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1627 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1629 // Rem needs compensation, it's easier to recompute it
1630 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1631 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1637 return DAG.getMergeValues(Res, DL);
1640 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1642 SmallVectorImpl<SDValue> &Results) const {
1643 assert(Op.getValueType() == MVT::i64);
1646 EVT VT = Op.getValueType();
1647 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1649 SDValue one = DAG.getConstant(1, HalfVT);
1650 SDValue zero = DAG.getConstant(0, HalfVT);
1653 SDValue LHS = Op.getOperand(0);
1654 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1655 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1657 SDValue RHS = Op.getOperand(1);
1658 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1659 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1661 // Get Speculative values
1662 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1663 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1665 SDValue REM_Hi = zero;
1666 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1668 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1669 SDValue DIV_Lo = zero;
1671 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1673 for (unsigned i = 0; i < halfBitWidth; ++i) {
1674 SDValue POS = DAG.getConstant(halfBitWidth - i - 1, HalfVT);
1675 // Get Value of high bit
1677 if (halfBitWidth == 32 && Subtarget->hasBFE()) {
1678 HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
1680 HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1681 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1684 SDValue Carry = DAG.getNode(ISD::SRL, DL, HalfVT, REM_Lo,
1685 DAG.getConstant(halfBitWidth - 1, HalfVT));
1686 REM_Hi = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Hi, one);
1687 REM_Hi = DAG.getNode(ISD::OR, DL, HalfVT, REM_Hi, Carry);
1689 REM_Lo = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Lo, one);
1690 REM_Lo = DAG.getNode(ISD::OR, DL, HalfVT, REM_Lo, HBit);
1693 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
1695 SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
1696 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1698 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1702 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1704 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1705 REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
1706 REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
1709 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
1710 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
1711 Results.push_back(DIV);
1712 Results.push_back(REM);
1715 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1716 SelectionDAG &DAG) const {
1718 EVT VT = Op.getValueType();
1720 if (VT == MVT::i64) {
1721 SmallVector<SDValue, 2> Results;
1722 LowerUDIVREM64(Op, DAG, Results);
1723 return DAG.getMergeValues(Results, DL);
1726 SDValue Num = Op.getOperand(0);
1727 SDValue Den = Op.getOperand(1);
1729 if (VT == MVT::i32) {
1730 if (DAG.MaskedValueIsZero(Op.getOperand(0), APInt(32, 0xff << 24)) &&
1731 DAG.MaskedValueIsZero(Op.getOperand(1), APInt(32, 0xff << 24))) {
1732 // TODO: We technically could do this for i64, but shouldn't that just be
1733 // handled by something generally reducing 64-bit division on 32-bit
1734 // values to 32-bit?
1735 return LowerDIVREM24(Op, DAG, false);
1739 // RCP = URECIP(Den) = 2^32 / Den + e
1740 // e is rounding error.
1741 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1743 // RCP_LO = mul(RCP, Den) */
1744 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1746 // RCP_HI = mulhu (RCP, Den) */
1747 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1749 // NEG_RCP_LO = -RCP_LO
1750 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1753 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1754 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1757 // Calculate the rounding error from the URECIP instruction
1758 // E = mulhu(ABS_RCP_LO, RCP)
1759 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1761 // RCP_A_E = RCP + E
1762 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1764 // RCP_S_E = RCP - E
1765 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1767 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1768 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1771 // Quotient = mulhu(Tmp0, Num)
1772 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1774 // Num_S_Remainder = Quotient * Den
1775 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1777 // Remainder = Num - Num_S_Remainder
1778 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1780 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1781 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1782 DAG.getConstant(-1, VT),
1783 DAG.getConstant(0, VT),
1785 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1786 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1788 DAG.getConstant(-1, VT),
1789 DAG.getConstant(0, VT),
1791 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1792 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1795 // Calculate Division result:
1797 // Quotient_A_One = Quotient + 1
1798 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1799 DAG.getConstant(1, VT));
1801 // Quotient_S_One = Quotient - 1
1802 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1803 DAG.getConstant(1, VT));
1805 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1806 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1807 Quotient, Quotient_A_One, ISD::SETEQ);
1809 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1810 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1811 Quotient_S_One, Div, ISD::SETEQ);
1813 // Calculate Rem result:
1815 // Remainder_S_Den = Remainder - Den
1816 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1818 // Remainder_A_Den = Remainder + Den
1819 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1821 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1822 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1823 Remainder, Remainder_S_Den, ISD::SETEQ);
1825 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1826 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1827 Remainder_A_Den, Rem, ISD::SETEQ);
1832 return DAG.getMergeValues(Ops, DL);
1835 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1836 SelectionDAG &DAG) const {
1838 EVT VT = Op.getValueType();
1840 SDValue LHS = Op.getOperand(0);
1841 SDValue RHS = Op.getOperand(1);
1843 if (VT == MVT::i32) {
1844 if (DAG.ComputeNumSignBits(Op.getOperand(0)) > 8 &&
1845 DAG.ComputeNumSignBits(Op.getOperand(1)) > 8) {
1846 // TODO: We technically could do this for i64, but shouldn't that just be
1847 // handled by something generally reducing 64-bit division on 32-bit
1848 // values to 32-bit?
1849 return LowerDIVREM24(Op, DAG, true);
1853 SDValue Zero = DAG.getConstant(0, VT);
1854 SDValue NegOne = DAG.getConstant(-1, VT);
1856 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1857 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1858 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1859 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1861 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1862 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1864 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1865 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1867 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1868 SDValue Rem = Div.getValue(1);
1870 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1871 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1873 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1874 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1880 return DAG.getMergeValues(Res, DL);
1883 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1884 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1886 EVT VT = Op.getValueType();
1887 SDValue X = Op.getOperand(0);
1888 SDValue Y = Op.getOperand(1);
1890 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1891 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1892 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1894 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1897 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1899 SDValue Src = Op.getOperand(0);
1901 // result = trunc(src)
1902 // if (src > 0.0 && src != result)
1905 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1907 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1908 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1910 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1912 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1913 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1914 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1916 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1917 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1920 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1922 SDValue Src = Op.getOperand(0);
1924 assert(Op.getValueType() == MVT::f64);
1926 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1927 const SDValue One = DAG.getConstant(1, MVT::i32);
1929 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1931 // Extract the upper half, since this is where we will find the sign and
1933 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1935 const unsigned FractBits = 52;
1936 const unsigned ExpBits = 11;
1938 // Extract the exponent.
1939 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1941 DAG.getConstant(FractBits - 32, MVT::i32),
1942 DAG.getConstant(ExpBits, MVT::i32));
1943 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1944 DAG.getConstant(1023, MVT::i32));
1946 // Extract the sign bit.
1947 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1948 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1950 // Extend back to to 64-bits.
1951 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1953 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1955 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1956 const SDValue FractMask
1957 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1959 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1960 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1961 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1963 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1965 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1967 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1968 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1970 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1971 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1973 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1976 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1978 SDValue Src = Op.getOperand(0);
1980 assert(Op.getValueType() == MVT::f64);
1982 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1983 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1984 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1986 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1987 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1989 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1991 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1992 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
1994 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1995 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1997 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2000 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2001 // FNEARBYINT and FRINT are the same, except in their handling of FP
2002 // exceptions. Those aren't really meaningful for us, and OpenCL only has
2003 // rint, so just treat them as equivalent.
2004 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2007 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2009 SDValue Src = Op.getOperand(0);
2011 // result = trunc(src);
2012 // if (src < 0.0 && src != result)
2015 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2017 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
2018 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
2020 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
2022 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2023 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2024 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2026 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2027 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2030 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2031 bool Signed) const {
2033 SDValue Src = Op.getOperand(0);
2035 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2037 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2038 DAG.getConstant(0, MVT::i32));
2039 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2040 DAG.getConstant(1, MVT::i32));
2042 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2045 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2047 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2048 DAG.getConstant(32, MVT::i32));
2050 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2053 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2054 SelectionDAG &DAG) const {
2055 SDValue S0 = Op.getOperand(0);
2056 if (S0.getValueType() != MVT::i64)
2059 EVT DestVT = Op.getValueType();
2060 if (DestVT == MVT::f64)
2061 return LowerINT_TO_FP64(Op, DAG, false);
2063 assert(DestVT == MVT::f32);
2067 // f32 uint_to_fp i64
2068 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2069 DAG.getConstant(0, MVT::i32));
2070 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
2071 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2072 DAG.getConstant(1, MVT::i32));
2073 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
2074 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
2075 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
2076 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
2079 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2080 SelectionDAG &DAG) const {
2081 SDValue Src = Op.getOperand(0);
2082 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
2083 return LowerINT_TO_FP64(Op, DAG, true);
2088 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2089 bool Signed) const {
2092 SDValue Src = Op.getOperand(0);
2094 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2097 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), MVT::f64);
2099 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), MVT::f64);
2101 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2103 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2106 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2108 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2109 MVT::i32, FloorMul);
2110 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2112 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
2114 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2117 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2118 SelectionDAG &DAG) const {
2119 SDValue Src = Op.getOperand(0);
2121 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2122 return LowerFP64_TO_INT(Op, DAG, true);
2127 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2128 SelectionDAG &DAG) const {
2129 SDValue Src = Op.getOperand(0);
2131 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2132 return LowerFP64_TO_INT(Op, DAG, false);
2137 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2138 SelectionDAG &DAG) const {
2139 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2140 MVT VT = Op.getSimpleValueType();
2141 MVT ScalarVT = VT.getScalarType();
2146 SDValue Src = Op.getOperand(0);
2149 // TODO: Don't scalarize on Evergreen?
2150 unsigned NElts = VT.getVectorNumElements();
2151 SmallVector<SDValue, 8> Args;
2152 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2154 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2155 for (unsigned I = 0; I < NElts; ++I)
2156 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2158 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2161 //===----------------------------------------------------------------------===//
2162 // Custom DAG optimizations
2163 //===----------------------------------------------------------------------===//
2165 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2166 APInt KnownZero, KnownOne;
2167 EVT VT = Op.getValueType();
2168 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2170 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2173 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2174 EVT VT = Op.getValueType();
2176 // In order for this to be a signed 24-bit value, bit 23, must
2178 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2179 // as unsigned 24-bit values.
2180 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2183 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2185 SelectionDAG &DAG = DCI.DAG;
2186 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2187 EVT VT = Op.getValueType();
2189 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2190 APInt KnownZero, KnownOne;
2191 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2192 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2193 DCI.CommitTargetLoweringOpt(TLO);
2196 template <typename IntTy>
2197 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2198 uint32_t Offset, uint32_t Width) {
2199 if (Width + Offset < 32) {
2200 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2201 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2202 return DAG.getConstant(Result, MVT::i32);
2205 return DAG.getConstant(Src0 >> Offset, MVT::i32);
2208 static bool usesAllNormalStores(SDNode *LoadVal) {
2209 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2210 if (!ISD::isNormalStore(*I))
2217 // If we have a copy of an illegal type, replace it with a load / store of an
2218 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2219 // instructions emitted when handling extloads and truncstores. Ideally we could
2220 // recognize the pack / unpack pattern to eliminate it.
2221 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2222 DAGCombinerInfo &DCI) const {
2223 if (!DCI.isBeforeLegalize())
2226 StoreSDNode *SN = cast<StoreSDNode>(N);
2227 SDValue Value = SN->getValue();
2228 EVT VT = Value.getValueType();
2230 if (isTypeLegal(VT) || SN->isVolatile() ||
2231 !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2234 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2235 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2238 EVT MemVT = LoadVal->getMemoryVT();
2241 SelectionDAG &DAG = DCI.DAG;
2242 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2244 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2246 LoadVal->getChain(),
2247 LoadVal->getBasePtr(),
2248 LoadVal->getOffset(),
2250 LoadVal->getMemOperand());
2252 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2253 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2255 return DAG.getStore(SN->getChain(), SL, NewLoad,
2256 SN->getBasePtr(), SN->getMemOperand());
2259 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2260 DAGCombinerInfo &DCI) const {
2261 EVT VT = N->getValueType(0);
2263 if (VT.isVector() || VT.getSizeInBits() > 32)
2266 SelectionDAG &DAG = DCI.DAG;
2269 SDValue N0 = N->getOperand(0);
2270 SDValue N1 = N->getOperand(1);
2273 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2274 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2275 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2276 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2277 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2278 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2279 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2280 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2285 // We need to use sext even for MUL_U24, because MUL_U24 is used
2286 // for signed multiply of 8 and 16-bit types.
2287 return DAG.getSExtOrTrunc(Mul, DL, VT);
2290 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2291 DAGCombinerInfo &DCI) const {
2292 SelectionDAG &DAG = DCI.DAG;
2295 switch(N->getOpcode()) {
2298 return performMulCombine(N, DCI);
2299 case AMDGPUISD::MUL_I24:
2300 case AMDGPUISD::MUL_U24: {
2301 SDValue N0 = N->getOperand(0);
2302 SDValue N1 = N->getOperand(1);
2303 simplifyI24(N0, DCI);
2304 simplifyI24(N1, DCI);
2308 SDValue Cond = N->getOperand(0);
2309 if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) {
2311 EVT VT = N->getValueType(0);
2312 SDValue LHS = Cond.getOperand(0);
2313 SDValue RHS = Cond.getOperand(1);
2314 SDValue CC = Cond.getOperand(2);
2316 SDValue True = N->getOperand(1);
2317 SDValue False = N->getOperand(2);
2320 return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
2322 // TODO: Implement min / max Evergreen instructions.
2323 if (VT == MVT::i32 &&
2324 Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
2325 return CombineIMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
2331 case AMDGPUISD::BFE_I32:
2332 case AMDGPUISD::BFE_U32: {
2333 assert(!N->getValueType(0).isVector() &&
2334 "Vector handling of BFE not implemented");
2335 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2339 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2341 return DAG.getConstant(0, MVT::i32);
2343 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2347 SDValue BitsFrom = N->getOperand(0);
2348 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2350 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2352 if (OffsetVal == 0) {
2353 // This is already sign / zero extended, so try to fold away extra BFEs.
2354 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2356 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2357 if (OpSignBits >= SignBits)
2360 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2362 // This is a sign_extend_inreg. Replace it to take advantage of existing
2363 // DAG Combines. If not eliminated, we will match back to BFE during
2366 // TODO: The sext_inreg of extended types ends, although we can could
2367 // handle them in a single BFE.
2368 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2369 DAG.getValueType(SmallVT));
2372 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2375 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2377 return constantFoldBFE<int32_t>(DAG,
2378 CVal->getSExtValue(),
2383 return constantFoldBFE<uint32_t>(DAG,
2384 CVal->getZExtValue(),
2389 if ((OffsetVal + WidthVal) >= 32) {
2390 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
2391 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2392 BitsFrom, ShiftVal);
2395 if (BitsFrom.hasOneUse()) {
2396 APInt Demanded = APInt::getBitsSet(32,
2398 OffsetVal + WidthVal);
2400 APInt KnownZero, KnownOne;
2401 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2402 !DCI.isBeforeLegalizeOps());
2403 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2404 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2405 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2406 KnownZero, KnownOne, TLO)) {
2407 DCI.CommitTargetLoweringOpt(TLO);
2415 return performStoreCombine(N, DCI);
2420 //===----------------------------------------------------------------------===//
2422 //===----------------------------------------------------------------------===//
2424 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2427 const SmallVectorImpl<ISD::InputArg> &Ins,
2428 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2430 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2431 if (Ins[i].ArgVT == Ins[i].VT) {
2432 OrigIns.push_back(Ins[i]);
2437 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2438 // Vector has been split into scalars.
2439 VT = Ins[i].ArgVT.getVectorElementType();
2440 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2441 Ins[i].ArgVT.getVectorElementType() !=
2442 Ins[i].VT.getVectorElementType()) {
2443 // Vector elements have been promoted
2446 // Vector has been spilt into smaller vectors.
2450 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2451 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2452 OrigIns.push_back(Arg);
2456 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2457 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2458 return CFP->isExactlyValue(1.0);
2460 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2461 return C->isAllOnesValue();
2466 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2467 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2468 return CFP->getValueAPF().isZero();
2470 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2471 return C->isNullValue();
2476 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2477 const TargetRegisterClass *RC,
2478 unsigned Reg, EVT VT) const {
2479 MachineFunction &MF = DAG.getMachineFunction();
2480 MachineRegisterInfo &MRI = MF.getRegInfo();
2481 unsigned VirtualRegister;
2482 if (!MRI.isLiveIn(Reg)) {
2483 VirtualRegister = MRI.createVirtualRegister(RC);
2484 MRI.addLiveIn(Reg, VirtualRegister);
2486 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2488 return DAG.getRegister(VirtualRegister, VT);
2491 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2493 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2495 default: return nullptr;
2497 NODE_NAME_CASE(CALL);
2498 NODE_NAME_CASE(UMUL);
2499 NODE_NAME_CASE(RET_FLAG);
2500 NODE_NAME_CASE(BRANCH_COND);
2503 NODE_NAME_CASE(DWORDADDR)
2504 NODE_NAME_CASE(FRACT)
2505 NODE_NAME_CASE(CLAMP)
2507 NODE_NAME_CASE(FMAX_LEGACY)
2508 NODE_NAME_CASE(SMAX)
2509 NODE_NAME_CASE(UMAX)
2510 NODE_NAME_CASE(FMIN_LEGACY)
2511 NODE_NAME_CASE(SMIN)
2512 NODE_NAME_CASE(UMIN)
2513 NODE_NAME_CASE(FMAX3)
2514 NODE_NAME_CASE(SMAX3)
2515 NODE_NAME_CASE(UMAX3)
2516 NODE_NAME_CASE(FMIN3)
2517 NODE_NAME_CASE(SMIN3)
2518 NODE_NAME_CASE(UMIN3)
2519 NODE_NAME_CASE(URECIP)
2520 NODE_NAME_CASE(DIV_SCALE)
2521 NODE_NAME_CASE(DIV_FMAS)
2522 NODE_NAME_CASE(DIV_FIXUP)
2523 NODE_NAME_CASE(TRIG_PREOP)
2526 NODE_NAME_CASE(RSQ_LEGACY)
2527 NODE_NAME_CASE(RSQ_CLAMPED)
2528 NODE_NAME_CASE(LDEXP)
2529 NODE_NAME_CASE(FP_CLASS)
2530 NODE_NAME_CASE(DOT4)
2531 NODE_NAME_CASE(BFE_U32)
2532 NODE_NAME_CASE(BFE_I32)
2535 NODE_NAME_CASE(BREV)
2536 NODE_NAME_CASE(MUL_U24)
2537 NODE_NAME_CASE(MUL_I24)
2538 NODE_NAME_CASE(MAD_U24)
2539 NODE_NAME_CASE(MAD_I24)
2540 NODE_NAME_CASE(EXPORT)
2541 NODE_NAME_CASE(CONST_ADDRESS)
2542 NODE_NAME_CASE(REGISTER_LOAD)
2543 NODE_NAME_CASE(REGISTER_STORE)
2544 NODE_NAME_CASE(LOAD_CONSTANT)
2545 NODE_NAME_CASE(LOAD_INPUT)
2546 NODE_NAME_CASE(SAMPLE)
2547 NODE_NAME_CASE(SAMPLEB)
2548 NODE_NAME_CASE(SAMPLED)
2549 NODE_NAME_CASE(SAMPLEL)
2550 NODE_NAME_CASE(CVT_F32_UBYTE0)
2551 NODE_NAME_CASE(CVT_F32_UBYTE1)
2552 NODE_NAME_CASE(CVT_F32_UBYTE2)
2553 NODE_NAME_CASE(CVT_F32_UBYTE3)
2554 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2555 NODE_NAME_CASE(CONST_DATA_PTR)
2556 NODE_NAME_CASE(STORE_MSKOR)
2557 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2561 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2562 DAGCombinerInfo &DCI,
2563 unsigned &RefinementSteps,
2564 bool &UseOneConstNR) const {
2565 SelectionDAG &DAG = DCI.DAG;
2566 EVT VT = Operand.getValueType();
2568 if (VT == MVT::f32) {
2569 RefinementSteps = 0;
2570 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2573 // TODO: There is also f64 rsq instruction, but the documentation is less
2574 // clear on its precision.
2579 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2580 DAGCombinerInfo &DCI,
2581 unsigned &RefinementSteps) const {
2582 SelectionDAG &DAG = DCI.DAG;
2583 EVT VT = Operand.getValueType();
2585 if (VT == MVT::f32) {
2586 // Reciprocal, < 1 ulp error.
2588 // This reciprocal approximation converges to < 0.5 ulp error with one
2589 // newton rhapson performed with two fused multiple adds (FMAs).
2591 RefinementSteps = 0;
2592 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
2595 // TODO: There is also f64 rcp instruction, but the documentation is less
2596 // clear on its precision.
2601 static void computeKnownBitsForMinMax(const SDValue Op0,
2605 const SelectionDAG &DAG,
2607 APInt Op0Zero, Op0One;
2608 APInt Op1Zero, Op1One;
2609 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2610 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2612 KnownZero = Op0Zero & Op1Zero;
2613 KnownOne = Op0One & Op1One;
2616 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2620 const SelectionDAG &DAG,
2621 unsigned Depth) const {
2623 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2627 unsigned Opc = Op.getOpcode();
2632 case ISD::INTRINSIC_WO_CHAIN: {
2633 // FIXME: The intrinsic should just use the node.
2634 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2635 case AMDGPUIntrinsic::AMDGPU_imax:
2636 case AMDGPUIntrinsic::AMDGPU_umax:
2637 case AMDGPUIntrinsic::AMDGPU_imin:
2638 case AMDGPUIntrinsic::AMDGPU_umin:
2639 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2640 KnownZero, KnownOne, DAG, Depth);
2648 case AMDGPUISD::SMAX:
2649 case AMDGPUISD::UMAX:
2650 case AMDGPUISD::SMIN:
2651 case AMDGPUISD::UMIN:
2652 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2653 KnownZero, KnownOne, DAG, Depth);
2656 case AMDGPUISD::BFE_I32:
2657 case AMDGPUISD::BFE_U32: {
2658 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2662 unsigned BitWidth = 32;
2663 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2665 if (Opc == AMDGPUISD::BFE_U32)
2666 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2673 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2675 const SelectionDAG &DAG,
2676 unsigned Depth) const {
2677 switch (Op.getOpcode()) {
2678 case AMDGPUISD::BFE_I32: {
2679 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2683 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2684 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2685 if (!Offset || !Offset->isNullValue())
2688 // TODO: Could probably figure something out with non-0 offsets.
2689 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2690 return std::max(SignBits, Op0SignBits);
2693 case AMDGPUISD::BFE_U32: {
2694 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2695 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;