1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
106 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
108 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
110 setOperationAction(ISD::Constant, MVT::i32, Legal);
111 setOperationAction(ISD::Constant, MVT::i64, Legal);
112 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
113 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
115 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
116 setOperationAction(ISD::BRIND, MVT::Other, Expand);
118 // We need to custom lower some of the intrinsics
119 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
121 // Library functions. These default to Expand, but we have instructions
123 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
124 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
125 setOperationAction(ISD::FPOW, MVT::f32, Legal);
126 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
127 setOperationAction(ISD::FABS, MVT::f32, Legal);
128 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
129 setOperationAction(ISD::FRINT, MVT::f32, Legal);
130 setOperationAction(ISD::FROUND, MVT::f32, Legal);
131 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
133 setOperationAction(ISD::FREM, MVT::f32, Custom);
134 setOperationAction(ISD::FREM, MVT::f64, Custom);
136 // Lower floating point store/load to integer store/load to reduce the number
137 // of patterns in tablegen.
138 setOperationAction(ISD::STORE, MVT::f32, Promote);
139 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
141 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
142 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
144 setOperationAction(ISD::STORE, MVT::i64, Promote);
145 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
147 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
148 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
150 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
153 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
154 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
156 setOperationAction(ISD::STORE, MVT::f64, Promote);
157 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
159 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
160 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
162 // Custom lowering of vector stores is required for local address space
164 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
165 // XXX: Native v2i32 local address space stores are possible, but not
166 // currently implemented.
167 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
169 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
170 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
171 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
173 // XXX: This can be change to Custom, once ExpandVectorStores can
174 // handle 64-bit stores.
175 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
177 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
178 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
179 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
180 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
181 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
184 setOperationAction(ISD::LOAD, MVT::f32, Promote);
185 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
187 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
190 setOperationAction(ISD::LOAD, MVT::i64, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
193 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
196 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
199 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
200 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
202 setOperationAction(ISD::LOAD, MVT::f64, Promote);
203 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
205 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
206 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
210 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
211 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
216 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
217 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
219 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
220 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
221 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
222 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
223 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
224 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
225 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
226 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
227 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
228 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
229 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
230 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
232 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
234 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
235 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
236 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
237 setOperationAction(ISD::FRINT, MVT::f64, Custom);
238 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
241 if (!Subtarget->hasBFI()) {
242 // fcopysign can be done in a single instruction with BFI.
243 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
244 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
247 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
249 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
250 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
251 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
253 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
254 for (MVT VT : ScalarIntVTs) {
255 setOperationAction(ISD::SREM, VT, Expand);
256 setOperationAction(ISD::SDIV, VT, Expand);
258 // GPU does not have divrem function for signed or unsigned.
259 setOperationAction(ISD::SDIVREM, VT, Custom);
260 setOperationAction(ISD::UDIVREM, VT, Custom);
262 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
263 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
264 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
266 setOperationAction(ISD::BSWAP, VT, Expand);
267 setOperationAction(ISD::CTTZ, VT, Expand);
268 setOperationAction(ISD::CTLZ, VT, Expand);
271 if (!Subtarget->hasBCNT(32))
272 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
274 if (!Subtarget->hasBCNT(64))
275 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
277 // The hardware supports 32-bit ROTR, but not ROTL.
278 setOperationAction(ISD::ROTL, MVT::i32, Expand);
279 setOperationAction(ISD::ROTL, MVT::i64, Expand);
280 setOperationAction(ISD::ROTR, MVT::i64, Expand);
282 setOperationAction(ISD::MUL, MVT::i64, Expand);
283 setOperationAction(ISD::MULHU, MVT::i64, Expand);
284 setOperationAction(ISD::MULHS, MVT::i64, Expand);
285 setOperationAction(ISD::UDIV, MVT::i32, Expand);
286 setOperationAction(ISD::UREM, MVT::i32, Expand);
287 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
288 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
290 if (!Subtarget->hasFFBH())
291 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
293 if (!Subtarget->hasFFBL())
294 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
296 static const MVT::SimpleValueType VectorIntTypes[] = {
297 MVT::v2i32, MVT::v4i32
300 for (MVT VT : VectorIntTypes) {
301 // Expand the following operations for the current type by default.
302 setOperationAction(ISD::ADD, VT, Expand);
303 setOperationAction(ISD::AND, VT, Expand);
304 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
305 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
306 setOperationAction(ISD::MUL, VT, Expand);
307 setOperationAction(ISD::OR, VT, Expand);
308 setOperationAction(ISD::SHL, VT, Expand);
309 setOperationAction(ISD::SRA, VT, Expand);
310 setOperationAction(ISD::SRL, VT, Expand);
311 setOperationAction(ISD::ROTL, VT, Expand);
312 setOperationAction(ISD::ROTR, VT, Expand);
313 setOperationAction(ISD::SUB, VT, Expand);
314 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
315 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
316 setOperationAction(ISD::SDIV, VT, Expand);
317 setOperationAction(ISD::UDIV, VT, Expand);
318 setOperationAction(ISD::SREM, VT, Expand);
319 setOperationAction(ISD::UREM, VT, Expand);
320 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
321 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
322 setOperationAction(ISD::SDIVREM, VT, Custom);
323 setOperationAction(ISD::UDIVREM, VT, Custom);
324 setOperationAction(ISD::ADDC, VT, Expand);
325 setOperationAction(ISD::SUBC, VT, Expand);
326 setOperationAction(ISD::ADDE, VT, Expand);
327 setOperationAction(ISD::SUBE, VT, Expand);
328 setOperationAction(ISD::SELECT, VT, Expand);
329 setOperationAction(ISD::VSELECT, VT, Expand);
330 setOperationAction(ISD::SELECT_CC, VT, Expand);
331 setOperationAction(ISD::XOR, VT, Expand);
332 setOperationAction(ISD::BSWAP, VT, Expand);
333 setOperationAction(ISD::CTPOP, VT, Expand);
334 setOperationAction(ISD::CTTZ, VT, Expand);
335 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
336 setOperationAction(ISD::CTLZ, VT, Expand);
337 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
338 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
341 static const MVT::SimpleValueType FloatVectorTypes[] = {
342 MVT::v2f32, MVT::v4f32
345 for (MVT VT : FloatVectorTypes) {
346 setOperationAction(ISD::FABS, VT, Expand);
347 setOperationAction(ISD::FADD, VT, Expand);
348 setOperationAction(ISD::FCEIL, VT, Expand);
349 setOperationAction(ISD::FCOS, VT, Expand);
350 setOperationAction(ISD::FDIV, VT, Expand);
351 setOperationAction(ISD::FEXP2, VT, Expand);
352 setOperationAction(ISD::FLOG2, VT, Expand);
353 setOperationAction(ISD::FREM, VT, Expand);
354 setOperationAction(ISD::FPOW, VT, Expand);
355 setOperationAction(ISD::FFLOOR, VT, Expand);
356 setOperationAction(ISD::FTRUNC, VT, Expand);
357 setOperationAction(ISD::FMUL, VT, Expand);
358 setOperationAction(ISD::FMA, VT, Expand);
359 setOperationAction(ISD::FRINT, VT, Expand);
360 setOperationAction(ISD::FNEARBYINT, VT, Expand);
361 setOperationAction(ISD::FSQRT, VT, Expand);
362 setOperationAction(ISD::FSIN, VT, Expand);
363 setOperationAction(ISD::FSUB, VT, Expand);
364 setOperationAction(ISD::FNEG, VT, Expand);
365 setOperationAction(ISD::SELECT, VT, Expand);
366 setOperationAction(ISD::VSELECT, VT, Expand);
367 setOperationAction(ISD::SELECT_CC, VT, Expand);
368 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
369 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
372 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
373 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
375 setTargetDAGCombine(ISD::MUL);
376 setTargetDAGCombine(ISD::SELECT_CC);
377 setTargetDAGCombine(ISD::STORE);
379 setSchedulingPreference(Sched::RegPressure);
380 setJumpIsExpensive(true);
382 // SI at least has hardware support for floating point exceptions, but no way
383 // of using or handling them is implemented. They are also optional in OpenCL
385 setHasFloatingPointExceptions(false);
387 setSelectIsExpensive(false);
388 PredictableSelectIsExpensive = false;
390 // There are no integer divide instructions, and these expand to a pretty
391 // large sequence of instructions.
392 setIntDivIsCheap(false);
393 setPow2SDivIsCheap(false);
395 // FIXME: Need to really handle these.
396 MaxStoresPerMemcpy = 4096;
397 MaxStoresPerMemmove = 4096;
398 MaxStoresPerMemset = 4096;
401 //===----------------------------------------------------------------------===//
402 // Target Information
403 //===----------------------------------------------------------------------===//
405 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
409 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
413 // The backend supports 32 and 64 bit floating point immediates.
414 // FIXME: Why are we reporting vectors of FP immediates as legal?
415 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
416 EVT ScalarVT = VT.getScalarType();
417 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
420 // We don't want to shrink f64 / f32 constants.
421 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
422 EVT ScalarVT = VT.getScalarType();
423 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
426 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
428 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
431 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
432 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
434 return ((LScalarSize <= CastScalarSize) ||
435 (CastScalarSize >= 32) ||
439 //===---------------------------------------------------------------------===//
441 //===---------------------------------------------------------------------===//
443 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
444 assert(VT.isFloatingPoint());
445 return VT == MVT::f32 || VT == MVT::f64;
448 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
449 assert(VT.isFloatingPoint());
450 return VT == MVT::f32 || VT == MVT::f64;
453 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
454 // Truncate is just accessing a subregister.
455 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
458 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
459 // Truncate is just accessing a subregister.
460 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
461 (Dest->getPrimitiveSizeInBits() % 32 == 0);
464 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
465 const DataLayout *DL = getDataLayout();
466 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
467 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
469 return SrcSize == 32 && DestSize == 64;
472 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
473 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
474 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
475 // this will enable reducing 64-bit operations the 32-bit, which is always
477 return Src == MVT::i32 && Dest == MVT::i64;
480 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
481 return isZExtFree(Val.getValueType(), VT2);
484 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
485 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
486 // limited number of native 64-bit operations. Shrinking an operation to fit
487 // in a single 32-bit register should always be helpful. As currently used,
488 // this is much less general than the name suggests, and is only used in
489 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
490 // not profitable, and may actually be harmful.
491 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
494 //===---------------------------------------------------------------------===//
495 // TargetLowering Callbacks
496 //===---------------------------------------------------------------------===//
498 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
499 const SmallVectorImpl<ISD::InputArg> &Ins) const {
501 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
504 SDValue AMDGPUTargetLowering::LowerReturn(
506 CallingConv::ID CallConv,
508 const SmallVectorImpl<ISD::OutputArg> &Outs,
509 const SmallVectorImpl<SDValue> &OutVals,
510 SDLoc DL, SelectionDAG &DAG) const {
511 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
514 //===---------------------------------------------------------------------===//
515 // Target specific lowering
516 //===---------------------------------------------------------------------===//
518 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
519 SmallVectorImpl<SDValue> &InVals) const {
520 SDValue Callee = CLI.Callee;
521 SelectionDAG &DAG = CLI.DAG;
523 const Function &Fn = *DAG.getMachineFunction().getFunction();
525 StringRef FuncName("<unknown>");
527 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
528 FuncName = G->getSymbol();
529 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
530 FuncName = G->getGlobal()->getName();
532 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
533 DAG.getContext()->diagnose(NoCalls);
537 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
538 SelectionDAG &DAG) const {
539 switch (Op.getOpcode()) {
541 Op.getNode()->dump();
542 llvm_unreachable("Custom lowering code for this"
543 "instruction is not implemented yet!");
545 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
546 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
547 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
548 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
549 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
550 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
551 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
552 case ISD::FREM: return LowerFREM(Op, DAG);
553 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
554 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
555 case ISD::FRINT: return LowerFRINT(Op, DAG);
556 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
557 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
558 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
563 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
564 SmallVectorImpl<SDValue> &Results,
565 SelectionDAG &DAG) const {
566 switch (N->getOpcode()) {
567 case ISD::SIGN_EXTEND_INREG:
568 // Different parts of legalization seem to interpret which type of
569 // sign_extend_inreg is the one to check for custom lowering. The extended
570 // from type is what really matters, but some places check for custom
571 // lowering of the result type. This results in trying to use
572 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
573 // nothing here and let the illegal result integer be handled normally.
576 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
580 Results.push_back(SDValue(Node, 0));
581 Results.push_back(SDValue(Node, 1));
582 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
584 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
588 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
589 if (Lowered.getNode())
590 Results.push_back(Lowered);
598 // FIXME: This implements accesses to initialized globals in the constant
599 // address space by copying them to private and accessing that. It does not
600 // properly handle illegal types or vectors. The private vector loads are not
601 // scalarized, and the illegal scalars hit an assertion. This technique will not
602 // work well with large initializers, and this should eventually be
603 // removed. Initialized globals should be placed into a data section that the
604 // runtime will load into a buffer before the kernel is executed. Uses of the
605 // global need to be replaced with a pointer loaded from an implicit kernel
606 // argument into this buffer holding the copy of the data, which will remove the
607 // need for any of this.
608 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
609 const GlobalValue *GV,
610 const SDValue &InitPtr,
612 SelectionDAG &DAG) const {
613 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
615 Type *InitTy = Init->getType();
617 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
618 EVT VT = EVT::getEVT(InitTy);
619 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
620 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
621 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
622 TD->getPrefTypeAlignment(InitTy));
625 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
626 EVT VT = EVT::getEVT(CFP->getType());
627 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
628 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
629 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
630 TD->getPrefTypeAlignment(CFP->getType()));
633 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
634 const StructLayout *SL = TD->getStructLayout(ST);
636 EVT PtrVT = InitPtr.getValueType();
637 SmallVector<SDValue, 8> Chains;
639 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
640 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
641 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
643 Constant *Elt = Init->getAggregateElement(I);
644 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
647 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
650 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
651 EVT PtrVT = InitPtr.getValueType();
653 unsigned NumElements;
654 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
655 NumElements = AT->getNumElements();
656 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
657 NumElements = VT->getNumElements();
659 llvm_unreachable("Unexpected type");
661 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
662 SmallVector<SDValue, 8> Chains;
663 for (unsigned i = 0; i < NumElements; ++i) {
664 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
665 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
667 Constant *Elt = Init->getAggregateElement(i);
668 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
671 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
674 if (isa<UndefValue>(Init)) {
675 EVT VT = EVT::getEVT(InitTy);
676 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
677 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
678 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
679 TD->getPrefTypeAlignment(InitTy));
683 llvm_unreachable("Unhandled constant initializer");
686 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
688 SelectionDAG &DAG) const {
690 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
691 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
692 const GlobalValue *GV = G->getGlobal();
694 switch (G->getAddressSpace()) {
695 default: llvm_unreachable("Global Address lowering not implemented for this "
697 case AMDGPUAS::LOCAL_ADDRESS: {
698 // XXX: What does the value of G->getOffset() mean?
699 assert(G->getOffset() == 0 &&
700 "Do not know what to do with an non-zero offset");
703 if (MFI->LocalMemoryObjects.count(GV) == 0) {
704 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
705 Offset = MFI->LDSSize;
706 MFI->LocalMemoryObjects[GV] = Offset;
707 // XXX: Account for alignment?
708 MFI->LDSSize += Size;
710 Offset = MFI->LocalMemoryObjects[GV];
713 return DAG.getConstant(Offset, getPointerTy(AMDGPUAS::LOCAL_ADDRESS));
715 case AMDGPUAS::CONSTANT_ADDRESS: {
716 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
717 Type *EltType = GV->getType()->getElementType();
718 unsigned Size = TD->getTypeAllocSize(EltType);
719 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
721 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
722 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
724 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
725 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
727 const GlobalVariable *Var = cast<GlobalVariable>(GV);
728 if (!Var->hasInitializer()) {
729 // This has no use, but bugpoint will hit it.
730 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
733 const Constant *Init = Var->getInitializer();
734 SmallVector<SDNode*, 8> WorkList;
736 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
737 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
738 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
740 WorkList.push_back(*I);
742 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
743 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
744 E = WorkList.end(); I != E; ++I) {
745 SmallVector<SDValue, 8> Ops;
746 Ops.push_back(Chain);
747 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
748 Ops.push_back((*I)->getOperand(i));
750 DAG.UpdateNodeOperands(*I, Ops);
752 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
757 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
758 SelectionDAG &DAG) const {
759 SmallVector<SDValue, 8> Args;
760 SDValue A = Op.getOperand(0);
761 SDValue B = Op.getOperand(1);
763 DAG.ExtractVectorElements(A, Args);
764 DAG.ExtractVectorElements(B, Args);
766 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
769 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
770 SelectionDAG &DAG) const {
772 SmallVector<SDValue, 8> Args;
773 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
774 EVT VT = Op.getValueType();
775 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
776 VT.getVectorNumElements());
778 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
781 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
782 SelectionDAG &DAG) const {
784 MachineFunction &MF = DAG.getMachineFunction();
785 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
786 getTargetMachine().getSubtargetImpl()->getFrameLowering());
788 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
790 unsigned FrameIndex = FIN->getIndex();
791 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
792 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
796 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
797 SelectionDAG &DAG) const {
798 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
800 EVT VT = Op.getValueType();
802 switch (IntrinsicID) {
804 case AMDGPUIntrinsic::AMDGPU_abs:
805 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
806 return LowerIntrinsicIABS(Op, DAG);
807 case AMDGPUIntrinsic::AMDGPU_lrp:
808 return LowerIntrinsicLRP(Op, DAG);
809 case AMDGPUIntrinsic::AMDGPU_fract:
810 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
811 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
813 case AMDGPUIntrinsic::AMDGPU_clamp:
814 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
815 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
816 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
818 case Intrinsic::AMDGPU_div_scale: {
819 // 3rd parameter required to be a constant.
820 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
822 return DAG.getUNDEF(VT);
824 // Translate to the operands expected by the machine instruction. The
825 // first parameter must be the same as the first instruction.
826 SDValue Numerator = Op.getOperand(1);
827 SDValue Denominator = Op.getOperand(2);
828 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
830 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
831 Denominator, Numerator);
834 case Intrinsic::AMDGPU_div_fmas:
835 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
836 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
838 case Intrinsic::AMDGPU_div_fixup:
839 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
840 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
842 case Intrinsic::AMDGPU_trig_preop:
843 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
844 Op.getOperand(1), Op.getOperand(2));
846 case Intrinsic::AMDGPU_rcp:
847 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
849 case Intrinsic::AMDGPU_rsq:
850 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
852 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
853 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
855 case Intrinsic::AMDGPU_rsq_clamped:
856 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
858 case Intrinsic::AMDGPU_ldexp:
859 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
862 case AMDGPUIntrinsic::AMDGPU_imax:
863 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
865 case AMDGPUIntrinsic::AMDGPU_umax:
866 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
868 case AMDGPUIntrinsic::AMDGPU_imin:
869 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
871 case AMDGPUIntrinsic::AMDGPU_umin:
872 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
875 case AMDGPUIntrinsic::AMDGPU_umul24:
876 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
877 Op.getOperand(1), Op.getOperand(2));
879 case AMDGPUIntrinsic::AMDGPU_imul24:
880 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
881 Op.getOperand(1), Op.getOperand(2));
883 case AMDGPUIntrinsic::AMDGPU_umad24:
884 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
885 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
887 case AMDGPUIntrinsic::AMDGPU_imad24:
888 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
889 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
891 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
892 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
894 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
895 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
897 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
898 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
900 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
901 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
903 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
904 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
909 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
910 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
915 case AMDGPUIntrinsic::AMDGPU_bfi:
916 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
921 case AMDGPUIntrinsic::AMDGPU_bfm:
922 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
926 case AMDGPUIntrinsic::AMDGPU_brev:
927 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
929 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
930 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
932 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
933 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
934 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
935 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
939 ///IABS(a) = SMAX(sub(0, a), a)
940 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
941 SelectionDAG &DAG) const {
943 EVT VT = Op.getValueType();
944 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
947 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
950 /// Linear Interpolation
951 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
952 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
953 SelectionDAG &DAG) const {
955 EVT VT = Op.getValueType();
956 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
957 DAG.getConstantFP(1.0f, MVT::f32),
959 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
961 return DAG.getNode(ISD::FADD, DL, VT,
962 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
966 /// \brief Generate Min/Max node
967 SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
968 SelectionDAG &DAG) const {
970 EVT VT = N->getValueType(0);
972 SDValue LHS = N->getOperand(0);
973 SDValue RHS = N->getOperand(1);
974 SDValue True = N->getOperand(2);
975 SDValue False = N->getOperand(3);
976 SDValue CC = N->getOperand(4);
978 if (VT != MVT::f32 ||
979 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
983 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
997 llvm_unreachable("Operation should already be optimised!");
1004 unsigned Opc = (LHS == True) ? AMDGPUISD::FMIN : AMDGPUISD::FMAX;
1005 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1013 unsigned Opc = (LHS == True) ? AMDGPUISD::FMAX : AMDGPUISD::FMIN;
1014 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1016 case ISD::SETCC_INVALID:
1017 llvm_unreachable("Invalid setcc condcode!");
1022 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1023 SelectionDAG &DAG) const {
1024 LoadSDNode *Load = cast<LoadSDNode>(Op);
1025 EVT MemVT = Load->getMemoryVT();
1026 EVT MemEltVT = MemVT.getVectorElementType();
1028 EVT LoadVT = Op.getValueType();
1029 EVT EltVT = LoadVT.getVectorElementType();
1030 EVT PtrVT = Load->getBasePtr().getValueType();
1032 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1033 SmallVector<SDValue, 8> Loads;
1034 SmallVector<SDValue, 8> Chains;
1037 unsigned MemEltSize = MemEltVT.getStoreSize();
1038 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1040 for (unsigned i = 0; i < NumElts; ++i) {
1041 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1042 DAG.getConstant(i * MemEltSize, PtrVT));
1045 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1046 Load->getChain(), Ptr,
1047 SrcValue.getWithOffset(i * MemEltSize),
1048 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1049 Load->isInvariant(), Load->getAlignment());
1050 Loads.push_back(NewLoad.getValue(0));
1051 Chains.push_back(NewLoad.getValue(1));
1055 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1056 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1059 return DAG.getMergeValues(Ops, SL);
1062 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1063 SelectionDAG &DAG) const {
1064 EVT VT = Op.getValueType();
1066 // If this is a 2 element vector, we really want to scalarize and not create
1067 // weird 1 element vectors.
1068 if (VT.getVectorNumElements() == 2)
1069 return ScalarizeVectorLoad(Op, DAG);
1071 LoadSDNode *Load = cast<LoadSDNode>(Op);
1072 SDValue BasePtr = Load->getBasePtr();
1073 EVT PtrVT = BasePtr.getValueType();
1074 EVT MemVT = Load->getMemoryVT();
1076 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1079 EVT LoMemVT, HiMemVT;
1082 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1083 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1084 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1086 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1087 Load->getChain(), BasePtr,
1089 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1090 Load->isInvariant(), Load->getAlignment());
1092 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1093 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1096 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1097 Load->getChain(), HiPtr,
1098 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1099 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1100 Load->isInvariant(), Load->getAlignment());
1103 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1104 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1105 LoLoad.getValue(1), HiLoad.getValue(1))
1108 return DAG.getMergeValues(Ops, SL);
1111 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1112 SelectionDAG &DAG) const {
1113 StoreSDNode *Store = cast<StoreSDNode>(Op);
1114 EVT MemVT = Store->getMemoryVT();
1115 unsigned MemBits = MemVT.getSizeInBits();
1117 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1118 // truncating store into an i32 store.
1119 // XXX: We could also handle optimize other vector bitwidths.
1120 if (!MemVT.isVector() || MemBits > 32) {
1125 SDValue Value = Store->getValue();
1126 EVT VT = Value.getValueType();
1127 EVT ElemVT = VT.getVectorElementType();
1128 SDValue Ptr = Store->getBasePtr();
1129 EVT MemEltVT = MemVT.getVectorElementType();
1130 unsigned MemEltBits = MemEltVT.getSizeInBits();
1131 unsigned MemNumElements = MemVT.getVectorNumElements();
1132 unsigned PackedSize = MemVT.getStoreSizeInBits();
1133 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1135 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1137 SDValue PackedValue;
1138 for (unsigned i = 0; i < MemNumElements; ++i) {
1139 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1140 DAG.getConstant(i, MVT::i32));
1141 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1142 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1144 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1145 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1150 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1154 if (PackedSize < 32) {
1155 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1156 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1157 Store->getMemOperand()->getPointerInfo(),
1159 Store->isNonTemporal(), Store->isVolatile(),
1160 Store->getAlignment());
1163 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1164 Store->getMemOperand()->getPointerInfo(),
1165 Store->isVolatile(), Store->isNonTemporal(),
1166 Store->getAlignment());
1169 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1170 SelectionDAG &DAG) const {
1171 StoreSDNode *Store = cast<StoreSDNode>(Op);
1172 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1173 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1174 EVT PtrVT = Store->getBasePtr().getValueType();
1175 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1178 SmallVector<SDValue, 8> Chains;
1180 unsigned EltSize = MemEltVT.getStoreSize();
1181 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1183 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1184 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1186 DAG.getConstant(i, MVT::i32));
1188 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), PtrVT);
1189 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1191 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1192 SrcValue.getWithOffset(i * EltSize),
1193 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1194 Store->getAlignment());
1195 Chains.push_back(NewStore);
1198 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1201 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1202 SelectionDAG &DAG) const {
1203 StoreSDNode *Store = cast<StoreSDNode>(Op);
1204 SDValue Val = Store->getValue();
1205 EVT VT = Val.getValueType();
1207 // If this is a 2 element vector, we really want to scalarize and not create
1208 // weird 1 element vectors.
1209 if (VT.getVectorNumElements() == 2)
1210 return ScalarizeVectorStore(Op, DAG);
1212 EVT MemVT = Store->getMemoryVT();
1213 SDValue Chain = Store->getChain();
1214 SDValue BasePtr = Store->getBasePtr();
1218 EVT LoMemVT, HiMemVT;
1221 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1222 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1223 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1225 EVT PtrVT = BasePtr.getValueType();
1226 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1227 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1229 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1231 = DAG.getTruncStore(Chain, SL, Lo,
1235 Store->isNonTemporal(),
1236 Store->isVolatile(),
1237 Store->getAlignment());
1239 = DAG.getTruncStore(Chain, SL, Hi,
1241 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1243 Store->isNonTemporal(),
1244 Store->isVolatile(),
1245 Store->getAlignment());
1247 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1251 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1253 LoadSDNode *Load = cast<LoadSDNode>(Op);
1254 ISD::LoadExtType ExtType = Load->getExtensionType();
1255 EVT VT = Op.getValueType();
1256 EVT MemVT = Load->getMemoryVT();
1258 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1259 // We can do the extload to 32-bits, and then need to separately extend to
1262 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1266 Load->getMemOperand());
1269 DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32),
1270 ExtLoad32.getValue(1)
1273 return DAG.getMergeValues(Ops, DL);
1276 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1277 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1278 // FIXME: Copied from PPC
1279 // First, load into 32 bits, then truncate to 1 bit.
1281 SDValue Chain = Load->getChain();
1282 SDValue BasePtr = Load->getBasePtr();
1283 MachineMemOperand *MMO = Load->getMemOperand();
1285 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1286 BasePtr, MVT::i8, MMO);
1289 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1293 return DAG.getMergeValues(Ops, DL);
1296 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1297 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1298 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1302 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1303 DAG.getConstant(2, MVT::i32));
1304 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1305 Load->getChain(), Ptr,
1306 DAG.getTargetConstant(0, MVT::i32),
1308 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1310 DAG.getConstant(0x3, MVT::i32));
1311 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1312 DAG.getConstant(3, MVT::i32));
1314 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1316 EVT MemEltVT = MemVT.getScalarType();
1317 if (ExtType == ISD::SEXTLOAD) {
1318 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1321 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1325 return DAG.getMergeValues(Ops, DL);
1329 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1333 return DAG.getMergeValues(Ops, DL);
1336 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1338 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1339 if (Result.getNode()) {
1343 StoreSDNode *Store = cast<StoreSDNode>(Op);
1344 SDValue Chain = Store->getChain();
1345 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1346 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1347 Store->getValue().getValueType().isVector()) {
1348 return ScalarizeVectorStore(Op, DAG);
1351 EVT MemVT = Store->getMemoryVT();
1352 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1353 MemVT.bitsLT(MVT::i32)) {
1355 if (Store->getMemoryVT() == MVT::i8) {
1357 } else if (Store->getMemoryVT() == MVT::i16) {
1360 SDValue BasePtr = Store->getBasePtr();
1361 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1362 DAG.getConstant(2, MVT::i32));
1363 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1364 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1366 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1367 DAG.getConstant(0x3, MVT::i32));
1369 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1370 DAG.getConstant(3, MVT::i32));
1372 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1375 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1377 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1378 MaskedValue, ShiftAmt);
1380 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1382 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1383 DAG.getConstant(0xffffffff, MVT::i32));
1384 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1386 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1387 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1388 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1393 // This is a shortcut for integer division because we have fast i32<->f32
1394 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1395 // float is enough to accurately represent up to a 24-bit integer.
1396 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1398 EVT VT = Op.getValueType();
1399 SDValue LHS = Op.getOperand(0);
1400 SDValue RHS = Op.getOperand(1);
1401 MVT IntVT = MVT::i32;
1402 MVT FltVT = MVT::f32;
1404 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1405 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1407 if (VT.isVector()) {
1408 unsigned NElts = VT.getVectorNumElements();
1409 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1410 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1413 unsigned BitSize = VT.getScalarType().getSizeInBits();
1415 SDValue jq = DAG.getConstant(1, IntVT);
1418 // char|short jq = ia ^ ib;
1419 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1421 // jq = jq >> (bitsize - 2)
1422 jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
1425 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));
1428 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1431 // int ia = (int)LHS;
1433 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1435 // int ib, (int)RHS;
1437 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1439 // float fa = (float)ia;
1440 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1442 // float fb = (float)ib;
1443 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1445 // float fq = native_divide(fa, fb);
1446 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1447 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1450 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1452 // float fqneg = -fq;
1453 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1455 // float fr = mad(fqneg, fb, fa);
1456 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1457 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1459 // int iq = (int)fq;
1460 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1463 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1466 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1468 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), VT);
1470 // int cv = fr >= fb;
1471 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1473 // jq = (cv ? jq : 0);
1474 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
1476 // dst = trunc/extend to legal type
1477 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1480 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1482 // Rem needs compensation, it's easier to recompute it
1483 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1484 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1490 return DAG.getMergeValues(Res, DL);
1493 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1494 SelectionDAG &DAG) const {
1496 EVT VT = Op.getValueType();
1498 SDValue Num = Op.getOperand(0);
1499 SDValue Den = Op.getOperand(1);
1501 if (VT == MVT::i32) {
1502 if (DAG.MaskedValueIsZero(Op.getOperand(0), APInt(32, 0xff << 24)) &&
1503 DAG.MaskedValueIsZero(Op.getOperand(1), APInt(32, 0xff << 24))) {
1504 // TODO: We technically could do this for i64, but shouldn't that just be
1505 // handled by something generally reducing 64-bit division on 32-bit
1506 // values to 32-bit?
1507 return LowerDIVREM24(Op, DAG, false);
1511 // RCP = URECIP(Den) = 2^32 / Den + e
1512 // e is rounding error.
1513 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1515 // RCP_LO = mul(RCP, Den) */
1516 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1518 // RCP_HI = mulhu (RCP, Den) */
1519 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1521 // NEG_RCP_LO = -RCP_LO
1522 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1525 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1526 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1529 // Calculate the rounding error from the URECIP instruction
1530 // E = mulhu(ABS_RCP_LO, RCP)
1531 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1533 // RCP_A_E = RCP + E
1534 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1536 // RCP_S_E = RCP - E
1537 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1539 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1540 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1543 // Quotient = mulhu(Tmp0, Num)
1544 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1546 // Num_S_Remainder = Quotient * Den
1547 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1549 // Remainder = Num - Num_S_Remainder
1550 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1552 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1553 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1554 DAG.getConstant(-1, VT),
1555 DAG.getConstant(0, VT),
1557 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1558 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1560 DAG.getConstant(-1, VT),
1561 DAG.getConstant(0, VT),
1563 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1564 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1567 // Calculate Division result:
1569 // Quotient_A_One = Quotient + 1
1570 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1571 DAG.getConstant(1, VT));
1573 // Quotient_S_One = Quotient - 1
1574 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1575 DAG.getConstant(1, VT));
1577 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1578 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1579 Quotient, Quotient_A_One, ISD::SETEQ);
1581 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1582 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1583 Quotient_S_One, Div, ISD::SETEQ);
1585 // Calculate Rem result:
1587 // Remainder_S_Den = Remainder - Den
1588 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1590 // Remainder_A_Den = Remainder + Den
1591 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1593 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1594 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1595 Remainder, Remainder_S_Den, ISD::SETEQ);
1597 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1598 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1599 Remainder_A_Den, Rem, ISD::SETEQ);
1604 return DAG.getMergeValues(Ops, DL);
1607 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1608 SelectionDAG &DAG) const {
1610 EVT VT = Op.getValueType();
1612 SDValue LHS = Op.getOperand(0);
1613 SDValue RHS = Op.getOperand(1);
1615 if (VT == MVT::i32) {
1616 if (DAG.ComputeNumSignBits(Op.getOperand(0)) > 8 &&
1617 DAG.ComputeNumSignBits(Op.getOperand(1)) > 8) {
1618 // TODO: We technically could do this for i64, but shouldn't that just be
1619 // handled by something generally reducing 64-bit division on 32-bit
1620 // values to 32-bit?
1621 return LowerDIVREM24(Op, DAG, true);
1625 SDValue Zero = DAG.getConstant(0, VT);
1626 SDValue NegOne = DAG.getConstant(-1, VT);
1628 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1629 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1630 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1631 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1633 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1634 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1636 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1637 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1639 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1640 SDValue Rem = Div.getValue(1);
1642 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1643 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1645 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1646 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1652 return DAG.getMergeValues(Res, DL);
1655 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1656 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1658 EVT VT = Op.getValueType();
1659 SDValue X = Op.getOperand(0);
1660 SDValue Y = Op.getOperand(1);
1662 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1663 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1664 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1666 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1669 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1671 SDValue Src = Op.getOperand(0);
1673 // result = trunc(src)
1674 // if (src > 0.0 && src != result)
1677 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1679 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1680 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1682 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1684 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1685 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1686 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1688 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1689 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1692 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1694 SDValue Src = Op.getOperand(0);
1696 assert(Op.getValueType() == MVT::f64);
1698 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1699 const SDValue One = DAG.getConstant(1, MVT::i32);
1701 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1703 // Extract the upper half, since this is where we will find the sign and
1705 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1707 const unsigned FractBits = 52;
1708 const unsigned ExpBits = 11;
1710 // Extract the exponent.
1711 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_I32, SL, MVT::i32,
1713 DAG.getConstant(FractBits - 32, MVT::i32),
1714 DAG.getConstant(ExpBits, MVT::i32));
1715 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1716 DAG.getConstant(1023, MVT::i32));
1718 // Extract the sign bit.
1719 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1720 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1722 // Extend back to to 64-bits.
1723 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1725 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1727 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1728 const SDValue FractMask
1729 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1731 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1732 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1733 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1735 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1737 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1739 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1740 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1742 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1743 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1745 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1748 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1750 SDValue Src = Op.getOperand(0);
1752 assert(Op.getValueType() == MVT::f64);
1754 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1755 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1756 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1758 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1759 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1761 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1763 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1764 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
1766 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1767 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1769 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1772 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1773 // FNEARBYINT and FRINT are the same, except in their handling of FP
1774 // exceptions. Those aren't really meaningful for us, and OpenCL only has
1775 // rint, so just treat them as equivalent.
1776 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1779 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1781 SDValue Src = Op.getOperand(0);
1783 // result = trunc(src);
1784 // if (src < 0.0 && src != result)
1787 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1789 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1790 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
1792 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1794 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
1795 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1796 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1798 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
1799 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1802 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1803 SelectionDAG &DAG) const {
1804 SDValue S0 = Op.getOperand(0);
1806 if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64)
1809 // f32 uint_to_fp i64
1810 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1811 DAG.getConstant(0, MVT::i32));
1812 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1813 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1814 DAG.getConstant(1, MVT::i32));
1815 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1816 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1817 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1818 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1821 SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
1823 SelectionDAG &DAG) const {
1824 MVT VT = Op.getSimpleValueType();
1826 SDValue Shift = DAG.getConstant(BitsDiff, VT);
1827 // Shift left by 'Shift' bits.
1828 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
1829 // Signed shift Right by 'Shift' bits.
1830 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
1833 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1834 SelectionDAG &DAG) const {
1835 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1836 MVT VT = Op.getSimpleValueType();
1837 MVT ScalarVT = VT.getScalarType();
1842 SDValue Src = Op.getOperand(0);
1845 // TODO: Don't scalarize on Evergreen?
1846 unsigned NElts = VT.getVectorNumElements();
1847 SmallVector<SDValue, 8> Args;
1848 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1850 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1851 for (unsigned I = 0; I < NElts; ++I)
1852 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1854 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1857 //===----------------------------------------------------------------------===//
1858 // Custom DAG optimizations
1859 //===----------------------------------------------------------------------===//
1861 static bool isU24(SDValue Op, SelectionDAG &DAG) {
1862 APInt KnownZero, KnownOne;
1863 EVT VT = Op.getValueType();
1864 DAG.computeKnownBits(Op, KnownZero, KnownOne);
1866 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1869 static bool isI24(SDValue Op, SelectionDAG &DAG) {
1870 EVT VT = Op.getValueType();
1872 // In order for this to be a signed 24-bit value, bit 23, must
1874 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1875 // as unsigned 24-bit values.
1876 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1879 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
1881 SelectionDAG &DAG = DCI.DAG;
1882 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1883 EVT VT = Op.getValueType();
1885 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
1886 APInt KnownZero, KnownOne;
1887 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
1888 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
1889 DCI.CommitTargetLoweringOpt(TLO);
1892 template <typename IntTy>
1893 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
1894 uint32_t Offset, uint32_t Width) {
1895 if (Width + Offset < 32) {
1896 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
1897 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
1898 return DAG.getConstant(Result, MVT::i32);
1901 return DAG.getConstant(Src0 >> Offset, MVT::i32);
1904 static bool usesAllNormalStores(SDNode *LoadVal) {
1905 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
1906 if (!ISD::isNormalStore(*I))
1913 // If we have a copy of an illegal type, replace it with a load / store of an
1914 // equivalently sized legal type. This avoids intermediate bit pack / unpack
1915 // instructions emitted when handling extloads and truncstores. Ideally we could
1916 // recognize the pack / unpack pattern to eliminate it.
1917 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
1918 DAGCombinerInfo &DCI) const {
1919 if (!DCI.isBeforeLegalize())
1922 StoreSDNode *SN = cast<StoreSDNode>(N);
1923 SDValue Value = SN->getValue();
1924 EVT VT = Value.getValueType();
1926 if (isTypeLegal(VT) || SN->isVolatile() || !ISD::isNormalLoad(Value.getNode()))
1929 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
1930 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
1933 EVT MemVT = LoadVal->getMemoryVT();
1936 SelectionDAG &DAG = DCI.DAG;
1937 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
1939 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
1941 LoadVal->getChain(),
1942 LoadVal->getBasePtr(),
1943 LoadVal->getOffset(),
1945 LoadVal->getMemOperand());
1947 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
1948 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
1950 return DAG.getStore(SN->getChain(), SL, NewLoad,
1951 SN->getBasePtr(), SN->getMemOperand());
1954 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
1955 DAGCombinerInfo &DCI) const {
1956 EVT VT = N->getValueType(0);
1958 if (VT.isVector() || VT.getSizeInBits() > 32)
1961 SelectionDAG &DAG = DCI.DAG;
1964 SDValue N0 = N->getOperand(0);
1965 SDValue N1 = N->getOperand(1);
1968 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
1969 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
1970 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
1971 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
1972 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
1973 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
1974 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
1975 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
1980 // We need to use sext even for MUL_U24, because MUL_U24 is used
1981 // for signed multiply of 8 and 16-bit types.
1982 return DAG.getSExtOrTrunc(Mul, DL, VT);
1985 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
1986 DAGCombinerInfo &DCI) const {
1987 SelectionDAG &DAG = DCI.DAG;
1990 switch(N->getOpcode()) {
1993 return performMulCombine(N, DCI);
1994 case AMDGPUISD::MUL_I24:
1995 case AMDGPUISD::MUL_U24: {
1996 SDValue N0 = N->getOperand(0);
1997 SDValue N1 = N->getOperand(1);
1998 simplifyI24(N0, DCI);
1999 simplifyI24(N1, DCI);
2002 case ISD::SELECT_CC: {
2003 return CombineMinMax(N, DAG);
2005 case AMDGPUISD::BFE_I32:
2006 case AMDGPUISD::BFE_U32: {
2007 assert(!N->getValueType(0).isVector() &&
2008 "Vector handling of BFE not implemented");
2009 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2013 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2015 return DAG.getConstant(0, MVT::i32);
2017 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2021 SDValue BitsFrom = N->getOperand(0);
2022 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2024 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2026 if (OffsetVal == 0) {
2027 // This is already sign / zero extended, so try to fold away extra BFEs.
2028 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2030 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2031 if (OpSignBits >= SignBits)
2034 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2036 // This is a sign_extend_inreg. Replace it to take advantage of existing
2037 // DAG Combines. If not eliminated, we will match back to BFE during
2040 // TODO: The sext_inreg of extended types ends, although we can could
2041 // handle them in a single BFE.
2042 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2043 DAG.getValueType(SmallVT));
2046 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2049 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2051 // Avoid undefined left shift of a negative in the constant fold.
2052 // TODO: I'm not sure what the behavior of the hardware is, this should
2053 // probably follow that instead.
2054 return constantFoldBFE<int32_t>(DAG,
2055 CVal->getSExtValue(),
2060 return constantFoldBFE<uint32_t>(DAG,
2061 CVal->getZExtValue(),
2066 APInt Demanded = APInt::getBitsSet(32,
2068 OffsetVal + WidthVal);
2070 if ((OffsetVal + WidthVal) >= 32) {
2071 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
2072 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2073 BitsFrom, ShiftVal);
2076 APInt KnownZero, KnownOne;
2077 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2078 !DCI.isBeforeLegalizeOps());
2079 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2080 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2081 TLI.SimplifyDemandedBits(BitsFrom, Demanded, KnownZero, KnownOne, TLO)) {
2082 DCI.CommitTargetLoweringOpt(TLO);
2089 return performStoreCombine(N, DCI);
2094 //===----------------------------------------------------------------------===//
2096 //===----------------------------------------------------------------------===//
2098 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2101 const SmallVectorImpl<ISD::InputArg> &Ins,
2102 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2104 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2105 if (Ins[i].ArgVT == Ins[i].VT) {
2106 OrigIns.push_back(Ins[i]);
2111 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2112 // Vector has been split into scalars.
2113 VT = Ins[i].ArgVT.getVectorElementType();
2114 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2115 Ins[i].ArgVT.getVectorElementType() !=
2116 Ins[i].VT.getVectorElementType()) {
2117 // Vector elements have been promoted
2120 // Vector has been spilt into smaller vectors.
2124 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2125 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2126 OrigIns.push_back(Arg);
2130 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2131 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2132 return CFP->isExactlyValue(1.0);
2134 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2135 return C->isAllOnesValue();
2140 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2141 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2142 return CFP->getValueAPF().isZero();
2144 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2145 return C->isNullValue();
2150 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2151 const TargetRegisterClass *RC,
2152 unsigned Reg, EVT VT) const {
2153 MachineFunction &MF = DAG.getMachineFunction();
2154 MachineRegisterInfo &MRI = MF.getRegInfo();
2155 unsigned VirtualRegister;
2156 if (!MRI.isLiveIn(Reg)) {
2157 VirtualRegister = MRI.createVirtualRegister(RC);
2158 MRI.addLiveIn(Reg, VirtualRegister);
2160 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2162 return DAG.getRegister(VirtualRegister, VT);
2165 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2167 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2169 default: return nullptr;
2171 NODE_NAME_CASE(CALL);
2172 NODE_NAME_CASE(UMUL);
2173 NODE_NAME_CASE(RET_FLAG);
2174 NODE_NAME_CASE(BRANCH_COND);
2177 NODE_NAME_CASE(DWORDADDR)
2178 NODE_NAME_CASE(FRACT)
2179 NODE_NAME_CASE(CLAMP)
2181 NODE_NAME_CASE(FMAX)
2182 NODE_NAME_CASE(SMAX)
2183 NODE_NAME_CASE(UMAX)
2184 NODE_NAME_CASE(FMIN)
2185 NODE_NAME_CASE(SMIN)
2186 NODE_NAME_CASE(UMIN)
2187 NODE_NAME_CASE(URECIP)
2188 NODE_NAME_CASE(DIV_SCALE)
2189 NODE_NAME_CASE(DIV_FMAS)
2190 NODE_NAME_CASE(DIV_FIXUP)
2191 NODE_NAME_CASE(TRIG_PREOP)
2194 NODE_NAME_CASE(RSQ_LEGACY)
2195 NODE_NAME_CASE(RSQ_CLAMPED)
2196 NODE_NAME_CASE(LDEXP)
2197 NODE_NAME_CASE(DOT4)
2198 NODE_NAME_CASE(BFE_U32)
2199 NODE_NAME_CASE(BFE_I32)
2202 NODE_NAME_CASE(BREV)
2203 NODE_NAME_CASE(MUL_U24)
2204 NODE_NAME_CASE(MUL_I24)
2205 NODE_NAME_CASE(MAD_U24)
2206 NODE_NAME_CASE(MAD_I24)
2207 NODE_NAME_CASE(EXPORT)
2208 NODE_NAME_CASE(CONST_ADDRESS)
2209 NODE_NAME_CASE(REGISTER_LOAD)
2210 NODE_NAME_CASE(REGISTER_STORE)
2211 NODE_NAME_CASE(LOAD_CONSTANT)
2212 NODE_NAME_CASE(LOAD_INPUT)
2213 NODE_NAME_CASE(SAMPLE)
2214 NODE_NAME_CASE(SAMPLEB)
2215 NODE_NAME_CASE(SAMPLED)
2216 NODE_NAME_CASE(SAMPLEL)
2217 NODE_NAME_CASE(CVT_F32_UBYTE0)
2218 NODE_NAME_CASE(CVT_F32_UBYTE1)
2219 NODE_NAME_CASE(CVT_F32_UBYTE2)
2220 NODE_NAME_CASE(CVT_F32_UBYTE3)
2221 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2222 NODE_NAME_CASE(CONST_DATA_PTR)
2223 NODE_NAME_CASE(STORE_MSKOR)
2224 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2228 static void computeKnownBitsForMinMax(const SDValue Op0,
2232 const SelectionDAG &DAG,
2234 APInt Op0Zero, Op0One;
2235 APInt Op1Zero, Op1One;
2236 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2237 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2239 KnownZero = Op0Zero & Op1Zero;
2240 KnownOne = Op0One & Op1One;
2243 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2247 const SelectionDAG &DAG,
2248 unsigned Depth) const {
2250 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2254 unsigned Opc = Op.getOpcode();
2259 case ISD::INTRINSIC_WO_CHAIN: {
2260 // FIXME: The intrinsic should just use the node.
2261 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2262 case AMDGPUIntrinsic::AMDGPU_imax:
2263 case AMDGPUIntrinsic::AMDGPU_umax:
2264 case AMDGPUIntrinsic::AMDGPU_imin:
2265 case AMDGPUIntrinsic::AMDGPU_umin:
2266 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2267 KnownZero, KnownOne, DAG, Depth);
2275 case AMDGPUISD::SMAX:
2276 case AMDGPUISD::UMAX:
2277 case AMDGPUISD::SMIN:
2278 case AMDGPUISD::UMIN:
2279 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2280 KnownZero, KnownOne, DAG, Depth);
2283 case AMDGPUISD::BFE_I32:
2284 case AMDGPUISD::BFE_U32: {
2285 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2289 unsigned BitWidth = 32;
2290 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2292 KnownZero = APInt::getAllOnesValue(BitWidth);
2293 KnownOne = APInt::getNullValue(BitWidth);
2297 // FIXME: This could do a lot more. If offset is 0, should be the same as
2298 // sign_extend_inreg implementation, but that involves duplicating it.
2299 if (Opc == AMDGPUISD::BFE_I32)
2300 KnownOne = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2302 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2309 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2311 const SelectionDAG &DAG,
2312 unsigned Depth) const {
2313 switch (Op.getOpcode()) {
2314 case AMDGPUISD::BFE_I32: {
2315 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2319 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2320 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2321 if (!Offset || !Offset->isNullValue())
2324 // TODO: Could probably figure something out with non-0 offsets.
2325 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2326 return std::max(SignBits, Op0SignBits);
2329 case AMDGPUISD::BFE_U32: {
2330 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2331 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;