1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
106 const AMDGPUSubtarget &STI)
107 : TargetLowering(TM), Subtarget(&STI) {
108 setOperationAction(ISD::Constant, MVT::i32, Legal);
109 setOperationAction(ISD::Constant, MVT::i64, Legal);
110 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
111 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
114 setOperationAction(ISD::BRIND, MVT::Other, Expand);
116 // We need to custom lower some of the intrinsics
117 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
119 // Library functions. These default to Expand, but we have instructions
121 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
122 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
123 setOperationAction(ISD::FPOW, MVT::f32, Legal);
124 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
125 setOperationAction(ISD::FABS, MVT::f32, Legal);
126 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
127 setOperationAction(ISD::FRINT, MVT::f32, Legal);
128 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
130 setOperationAction(ISD::FROUND, MVT::f32, Custom);
131 setOperationAction(ISD::FROUND, MVT::f64, Custom);
133 setOperationAction(ISD::FREM, MVT::f32, Custom);
134 setOperationAction(ISD::FREM, MVT::f64, Custom);
136 // v_mad_f32 does not support denormals according to some sources.
137 if (!Subtarget->hasFP32Denormals())
138 setOperationAction(ISD::FMAD, MVT::f32, Legal);
140 // Expand to fneg + fadd.
141 setOperationAction(ISD::FSUB, MVT::f64, Expand);
143 // Lower floating point store/load to integer store/load to reduce the number
144 // of patterns in tablegen.
145 setOperationAction(ISD::STORE, MVT::f32, Promote);
146 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
148 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
149 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
151 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
152 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
154 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
155 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
157 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
158 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
160 setOperationAction(ISD::STORE, MVT::f64, Promote);
161 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
163 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
164 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
166 // Custom lowering of vector stores is required for local address space
168 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
170 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
171 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
172 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
174 // XXX: This can be change to Custom, once ExpandVectorStores can
175 // handle 64-bit stores.
176 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
178 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
179 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
180 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
181 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
182 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
185 setOperationAction(ISD::LOAD, MVT::f32, Promote);
186 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
188 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
189 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
191 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
192 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
194 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
195 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
197 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
198 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
200 setOperationAction(ISD::LOAD, MVT::f64, Promote);
201 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
203 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
204 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
206 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
207 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
210 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
211 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
217 // There are no 64-bit extloads. These should be done as a 32-bit extload and
218 // an extension to 64-bit.
219 for (MVT VT : MVT::integer_valuetypes()) {
220 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
221 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
222 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
225 for (MVT VT : MVT::integer_vector_valuetypes()) {
226 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
227 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
228 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
229 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
230 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
231 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
232 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
233 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
234 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
235 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
236 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
237 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
240 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
242 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
243 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
244 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
245 setOperationAction(ISD::FRINT, MVT::f64, Custom);
246 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
249 if (!Subtarget->hasBFI()) {
250 // fcopysign can be done in a single instruction with BFI.
251 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
252 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
255 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
257 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
258 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
259 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
260 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
262 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
263 for (MVT VT : ScalarIntVTs) {
264 setOperationAction(ISD::SREM, VT, Expand);
265 setOperationAction(ISD::SDIV, VT, Expand);
267 // GPU does not have divrem function for signed or unsigned.
268 setOperationAction(ISD::SDIVREM, VT, Custom);
269 setOperationAction(ISD::UDIVREM, VT, Custom);
271 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
272 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
273 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
275 setOperationAction(ISD::BSWAP, VT, Expand);
276 setOperationAction(ISD::CTTZ, VT, Expand);
277 setOperationAction(ISD::CTLZ, VT, Expand);
280 if (!Subtarget->hasBCNT(32))
281 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
283 if (!Subtarget->hasBCNT(64))
284 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
286 // The hardware supports 32-bit ROTR, but not ROTL.
287 setOperationAction(ISD::ROTL, MVT::i32, Expand);
288 setOperationAction(ISD::ROTL, MVT::i64, Expand);
289 setOperationAction(ISD::ROTR, MVT::i64, Expand);
291 setOperationAction(ISD::MUL, MVT::i64, Expand);
292 setOperationAction(ISD::MULHU, MVT::i64, Expand);
293 setOperationAction(ISD::MULHS, MVT::i64, Expand);
294 setOperationAction(ISD::UDIV, MVT::i32, Expand);
295 setOperationAction(ISD::UREM, MVT::i32, Expand);
296 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
297 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
298 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
299 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
300 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
302 if (!Subtarget->hasFFBH())
303 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
305 if (!Subtarget->hasFFBL())
306 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
308 static const MVT::SimpleValueType VectorIntTypes[] = {
309 MVT::v2i32, MVT::v4i32
312 for (MVT VT : VectorIntTypes) {
313 // Expand the following operations for the current type by default.
314 setOperationAction(ISD::ADD, VT, Expand);
315 setOperationAction(ISD::AND, VT, Expand);
316 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
317 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
318 setOperationAction(ISD::MUL, VT, Expand);
319 setOperationAction(ISD::OR, VT, Expand);
320 setOperationAction(ISD::SHL, VT, Expand);
321 setOperationAction(ISD::SRA, VT, Expand);
322 setOperationAction(ISD::SRL, VT, Expand);
323 setOperationAction(ISD::ROTL, VT, Expand);
324 setOperationAction(ISD::ROTR, VT, Expand);
325 setOperationAction(ISD::SUB, VT, Expand);
326 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
327 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
328 setOperationAction(ISD::SDIV, VT, Expand);
329 setOperationAction(ISD::UDIV, VT, Expand);
330 setOperationAction(ISD::SREM, VT, Expand);
331 setOperationAction(ISD::UREM, VT, Expand);
332 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
333 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
334 setOperationAction(ISD::SDIVREM, VT, Custom);
335 setOperationAction(ISD::UDIVREM, VT, Custom);
336 setOperationAction(ISD::ADDC, VT, Expand);
337 setOperationAction(ISD::SUBC, VT, Expand);
338 setOperationAction(ISD::ADDE, VT, Expand);
339 setOperationAction(ISD::SUBE, VT, Expand);
340 setOperationAction(ISD::SELECT, VT, Expand);
341 setOperationAction(ISD::VSELECT, VT, Expand);
342 setOperationAction(ISD::SELECT_CC, VT, Expand);
343 setOperationAction(ISD::XOR, VT, Expand);
344 setOperationAction(ISD::BSWAP, VT, Expand);
345 setOperationAction(ISD::CTPOP, VT, Expand);
346 setOperationAction(ISD::CTTZ, VT, Expand);
347 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
348 setOperationAction(ISD::CTLZ, VT, Expand);
349 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
350 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
353 static const MVT::SimpleValueType FloatVectorTypes[] = {
354 MVT::v2f32, MVT::v4f32
357 for (MVT VT : FloatVectorTypes) {
358 setOperationAction(ISD::FABS, VT, Expand);
359 setOperationAction(ISD::FMINNUM, VT, Expand);
360 setOperationAction(ISD::FMAXNUM, VT, Expand);
361 setOperationAction(ISD::FADD, VT, Expand);
362 setOperationAction(ISD::FCEIL, VT, Expand);
363 setOperationAction(ISD::FCOS, VT, Expand);
364 setOperationAction(ISD::FDIV, VT, Expand);
365 setOperationAction(ISD::FEXP2, VT, Expand);
366 setOperationAction(ISD::FLOG2, VT, Expand);
367 setOperationAction(ISD::FREM, VT, Expand);
368 setOperationAction(ISD::FPOW, VT, Expand);
369 setOperationAction(ISD::FFLOOR, VT, Expand);
370 setOperationAction(ISD::FTRUNC, VT, Expand);
371 setOperationAction(ISD::FMUL, VT, Expand);
372 setOperationAction(ISD::FMA, VT, Expand);
373 setOperationAction(ISD::FRINT, VT, Expand);
374 setOperationAction(ISD::FNEARBYINT, VT, Expand);
375 setOperationAction(ISD::FSQRT, VT, Expand);
376 setOperationAction(ISD::FSIN, VT, Expand);
377 setOperationAction(ISD::FSUB, VT, Expand);
378 setOperationAction(ISD::FNEG, VT, Expand);
379 setOperationAction(ISD::SELECT, VT, Expand);
380 setOperationAction(ISD::VSELECT, VT, Expand);
381 setOperationAction(ISD::SELECT_CC, VT, Expand);
382 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
383 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
386 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
387 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
389 setTargetDAGCombine(ISD::MUL);
390 setTargetDAGCombine(ISD::SELECT);
391 setTargetDAGCombine(ISD::SELECT_CC);
392 setTargetDAGCombine(ISD::STORE);
394 setTargetDAGCombine(ISD::FADD);
395 setTargetDAGCombine(ISD::FSUB);
397 setBooleanContents(ZeroOrNegativeOneBooleanContent);
398 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
400 setSchedulingPreference(Sched::RegPressure);
401 setJumpIsExpensive(true);
403 // SI at least has hardware support for floating point exceptions, but no way
404 // of using or handling them is implemented. They are also optional in OpenCL
406 setHasFloatingPointExceptions(false);
408 setSelectIsExpensive(false);
409 PredictableSelectIsExpensive = false;
411 // There are no integer divide instructions, and these expand to a pretty
412 // large sequence of instructions.
413 setIntDivIsCheap(false);
414 setPow2SDivIsCheap(false);
415 setFsqrtIsCheap(true);
417 // FIXME: Need to really handle these.
418 MaxStoresPerMemcpy = 4096;
419 MaxStoresPerMemmove = 4096;
420 MaxStoresPerMemset = 4096;
423 //===----------------------------------------------------------------------===//
424 // Target Information
425 //===----------------------------------------------------------------------===//
427 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
431 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
435 // The backend supports 32 and 64 bit floating point immediates.
436 // FIXME: Why are we reporting vectors of FP immediates as legal?
437 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
438 EVT ScalarVT = VT.getScalarType();
439 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
442 // We don't want to shrink f64 / f32 constants.
443 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
444 EVT ScalarVT = VT.getScalarType();
445 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
448 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
452 unsigned NewSize = NewVT.getStoreSizeInBits();
454 // If we are reducing to a 32-bit load, this is always better.
458 EVT OldVT = N->getValueType(0);
459 unsigned OldSize = OldVT.getStoreSizeInBits();
461 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
462 // extloads, so doing one requires using a buffer_load. In cases where we
463 // still couldn't use a scalar load, using the wider load shouldn't really
466 // If the old size already had to be an extload, there's no harm in continuing
467 // to reduce the width.
468 return (OldSize < 32);
471 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
473 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
476 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
477 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
479 return ((LScalarSize <= CastScalarSize) ||
480 (CastScalarSize >= 32) ||
484 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
485 // profitable with the expansion for 64-bit since it's generally good to
487 // FIXME: These should really have the size as a parameter.
488 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
492 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
496 //===---------------------------------------------------------------------===//
498 //===---------------------------------------------------------------------===//
500 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
501 assert(VT.isFloatingPoint());
502 return VT == MVT::f32 || VT == MVT::f64;
505 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
506 assert(VT.isFloatingPoint());
507 return VT == MVT::f32 || VT == MVT::f64;
510 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
511 // Truncate is just accessing a subregister.
512 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
515 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
516 // Truncate is just accessing a subregister.
517 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
518 (Dest->getPrimitiveSizeInBits() % 32 == 0);
521 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
522 const DataLayout *DL = getDataLayout();
523 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
524 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
526 return SrcSize == 32 && DestSize == 64;
529 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
530 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
531 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
532 // this will enable reducing 64-bit operations the 32-bit, which is always
534 return Src == MVT::i32 && Dest == MVT::i64;
537 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
538 return isZExtFree(Val.getValueType(), VT2);
541 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
542 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
543 // limited number of native 64-bit operations. Shrinking an operation to fit
544 // in a single 32-bit register should always be helpful. As currently used,
545 // this is much less general than the name suggests, and is only used in
546 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
547 // not profitable, and may actually be harmful.
548 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
551 //===---------------------------------------------------------------------===//
552 // TargetLowering Callbacks
553 //===---------------------------------------------------------------------===//
555 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
556 const SmallVectorImpl<ISD::InputArg> &Ins) const {
558 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
561 SDValue AMDGPUTargetLowering::LowerReturn(
563 CallingConv::ID CallConv,
565 const SmallVectorImpl<ISD::OutputArg> &Outs,
566 const SmallVectorImpl<SDValue> &OutVals,
567 SDLoc DL, SelectionDAG &DAG) const {
568 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
571 //===---------------------------------------------------------------------===//
572 // Target specific lowering
573 //===---------------------------------------------------------------------===//
575 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
576 SmallVectorImpl<SDValue> &InVals) const {
577 SDValue Callee = CLI.Callee;
578 SelectionDAG &DAG = CLI.DAG;
580 const Function &Fn = *DAG.getMachineFunction().getFunction();
582 StringRef FuncName("<unknown>");
584 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
585 FuncName = G->getSymbol();
586 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
587 FuncName = G->getGlobal()->getName();
589 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
590 DAG.getContext()->diagnose(NoCalls);
594 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
595 SelectionDAG &DAG) const {
596 switch (Op.getOpcode()) {
598 Op.getNode()->dump();
599 llvm_unreachable("Custom lowering code for this"
600 "instruction is not implemented yet!");
602 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
603 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
604 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
605 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
606 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
607 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
608 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
609 case ISD::FREM: return LowerFREM(Op, DAG);
610 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
611 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
612 case ISD::FRINT: return LowerFRINT(Op, DAG);
613 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
614 case ISD::FROUND: return LowerFROUND(Op, DAG);
615 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
616 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
617 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
618 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
619 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
624 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
625 SmallVectorImpl<SDValue> &Results,
626 SelectionDAG &DAG) const {
627 switch (N->getOpcode()) {
628 case ISD::SIGN_EXTEND_INREG:
629 // Different parts of legalization seem to interpret which type of
630 // sign_extend_inreg is the one to check for custom lowering. The extended
631 // from type is what really matters, but some places check for custom
632 // lowering of the result type. This results in trying to use
633 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
634 // nothing here and let the illegal result integer be handled normally.
637 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
641 Results.push_back(SDValue(Node, 0));
642 Results.push_back(SDValue(Node, 1));
643 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
645 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
649 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
650 if (Lowered.getNode())
651 Results.push_back(Lowered);
659 // FIXME: This implements accesses to initialized globals in the constant
660 // address space by copying them to private and accessing that. It does not
661 // properly handle illegal types or vectors. The private vector loads are not
662 // scalarized, and the illegal scalars hit an assertion. This technique will not
663 // work well with large initializers, and this should eventually be
664 // removed. Initialized globals should be placed into a data section that the
665 // runtime will load into a buffer before the kernel is executed. Uses of the
666 // global need to be replaced with a pointer loaded from an implicit kernel
667 // argument into this buffer holding the copy of the data, which will remove the
668 // need for any of this.
669 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
670 const GlobalValue *GV,
671 const SDValue &InitPtr,
673 SelectionDAG &DAG) const {
674 const DataLayout *TD = getDataLayout();
676 Type *InitTy = Init->getType();
678 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
679 EVT VT = EVT::getEVT(InitTy);
680 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
681 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
682 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
683 TD->getPrefTypeAlignment(InitTy));
686 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
687 EVT VT = EVT::getEVT(CFP->getType());
688 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
689 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
690 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
691 TD->getPrefTypeAlignment(CFP->getType()));
694 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
695 const StructLayout *SL = TD->getStructLayout(ST);
697 EVT PtrVT = InitPtr.getValueType();
698 SmallVector<SDValue, 8> Chains;
700 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
701 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
702 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
704 Constant *Elt = Init->getAggregateElement(I);
705 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
708 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
711 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
712 EVT PtrVT = InitPtr.getValueType();
714 unsigned NumElements;
715 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
716 NumElements = AT->getNumElements();
717 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
718 NumElements = VT->getNumElements();
720 llvm_unreachable("Unexpected type");
722 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
723 SmallVector<SDValue, 8> Chains;
724 for (unsigned i = 0; i < NumElements; ++i) {
725 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
726 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
728 Constant *Elt = Init->getAggregateElement(i);
729 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
732 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
735 if (isa<UndefValue>(Init)) {
736 EVT VT = EVT::getEVT(InitTy);
737 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
738 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
739 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
740 TD->getPrefTypeAlignment(InitTy));
744 llvm_unreachable("Unhandled constant initializer");
747 static bool hasDefinedInitializer(const GlobalValue *GV) {
748 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
749 if (!GVar || !GVar->hasInitializer())
752 if (isa<UndefValue>(GVar->getInitializer()))
758 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
760 SelectionDAG &DAG) const {
762 const DataLayout *TD = getDataLayout();
763 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
764 const GlobalValue *GV = G->getGlobal();
766 switch (G->getAddressSpace()) {
767 case AMDGPUAS::LOCAL_ADDRESS: {
768 // XXX: What does the value of G->getOffset() mean?
769 assert(G->getOffset() == 0 &&
770 "Do not know what to do with an non-zero offset");
772 // TODO: We could emit code to handle the initialization somewhere.
773 if (hasDefinedInitializer(GV))
777 if (MFI->LocalMemoryObjects.count(GV) == 0) {
778 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
779 Offset = MFI->LDSSize;
780 MFI->LocalMemoryObjects[GV] = Offset;
781 // XXX: Account for alignment?
782 MFI->LDSSize += Size;
784 Offset = MFI->LocalMemoryObjects[GV];
787 return DAG.getConstant(Offset, getPointerTy(AMDGPUAS::LOCAL_ADDRESS));
789 case AMDGPUAS::CONSTANT_ADDRESS: {
790 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
791 Type *EltType = GV->getType()->getElementType();
792 unsigned Size = TD->getTypeAllocSize(EltType);
793 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
795 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
796 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
798 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
799 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
801 const GlobalVariable *Var = cast<GlobalVariable>(GV);
802 if (!Var->hasInitializer()) {
803 // This has no use, but bugpoint will hit it.
804 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
807 const Constant *Init = Var->getInitializer();
808 SmallVector<SDNode*, 8> WorkList;
810 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
811 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
812 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
814 WorkList.push_back(*I);
816 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
817 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
818 E = WorkList.end(); I != E; ++I) {
819 SmallVector<SDValue, 8> Ops;
820 Ops.push_back(Chain);
821 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
822 Ops.push_back((*I)->getOperand(i));
824 DAG.UpdateNodeOperands(*I, Ops);
826 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
830 const Function &Fn = *DAG.getMachineFunction().getFunction();
831 DiagnosticInfoUnsupported BadInit(Fn,
832 "initializer for address space");
833 DAG.getContext()->diagnose(BadInit);
837 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
838 SelectionDAG &DAG) const {
839 SmallVector<SDValue, 8> Args;
840 SDValue A = Op.getOperand(0);
841 SDValue B = Op.getOperand(1);
843 DAG.ExtractVectorElements(A, Args);
844 DAG.ExtractVectorElements(B, Args);
846 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
849 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
850 SelectionDAG &DAG) const {
852 SmallVector<SDValue, 8> Args;
853 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
854 EVT VT = Op.getValueType();
855 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
856 VT.getVectorNumElements());
858 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
861 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
862 SelectionDAG &DAG) const {
864 MachineFunction &MF = DAG.getMachineFunction();
865 const AMDGPUFrameLowering *TFL = Subtarget->getFrameLowering();
867 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
869 unsigned FrameIndex = FIN->getIndex();
870 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
871 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
875 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
876 SelectionDAG &DAG) const {
877 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
879 EVT VT = Op.getValueType();
881 switch (IntrinsicID) {
883 case AMDGPUIntrinsic::AMDGPU_abs:
884 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
885 return LowerIntrinsicIABS(Op, DAG);
886 case AMDGPUIntrinsic::AMDGPU_lrp:
887 return LowerIntrinsicLRP(Op, DAG);
888 case AMDGPUIntrinsic::AMDGPU_fract:
889 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
890 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
892 case AMDGPUIntrinsic::AMDGPU_clamp:
893 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
894 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
895 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
897 case Intrinsic::AMDGPU_div_scale: {
898 // 3rd parameter required to be a constant.
899 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
901 return DAG.getUNDEF(VT);
903 // Translate to the operands expected by the machine instruction. The
904 // first parameter must be the same as the first instruction.
905 SDValue Numerator = Op.getOperand(1);
906 SDValue Denominator = Op.getOperand(2);
908 // Note this order is opposite of the machine instruction's operations,
909 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
910 // intrinsic has the numerator as the first operand to match a normal
911 // division operation.
913 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
915 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
916 Denominator, Numerator);
919 case Intrinsic::AMDGPU_div_fmas:
920 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
921 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
924 case Intrinsic::AMDGPU_div_fixup:
925 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
926 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
928 case Intrinsic::AMDGPU_trig_preop:
929 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
930 Op.getOperand(1), Op.getOperand(2));
932 case Intrinsic::AMDGPU_rcp:
933 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
935 case Intrinsic::AMDGPU_rsq:
936 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
938 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
939 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
941 case Intrinsic::AMDGPU_rsq_clamped:
942 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
943 Type *Type = VT.getTypeForEVT(*DAG.getContext());
944 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
945 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
947 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
948 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
949 DAG.getConstantFP(Max, VT));
950 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
951 DAG.getConstantFP(Min, VT));
953 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
956 case Intrinsic::AMDGPU_ldexp:
957 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
960 case AMDGPUIntrinsic::AMDGPU_imax:
961 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
963 case AMDGPUIntrinsic::AMDGPU_umax:
964 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
966 case AMDGPUIntrinsic::AMDGPU_imin:
967 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
969 case AMDGPUIntrinsic::AMDGPU_umin:
970 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
973 case AMDGPUIntrinsic::AMDGPU_umul24:
974 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
975 Op.getOperand(1), Op.getOperand(2));
977 case AMDGPUIntrinsic::AMDGPU_imul24:
978 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
979 Op.getOperand(1), Op.getOperand(2));
981 case AMDGPUIntrinsic::AMDGPU_umad24:
982 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
983 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
985 case AMDGPUIntrinsic::AMDGPU_imad24:
986 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
987 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
989 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
990 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
992 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
993 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
995 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
996 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
998 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
999 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
1001 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
1002 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
1007 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
1008 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
1013 case AMDGPUIntrinsic::AMDGPU_bfi:
1014 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
1019 case AMDGPUIntrinsic::AMDGPU_bfm:
1020 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
1024 case AMDGPUIntrinsic::AMDGPU_brev:
1025 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
1027 case Intrinsic::AMDGPU_class:
1028 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
1029 Op.getOperand(1), Op.getOperand(2));
1031 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
1032 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
1034 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
1035 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
1036 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
1037 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
1041 ///IABS(a) = SMAX(sub(0, a), a)
1042 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
1043 SelectionDAG &DAG) const {
1045 EVT VT = Op.getValueType();
1046 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1049 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
1052 /// Linear Interpolation
1053 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
1054 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
1055 SelectionDAG &DAG) const {
1057 EVT VT = Op.getValueType();
1058 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
1059 DAG.getConstantFP(1.0f, MVT::f32),
1061 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
1063 return DAG.getNode(ISD::FADD, DL, VT,
1064 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1068 /// \brief Generate Min/Max node
1069 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
1076 DAGCombinerInfo &DCI) const {
1077 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1080 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1083 SelectionDAG &DAG = DCI.DAG;
1084 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1093 case ISD::SETFALSE2:
1102 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1103 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1109 // Ordered. Assume ordered for undefined.
1111 // Only do this after legalization to avoid interfering with other combines
1112 // which might occur.
1113 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1114 !DCI.isCalledByLegalizer())
1117 // We need to permute the operands to get the correct NaN behavior. The
1118 // selected operand is the second one based on the failing compare with NaN,
1119 // so permute it based on the compare type the hardware uses.
1121 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1122 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1127 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1128 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1134 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1135 !DCI.isCalledByLegalizer())
1139 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1140 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1142 case ISD::SETCC_INVALID:
1143 llvm_unreachable("Invalid setcc condcode!");
1148 /// \brief Generate Min/Max node
1149 SDValue AMDGPUTargetLowering::CombineIMinMax(SDLoc DL,
1156 SelectionDAG &DAG) const {
1157 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1160 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1164 unsigned Opc = (LHS == True) ? AMDGPUISD::UMIN : AMDGPUISD::UMAX;
1165 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1169 unsigned Opc = (LHS == True) ? AMDGPUISD::SMIN : AMDGPUISD::SMAX;
1170 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1174 unsigned Opc = (LHS == True) ? AMDGPUISD::SMAX : AMDGPUISD::SMIN;
1175 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1179 unsigned Opc = (LHS == True) ? AMDGPUISD::UMAX : AMDGPUISD::UMIN;
1180 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1187 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1188 SelectionDAG &DAG) const {
1189 LoadSDNode *Load = cast<LoadSDNode>(Op);
1190 EVT MemVT = Load->getMemoryVT();
1191 EVT MemEltVT = MemVT.getVectorElementType();
1193 EVT LoadVT = Op.getValueType();
1194 EVT EltVT = LoadVT.getVectorElementType();
1195 EVT PtrVT = Load->getBasePtr().getValueType();
1197 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1198 SmallVector<SDValue, 8> Loads;
1199 SmallVector<SDValue, 8> Chains;
1202 unsigned MemEltSize = MemEltVT.getStoreSize();
1203 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1205 for (unsigned i = 0; i < NumElts; ++i) {
1206 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1207 DAG.getConstant(i * MemEltSize, PtrVT));
1210 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1211 Load->getChain(), Ptr,
1212 SrcValue.getWithOffset(i * MemEltSize),
1213 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1214 Load->isInvariant(), Load->getAlignment());
1215 Loads.push_back(NewLoad.getValue(0));
1216 Chains.push_back(NewLoad.getValue(1));
1220 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1221 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1224 return DAG.getMergeValues(Ops, SL);
1227 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1228 SelectionDAG &DAG) const {
1229 EVT VT = Op.getValueType();
1231 // If this is a 2 element vector, we really want to scalarize and not create
1232 // weird 1 element vectors.
1233 if (VT.getVectorNumElements() == 2)
1234 return ScalarizeVectorLoad(Op, DAG);
1236 LoadSDNode *Load = cast<LoadSDNode>(Op);
1237 SDValue BasePtr = Load->getBasePtr();
1238 EVT PtrVT = BasePtr.getValueType();
1239 EVT MemVT = Load->getMemoryVT();
1241 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1244 EVT LoMemVT, HiMemVT;
1247 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1248 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1249 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1251 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1252 Load->getChain(), BasePtr,
1254 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1255 Load->isInvariant(), Load->getAlignment());
1257 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1258 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1261 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1262 Load->getChain(), HiPtr,
1263 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1264 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1265 Load->isInvariant(), Load->getAlignment());
1268 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1269 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1270 LoLoad.getValue(1), HiLoad.getValue(1))
1273 return DAG.getMergeValues(Ops, SL);
1276 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1277 SelectionDAG &DAG) const {
1278 StoreSDNode *Store = cast<StoreSDNode>(Op);
1279 EVT MemVT = Store->getMemoryVT();
1280 unsigned MemBits = MemVT.getSizeInBits();
1282 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1283 // truncating store into an i32 store.
1284 // XXX: We could also handle optimize other vector bitwidths.
1285 if (!MemVT.isVector() || MemBits > 32) {
1290 SDValue Value = Store->getValue();
1291 EVT VT = Value.getValueType();
1292 EVT ElemVT = VT.getVectorElementType();
1293 SDValue Ptr = Store->getBasePtr();
1294 EVT MemEltVT = MemVT.getVectorElementType();
1295 unsigned MemEltBits = MemEltVT.getSizeInBits();
1296 unsigned MemNumElements = MemVT.getVectorNumElements();
1297 unsigned PackedSize = MemVT.getStoreSizeInBits();
1298 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1300 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1302 SDValue PackedValue;
1303 for (unsigned i = 0; i < MemNumElements; ++i) {
1304 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1305 DAG.getConstant(i, MVT::i32));
1306 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1307 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1309 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1310 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1315 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1319 if (PackedSize < 32) {
1320 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1321 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1322 Store->getMemOperand()->getPointerInfo(),
1324 Store->isNonTemporal(), Store->isVolatile(),
1325 Store->getAlignment());
1328 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1329 Store->getMemOperand()->getPointerInfo(),
1330 Store->isVolatile(), Store->isNonTemporal(),
1331 Store->getAlignment());
1334 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1335 SelectionDAG &DAG) const {
1336 StoreSDNode *Store = cast<StoreSDNode>(Op);
1337 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1338 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1339 EVT PtrVT = Store->getBasePtr().getValueType();
1340 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1343 SmallVector<SDValue, 8> Chains;
1345 unsigned EltSize = MemEltVT.getStoreSize();
1346 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1348 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1349 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1351 DAG.getConstant(i, MVT::i32));
1353 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), PtrVT);
1354 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1356 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1357 SrcValue.getWithOffset(i * EltSize),
1358 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1359 Store->getAlignment());
1360 Chains.push_back(NewStore);
1363 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1366 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1367 SelectionDAG &DAG) const {
1368 StoreSDNode *Store = cast<StoreSDNode>(Op);
1369 SDValue Val = Store->getValue();
1370 EVT VT = Val.getValueType();
1372 // If this is a 2 element vector, we really want to scalarize and not create
1373 // weird 1 element vectors.
1374 if (VT.getVectorNumElements() == 2)
1375 return ScalarizeVectorStore(Op, DAG);
1377 EVT MemVT = Store->getMemoryVT();
1378 SDValue Chain = Store->getChain();
1379 SDValue BasePtr = Store->getBasePtr();
1383 EVT LoMemVT, HiMemVT;
1386 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1387 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1388 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1390 EVT PtrVT = BasePtr.getValueType();
1391 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1392 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1394 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1396 = DAG.getTruncStore(Chain, SL, Lo,
1400 Store->isNonTemporal(),
1401 Store->isVolatile(),
1402 Store->getAlignment());
1404 = DAG.getTruncStore(Chain, SL, Hi,
1406 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1408 Store->isNonTemporal(),
1409 Store->isVolatile(),
1410 Store->getAlignment());
1412 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1416 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1418 LoadSDNode *Load = cast<LoadSDNode>(Op);
1419 ISD::LoadExtType ExtType = Load->getExtensionType();
1420 EVT VT = Op.getValueType();
1421 EVT MemVT = Load->getMemoryVT();
1423 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1424 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1425 // FIXME: Copied from PPC
1426 // First, load into 32 bits, then truncate to 1 bit.
1428 SDValue Chain = Load->getChain();
1429 SDValue BasePtr = Load->getBasePtr();
1430 MachineMemOperand *MMO = Load->getMemOperand();
1432 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1433 BasePtr, MVT::i8, MMO);
1436 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1440 return DAG.getMergeValues(Ops, DL);
1443 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1444 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1445 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1449 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1450 DAG.getConstant(2, MVT::i32));
1451 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1452 Load->getChain(), Ptr,
1453 DAG.getTargetConstant(0, MVT::i32),
1455 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1457 DAG.getConstant(0x3, MVT::i32));
1458 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1459 DAG.getConstant(3, MVT::i32));
1461 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1463 EVT MemEltVT = MemVT.getScalarType();
1464 if (ExtType == ISD::SEXTLOAD) {
1465 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1468 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1472 return DAG.getMergeValues(Ops, DL);
1476 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1480 return DAG.getMergeValues(Ops, DL);
1483 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1485 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1486 if (Result.getNode()) {
1490 StoreSDNode *Store = cast<StoreSDNode>(Op);
1491 SDValue Chain = Store->getChain();
1492 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1493 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1494 Store->getValue().getValueType().isVector()) {
1495 return ScalarizeVectorStore(Op, DAG);
1498 EVT MemVT = Store->getMemoryVT();
1499 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1500 MemVT.bitsLT(MVT::i32)) {
1502 if (Store->getMemoryVT() == MVT::i8) {
1504 } else if (Store->getMemoryVT() == MVT::i16) {
1507 SDValue BasePtr = Store->getBasePtr();
1508 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1509 DAG.getConstant(2, MVT::i32));
1510 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1511 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1513 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1514 DAG.getConstant(0x3, MVT::i32));
1516 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1517 DAG.getConstant(3, MVT::i32));
1519 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1522 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1524 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1525 MaskedValue, ShiftAmt);
1527 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1529 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1530 DAG.getConstant(0xffffffff, MVT::i32));
1531 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1533 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1534 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1535 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1540 // This is a shortcut for integer division because we have fast i32<->f32
1541 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1542 // float is enough to accurately represent up to a 24-bit integer.
1543 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1545 EVT VT = Op.getValueType();
1546 SDValue LHS = Op.getOperand(0);
1547 SDValue RHS = Op.getOperand(1);
1548 MVT IntVT = MVT::i32;
1549 MVT FltVT = MVT::f32;
1551 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1552 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1554 if (VT.isVector()) {
1555 unsigned NElts = VT.getVectorNumElements();
1556 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1557 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1560 unsigned BitSize = VT.getScalarType().getSizeInBits();
1562 SDValue jq = DAG.getConstant(1, IntVT);
1565 // char|short jq = ia ^ ib;
1566 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1568 // jq = jq >> (bitsize - 2)
1569 jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
1572 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));
1575 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1578 // int ia = (int)LHS;
1580 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1582 // int ib, (int)RHS;
1584 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1586 // float fa = (float)ia;
1587 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1589 // float fb = (float)ib;
1590 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1592 // float fq = native_divide(fa, fb);
1593 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1594 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1597 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1599 // float fqneg = -fq;
1600 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1602 // float fr = mad(fqneg, fb, fa);
1603 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1604 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1606 // int iq = (int)fq;
1607 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1610 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1613 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1615 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), VT);
1617 // int cv = fr >= fb;
1618 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1620 // jq = (cv ? jq : 0);
1621 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
1623 // dst = trunc/extend to legal type
1624 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1627 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1629 // Rem needs compensation, it's easier to recompute it
1630 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1631 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1637 return DAG.getMergeValues(Res, DL);
1640 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1642 SmallVectorImpl<SDValue> &Results) const {
1643 assert(Op.getValueType() == MVT::i64);
1646 EVT VT = Op.getValueType();
1647 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1649 SDValue one = DAG.getConstant(1, HalfVT);
1650 SDValue zero = DAG.getConstant(0, HalfVT);
1653 SDValue LHS = Op.getOperand(0);
1654 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1655 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1657 SDValue RHS = Op.getOperand(1);
1658 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1659 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1661 if (VT == MVT::i64 &&
1662 DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1663 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1665 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1668 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero);
1669 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero);
1670 Results.push_back(DIV);
1671 Results.push_back(REM);
1675 // Get Speculative values
1676 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1677 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1679 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1680 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero);
1682 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1683 SDValue DIV_Lo = zero;
1685 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1687 for (unsigned i = 0; i < halfBitWidth; ++i) {
1688 const unsigned bitPos = halfBitWidth - i - 1;
1689 SDValue POS = DAG.getConstant(bitPos, HalfVT);
1690 // Get value of high bit
1691 // TODO: Remove the BFE part when the optimization is fixed
1693 if (halfBitWidth == 32 && Subtarget->hasBFE()) {
1694 HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
1696 HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1697 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1699 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1702 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, VT));
1704 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1706 SDValue BIT = DAG.getConstant(1 << bitPos, HalfVT);
1707 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1709 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1712 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1713 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1716 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
1717 Results.push_back(DIV);
1718 Results.push_back(REM);
1721 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1722 SelectionDAG &DAG) const {
1724 EVT VT = Op.getValueType();
1726 if (VT == MVT::i64) {
1727 SmallVector<SDValue, 2> Results;
1728 LowerUDIVREM64(Op, DAG, Results);
1729 return DAG.getMergeValues(Results, DL);
1732 SDValue Num = Op.getOperand(0);
1733 SDValue Den = Op.getOperand(1);
1735 if (VT == MVT::i32) {
1736 if (DAG.MaskedValueIsZero(Num, APInt::getHighBitsSet(32, 8)) &&
1737 DAG.MaskedValueIsZero(Den, APInt::getHighBitsSet(32, 8))) {
1738 // TODO: We technically could do this for i64, but shouldn't that just be
1739 // handled by something generally reducing 64-bit division on 32-bit
1740 // values to 32-bit?
1741 return LowerDIVREM24(Op, DAG, false);
1745 // RCP = URECIP(Den) = 2^32 / Den + e
1746 // e is rounding error.
1747 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1749 // RCP_LO = mul(RCP, Den) */
1750 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1752 // RCP_HI = mulhu (RCP, Den) */
1753 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1755 // NEG_RCP_LO = -RCP_LO
1756 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1759 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1760 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1763 // Calculate the rounding error from the URECIP instruction
1764 // E = mulhu(ABS_RCP_LO, RCP)
1765 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1767 // RCP_A_E = RCP + E
1768 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1770 // RCP_S_E = RCP - E
1771 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1773 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1774 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1777 // Quotient = mulhu(Tmp0, Num)
1778 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1780 // Num_S_Remainder = Quotient * Den
1781 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1783 // Remainder = Num - Num_S_Remainder
1784 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1786 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1787 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1788 DAG.getConstant(-1, VT),
1789 DAG.getConstant(0, VT),
1791 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1792 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1794 DAG.getConstant(-1, VT),
1795 DAG.getConstant(0, VT),
1797 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1798 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1801 // Calculate Division result:
1803 // Quotient_A_One = Quotient + 1
1804 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1805 DAG.getConstant(1, VT));
1807 // Quotient_S_One = Quotient - 1
1808 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1809 DAG.getConstant(1, VT));
1811 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1812 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1813 Quotient, Quotient_A_One, ISD::SETEQ);
1815 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1816 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1817 Quotient_S_One, Div, ISD::SETEQ);
1819 // Calculate Rem result:
1821 // Remainder_S_Den = Remainder - Den
1822 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1824 // Remainder_A_Den = Remainder + Den
1825 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1827 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1828 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1829 Remainder, Remainder_S_Den, ISD::SETEQ);
1831 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1832 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1833 Remainder_A_Den, Rem, ISD::SETEQ);
1838 return DAG.getMergeValues(Ops, DL);
1841 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1842 SelectionDAG &DAG) const {
1844 EVT VT = Op.getValueType();
1846 SDValue LHS = Op.getOperand(0);
1847 SDValue RHS = Op.getOperand(1);
1849 SDValue Zero = DAG.getConstant(0, VT);
1850 SDValue NegOne = DAG.getConstant(-1, VT);
1852 if (VT == MVT::i32 &&
1853 DAG.ComputeNumSignBits(LHS) > 8 &&
1854 DAG.ComputeNumSignBits(RHS) > 8) {
1855 return LowerDIVREM24(Op, DAG, true);
1857 if (VT == MVT::i64 &&
1858 DAG.ComputeNumSignBits(LHS) > 32 &&
1859 DAG.ComputeNumSignBits(RHS) > 32) {
1860 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1863 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1864 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1865 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1868 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1869 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1871 return DAG.getMergeValues(Res, DL);
1874 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1875 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1876 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1877 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1879 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1880 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1882 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1883 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1885 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1886 SDValue Rem = Div.getValue(1);
1888 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1889 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1891 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1892 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1898 return DAG.getMergeValues(Res, DL);
1901 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1902 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1904 EVT VT = Op.getValueType();
1905 SDValue X = Op.getOperand(0);
1906 SDValue Y = Op.getOperand(1);
1908 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1909 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1910 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1912 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1915 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1917 SDValue Src = Op.getOperand(0);
1919 // result = trunc(src)
1920 // if (src > 0.0 && src != result)
1923 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1925 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1926 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1928 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1930 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1931 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1932 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1934 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1935 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1938 static SDValue extractF64Exponent(SDValue Hi, SDLoc SL, SelectionDAG &DAG) {
1939 const unsigned FractBits = 52;
1940 const unsigned ExpBits = 11;
1942 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1944 DAG.getConstant(FractBits - 32, MVT::i32),
1945 DAG.getConstant(ExpBits, MVT::i32));
1946 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1947 DAG.getConstant(1023, MVT::i32));
1952 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1954 SDValue Src = Op.getOperand(0);
1956 assert(Op.getValueType() == MVT::f64);
1958 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1959 const SDValue One = DAG.getConstant(1, MVT::i32);
1961 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1963 // Extract the upper half, since this is where we will find the sign and
1965 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1967 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1969 const unsigned FractBits = 52;
1971 // Extract the sign bit.
1972 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1973 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1975 // Extend back to to 64-bits.
1976 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1978 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1980 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1981 const SDValue FractMask
1982 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1984 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1985 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1986 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1988 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1990 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1992 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1993 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1995 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1996 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1998 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
2001 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
2003 SDValue Src = Op.getOperand(0);
2005 assert(Op.getValueType() == MVT::f64);
2007 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
2008 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
2009 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2011 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2012 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2014 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2016 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
2017 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
2019 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
2020 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2022 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2025 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2026 // FNEARBYINT and FRINT are the same, except in their handling of FP
2027 // exceptions. Those aren't really meaningful for us, and OpenCL only has
2028 // rint, so just treat them as equivalent.
2029 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2032 // XXX - May require not supporting f32 denormals?
2033 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {
2035 SDValue X = Op.getOperand(0);
2037 SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X);
2039 SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T);
2041 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff);
2043 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f32);
2044 const SDValue One = DAG.getConstantFP(1.0, MVT::f32);
2045 const SDValue Half = DAG.getConstantFP(0.5, MVT::f32);
2047 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X);
2049 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f32);
2051 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2053 SDValue Sel = DAG.getNode(ISD::SELECT, SL, MVT::f32, Cmp, SignOne, Zero);
2055 return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel);
2058 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
2060 SDValue X = Op.getOperand(0);
2062 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2064 const SDValue Zero = DAG.getConstant(0, MVT::i32);
2065 const SDValue One = DAG.getConstant(1, MVT::i32);
2066 const SDValue NegOne = DAG.getConstant(-1, MVT::i32);
2067 const SDValue FiftyOne = DAG.getConstant(51, MVT::i32);
2068 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
2071 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2073 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2075 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2077 const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), MVT::i64);
2079 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2080 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2081 DAG.getConstant(INT64_C(0x0008000000000000), MVT::i64),
2084 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2085 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2086 DAG.getConstant(0, MVT::i64), Tmp0,
2089 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2090 D, DAG.getConstant(0, MVT::i64));
2091 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2093 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2094 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2096 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2097 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2098 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2100 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2102 DAG.getConstantFP(1.0, MVT::f64),
2103 DAG.getConstantFP(0.0, MVT::f64));
2105 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2107 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2108 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2113 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2114 EVT VT = Op.getValueType();
2117 return LowerFROUND32(Op, DAG);
2120 return LowerFROUND64(Op, DAG);
2122 llvm_unreachable("unhandled type");
2125 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2127 SDValue Src = Op.getOperand(0);
2129 // result = trunc(src);
2130 // if (src < 0.0 && src != result)
2133 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2135 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
2136 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
2138 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
2140 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2141 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2142 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2144 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2145 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2148 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2149 bool Signed) const {
2151 SDValue Src = Op.getOperand(0);
2153 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2155 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2156 DAG.getConstant(0, MVT::i32));
2157 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2158 DAG.getConstant(1, MVT::i32));
2160 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2163 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2165 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2166 DAG.getConstant(32, MVT::i32));
2168 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2171 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2172 SelectionDAG &DAG) const {
2173 SDValue S0 = Op.getOperand(0);
2174 if (S0.getValueType() != MVT::i64)
2177 EVT DestVT = Op.getValueType();
2178 if (DestVT == MVT::f64)
2179 return LowerINT_TO_FP64(Op, DAG, false);
2181 assert(DestVT == MVT::f32);
2185 // f32 uint_to_fp i64
2186 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2187 DAG.getConstant(0, MVT::i32));
2188 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
2189 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2190 DAG.getConstant(1, MVT::i32));
2191 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
2192 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
2193 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
2194 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
2197 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2198 SelectionDAG &DAG) const {
2199 SDValue Src = Op.getOperand(0);
2200 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
2201 return LowerINT_TO_FP64(Op, DAG, true);
2206 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2207 bool Signed) const {
2210 SDValue Src = Op.getOperand(0);
2212 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2215 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), MVT::f64);
2217 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), MVT::f64);
2219 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2221 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2224 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2226 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2227 MVT::i32, FloorMul);
2228 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2230 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
2232 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2235 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2236 SelectionDAG &DAG) const {
2237 SDValue Src = Op.getOperand(0);
2239 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2240 return LowerFP64_TO_INT(Op, DAG, true);
2245 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2246 SelectionDAG &DAG) const {
2247 SDValue Src = Op.getOperand(0);
2249 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2250 return LowerFP64_TO_INT(Op, DAG, false);
2255 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2256 SelectionDAG &DAG) const {
2257 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2258 MVT VT = Op.getSimpleValueType();
2259 MVT ScalarVT = VT.getScalarType();
2264 SDValue Src = Op.getOperand(0);
2267 // TODO: Don't scalarize on Evergreen?
2268 unsigned NElts = VT.getVectorNumElements();
2269 SmallVector<SDValue, 8> Args;
2270 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2272 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2273 for (unsigned I = 0; I < NElts; ++I)
2274 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2276 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2279 //===----------------------------------------------------------------------===//
2280 // Custom DAG optimizations
2281 //===----------------------------------------------------------------------===//
2283 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2284 APInt KnownZero, KnownOne;
2285 EVT VT = Op.getValueType();
2286 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2288 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2291 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2292 EVT VT = Op.getValueType();
2294 // In order for this to be a signed 24-bit value, bit 23, must
2296 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2297 // as unsigned 24-bit values.
2298 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2301 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2303 SelectionDAG &DAG = DCI.DAG;
2304 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2305 EVT VT = Op.getValueType();
2307 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2308 APInt KnownZero, KnownOne;
2309 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2310 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2311 DCI.CommitTargetLoweringOpt(TLO);
2314 template <typename IntTy>
2315 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2316 uint32_t Offset, uint32_t Width) {
2317 if (Width + Offset < 32) {
2318 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2319 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2320 return DAG.getConstant(Result, MVT::i32);
2323 return DAG.getConstant(Src0 >> Offset, MVT::i32);
2326 static bool usesAllNormalStores(SDNode *LoadVal) {
2327 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2328 if (!ISD::isNormalStore(*I))
2335 // If we have a copy of an illegal type, replace it with a load / store of an
2336 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2337 // instructions emitted when handling extloads and truncstores. Ideally we could
2338 // recognize the pack / unpack pattern to eliminate it.
2339 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2340 DAGCombinerInfo &DCI) const {
2341 if (!DCI.isBeforeLegalize())
2344 StoreSDNode *SN = cast<StoreSDNode>(N);
2345 SDValue Value = SN->getValue();
2346 EVT VT = Value.getValueType();
2348 if (isTypeLegal(VT) || SN->isVolatile() ||
2349 !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2352 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2353 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2356 EVT MemVT = LoadVal->getMemoryVT();
2359 SelectionDAG &DAG = DCI.DAG;
2360 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2362 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2364 LoadVal->getChain(),
2365 LoadVal->getBasePtr(),
2366 LoadVal->getOffset(),
2368 LoadVal->getMemOperand());
2370 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2371 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2373 return DAG.getStore(SN->getChain(), SL, NewLoad,
2374 SN->getBasePtr(), SN->getMemOperand());
2377 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2378 DAGCombinerInfo &DCI) const {
2379 EVT VT = N->getValueType(0);
2381 if (VT.isVector() || VT.getSizeInBits() > 32)
2384 SelectionDAG &DAG = DCI.DAG;
2387 SDValue N0 = N->getOperand(0);
2388 SDValue N1 = N->getOperand(1);
2391 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2392 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2393 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2394 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2395 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2396 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2397 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2398 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2403 // We need to use sext even for MUL_U24, because MUL_U24 is used
2404 // for signed multiply of 8 and 16-bit types.
2405 return DAG.getSExtOrTrunc(Mul, DL, VT);
2408 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2409 DAGCombinerInfo &DCI) const {
2410 SelectionDAG &DAG = DCI.DAG;
2413 switch(N->getOpcode()) {
2416 return performMulCombine(N, DCI);
2417 case AMDGPUISD::MUL_I24:
2418 case AMDGPUISD::MUL_U24: {
2419 SDValue N0 = N->getOperand(0);
2420 SDValue N1 = N->getOperand(1);
2421 simplifyI24(N0, DCI);
2422 simplifyI24(N1, DCI);
2426 SDValue Cond = N->getOperand(0);
2427 if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) {
2429 EVT VT = N->getValueType(0);
2430 SDValue LHS = Cond.getOperand(0);
2431 SDValue RHS = Cond.getOperand(1);
2432 SDValue CC = Cond.getOperand(2);
2434 SDValue True = N->getOperand(1);
2435 SDValue False = N->getOperand(2);
2438 return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
2440 // TODO: Implement min / max Evergreen instructions.
2441 if (VT == MVT::i32 &&
2442 Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
2443 return CombineIMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
2449 case AMDGPUISD::BFE_I32:
2450 case AMDGPUISD::BFE_U32: {
2451 assert(!N->getValueType(0).isVector() &&
2452 "Vector handling of BFE not implemented");
2453 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2457 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2459 return DAG.getConstant(0, MVT::i32);
2461 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2465 SDValue BitsFrom = N->getOperand(0);
2466 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2468 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2470 if (OffsetVal == 0) {
2471 // This is already sign / zero extended, so try to fold away extra BFEs.
2472 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2474 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2475 if (OpSignBits >= SignBits)
2478 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2480 // This is a sign_extend_inreg. Replace it to take advantage of existing
2481 // DAG Combines. If not eliminated, we will match back to BFE during
2484 // TODO: The sext_inreg of extended types ends, although we can could
2485 // handle them in a single BFE.
2486 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2487 DAG.getValueType(SmallVT));
2490 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2493 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2495 return constantFoldBFE<int32_t>(DAG,
2496 CVal->getSExtValue(),
2501 return constantFoldBFE<uint32_t>(DAG,
2502 CVal->getZExtValue(),
2507 if ((OffsetVal + WidthVal) >= 32) {
2508 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
2509 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2510 BitsFrom, ShiftVal);
2513 if (BitsFrom.hasOneUse()) {
2514 APInt Demanded = APInt::getBitsSet(32,
2516 OffsetVal + WidthVal);
2518 APInt KnownZero, KnownOne;
2519 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2520 !DCI.isBeforeLegalizeOps());
2521 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2522 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2523 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2524 KnownZero, KnownOne, TLO)) {
2525 DCI.CommitTargetLoweringOpt(TLO);
2533 return performStoreCombine(N, DCI);
2538 //===----------------------------------------------------------------------===//
2540 //===----------------------------------------------------------------------===//
2542 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2545 const SmallVectorImpl<ISD::InputArg> &Ins,
2546 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2548 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2549 if (Ins[i].ArgVT == Ins[i].VT) {
2550 OrigIns.push_back(Ins[i]);
2555 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2556 // Vector has been split into scalars.
2557 VT = Ins[i].ArgVT.getVectorElementType();
2558 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2559 Ins[i].ArgVT.getVectorElementType() !=
2560 Ins[i].VT.getVectorElementType()) {
2561 // Vector elements have been promoted
2564 // Vector has been spilt into smaller vectors.
2568 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2569 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2570 OrigIns.push_back(Arg);
2574 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2575 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2576 return CFP->isExactlyValue(1.0);
2578 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2579 return C->isAllOnesValue();
2584 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2585 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2586 return CFP->getValueAPF().isZero();
2588 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2589 return C->isNullValue();
2594 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2595 const TargetRegisterClass *RC,
2596 unsigned Reg, EVT VT) const {
2597 MachineFunction &MF = DAG.getMachineFunction();
2598 MachineRegisterInfo &MRI = MF.getRegInfo();
2599 unsigned VirtualRegister;
2600 if (!MRI.isLiveIn(Reg)) {
2601 VirtualRegister = MRI.createVirtualRegister(RC);
2602 MRI.addLiveIn(Reg, VirtualRegister);
2604 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2606 return DAG.getRegister(VirtualRegister, VT);
2609 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2611 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2613 default: return nullptr;
2615 NODE_NAME_CASE(CALL);
2616 NODE_NAME_CASE(UMUL);
2617 NODE_NAME_CASE(RET_FLAG);
2618 NODE_NAME_CASE(BRANCH_COND);
2621 NODE_NAME_CASE(DWORDADDR)
2622 NODE_NAME_CASE(FRACT)
2623 NODE_NAME_CASE(CLAMP)
2624 NODE_NAME_CASE(FMAX_LEGACY)
2625 NODE_NAME_CASE(SMAX)
2626 NODE_NAME_CASE(UMAX)
2627 NODE_NAME_CASE(FMIN_LEGACY)
2628 NODE_NAME_CASE(SMIN)
2629 NODE_NAME_CASE(UMIN)
2630 NODE_NAME_CASE(FMAX3)
2631 NODE_NAME_CASE(SMAX3)
2632 NODE_NAME_CASE(UMAX3)
2633 NODE_NAME_CASE(FMIN3)
2634 NODE_NAME_CASE(SMIN3)
2635 NODE_NAME_CASE(UMIN3)
2636 NODE_NAME_CASE(URECIP)
2637 NODE_NAME_CASE(DIV_SCALE)
2638 NODE_NAME_CASE(DIV_FMAS)
2639 NODE_NAME_CASE(DIV_FIXUP)
2640 NODE_NAME_CASE(TRIG_PREOP)
2643 NODE_NAME_CASE(RSQ_LEGACY)
2644 NODE_NAME_CASE(RSQ_CLAMPED)
2645 NODE_NAME_CASE(LDEXP)
2646 NODE_NAME_CASE(FP_CLASS)
2647 NODE_NAME_CASE(DOT4)
2648 NODE_NAME_CASE(BFE_U32)
2649 NODE_NAME_CASE(BFE_I32)
2652 NODE_NAME_CASE(BREV)
2653 NODE_NAME_CASE(MUL_U24)
2654 NODE_NAME_CASE(MUL_I24)
2655 NODE_NAME_CASE(MAD_U24)
2656 NODE_NAME_CASE(MAD_I24)
2657 NODE_NAME_CASE(EXPORT)
2658 NODE_NAME_CASE(CONST_ADDRESS)
2659 NODE_NAME_CASE(REGISTER_LOAD)
2660 NODE_NAME_CASE(REGISTER_STORE)
2661 NODE_NAME_CASE(LOAD_CONSTANT)
2662 NODE_NAME_CASE(LOAD_INPUT)
2663 NODE_NAME_CASE(SAMPLE)
2664 NODE_NAME_CASE(SAMPLEB)
2665 NODE_NAME_CASE(SAMPLED)
2666 NODE_NAME_CASE(SAMPLEL)
2667 NODE_NAME_CASE(CVT_F32_UBYTE0)
2668 NODE_NAME_CASE(CVT_F32_UBYTE1)
2669 NODE_NAME_CASE(CVT_F32_UBYTE2)
2670 NODE_NAME_CASE(CVT_F32_UBYTE3)
2671 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2672 NODE_NAME_CASE(CONST_DATA_PTR)
2673 NODE_NAME_CASE(STORE_MSKOR)
2674 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2678 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2679 DAGCombinerInfo &DCI,
2680 unsigned &RefinementSteps,
2681 bool &UseOneConstNR) const {
2682 SelectionDAG &DAG = DCI.DAG;
2683 EVT VT = Operand.getValueType();
2685 if (VT == MVT::f32) {
2686 RefinementSteps = 0;
2687 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2690 // TODO: There is also f64 rsq instruction, but the documentation is less
2691 // clear on its precision.
2696 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2697 DAGCombinerInfo &DCI,
2698 unsigned &RefinementSteps) const {
2699 SelectionDAG &DAG = DCI.DAG;
2700 EVT VT = Operand.getValueType();
2702 if (VT == MVT::f32) {
2703 // Reciprocal, < 1 ulp error.
2705 // This reciprocal approximation converges to < 0.5 ulp error with one
2706 // newton rhapson performed with two fused multiple adds (FMAs).
2708 RefinementSteps = 0;
2709 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
2712 // TODO: There is also f64 rcp instruction, but the documentation is less
2713 // clear on its precision.
2718 static void computeKnownBitsForMinMax(const SDValue Op0,
2722 const SelectionDAG &DAG,
2724 APInt Op0Zero, Op0One;
2725 APInt Op1Zero, Op1One;
2726 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2727 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2729 KnownZero = Op0Zero & Op1Zero;
2730 KnownOne = Op0One & Op1One;
2733 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2737 const SelectionDAG &DAG,
2738 unsigned Depth) const {
2740 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2744 unsigned Opc = Op.getOpcode();
2749 case ISD::INTRINSIC_WO_CHAIN: {
2750 // FIXME: The intrinsic should just use the node.
2751 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2752 case AMDGPUIntrinsic::AMDGPU_imax:
2753 case AMDGPUIntrinsic::AMDGPU_umax:
2754 case AMDGPUIntrinsic::AMDGPU_imin:
2755 case AMDGPUIntrinsic::AMDGPU_umin:
2756 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2757 KnownZero, KnownOne, DAG, Depth);
2765 case AMDGPUISD::SMAX:
2766 case AMDGPUISD::UMAX:
2767 case AMDGPUISD::SMIN:
2768 case AMDGPUISD::UMIN:
2769 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2770 KnownZero, KnownOne, DAG, Depth);
2773 case AMDGPUISD::BFE_I32:
2774 case AMDGPUISD::BFE_U32: {
2775 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2779 unsigned BitWidth = 32;
2780 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2782 if (Opc == AMDGPUISD::BFE_U32)
2783 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2790 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2792 const SelectionDAG &DAG,
2793 unsigned Depth) const {
2794 switch (Op.getOpcode()) {
2795 case AMDGPUISD::BFE_I32: {
2796 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2800 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2801 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2802 if (!Offset || !Offset->isNullValue())
2805 // TODO: Could probably figure something out with non-0 offsets.
2806 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2807 return std::max(SignBits, Op0SignBits);
2810 case AMDGPUISD::BFE_U32: {
2811 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2812 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;