1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
106 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
108 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
110 setOperationAction(ISD::Constant, MVT::i32, Legal);
111 setOperationAction(ISD::Constant, MVT::i64, Legal);
112 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
113 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
115 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
116 setOperationAction(ISD::BRIND, MVT::Other, Expand);
118 // We need to custom lower some of the intrinsics
119 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
121 // Library functions. These default to Expand, but we have instructions
123 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
124 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
125 setOperationAction(ISD::FPOW, MVT::f32, Legal);
126 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
127 setOperationAction(ISD::FABS, MVT::f32, Legal);
128 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
129 setOperationAction(ISD::FRINT, MVT::f32, Legal);
130 setOperationAction(ISD::FROUND, MVT::f32, Legal);
131 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
133 setOperationAction(ISD::FREM, MVT::f32, Custom);
134 setOperationAction(ISD::FREM, MVT::f64, Custom);
136 // Lower floating point store/load to integer store/load to reduce the number
137 // of patterns in tablegen.
138 setOperationAction(ISD::STORE, MVT::f32, Promote);
139 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
141 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
142 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
144 setOperationAction(ISD::STORE, MVT::i64, Promote);
145 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
147 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
148 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
150 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
153 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
154 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
156 setOperationAction(ISD::STORE, MVT::f64, Promote);
157 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
159 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
160 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
162 // Custom lowering of vector stores is required for local address space
164 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
165 // XXX: Native v2i32 local address space stores are possible, but not
166 // currently implemented.
167 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
169 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
170 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
171 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
173 // XXX: This can be change to Custom, once ExpandVectorStores can
174 // handle 64-bit stores.
175 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
177 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
178 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
179 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
180 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
181 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
184 setOperationAction(ISD::LOAD, MVT::f32, Promote);
185 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
187 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
190 setOperationAction(ISD::LOAD, MVT::i64, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
193 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
196 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
199 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
200 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
202 setOperationAction(ISD::LOAD, MVT::f64, Promote);
203 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
205 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
206 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
210 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
211 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
216 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
217 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
219 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
220 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
221 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
222 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
223 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
224 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
225 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
226 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
227 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
228 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
229 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
230 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
232 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
234 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
235 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
236 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
237 setOperationAction(ISD::FRINT, MVT::f64, Custom);
238 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
241 if (!Subtarget->hasBFI()) {
242 // fcopysign can be done in a single instruction with BFI.
243 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
244 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
247 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
249 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
250 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
251 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
253 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
254 for (MVT VT : ScalarIntVTs) {
255 setOperationAction(ISD::SREM, VT, Expand);
256 setOperationAction(ISD::SDIV, VT, Expand);
258 // GPU does not have divrem function for signed or unsigned.
259 setOperationAction(ISD::SDIVREM, VT, Custom);
260 setOperationAction(ISD::UDIVREM, VT, Custom);
262 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
263 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
264 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
266 setOperationAction(ISD::BSWAP, VT, Expand);
267 setOperationAction(ISD::CTTZ, VT, Expand);
268 setOperationAction(ISD::CTLZ, VT, Expand);
271 if (!Subtarget->hasBCNT(32))
272 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
274 if (!Subtarget->hasBCNT(64))
275 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
277 // The hardware supports 32-bit ROTR, but not ROTL.
278 setOperationAction(ISD::ROTL, MVT::i32, Expand);
279 setOperationAction(ISD::ROTL, MVT::i64, Expand);
280 setOperationAction(ISD::ROTR, MVT::i64, Expand);
282 setOperationAction(ISD::MUL, MVT::i64, Expand);
283 setOperationAction(ISD::MULHU, MVT::i64, Expand);
284 setOperationAction(ISD::MULHS, MVT::i64, Expand);
285 setOperationAction(ISD::UDIV, MVT::i32, Expand);
286 setOperationAction(ISD::UREM, MVT::i32, Expand);
287 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
288 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
289 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
290 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
291 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
293 if (!Subtarget->hasFFBH())
294 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
296 if (!Subtarget->hasFFBL())
297 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
299 static const MVT::SimpleValueType VectorIntTypes[] = {
300 MVT::v2i32, MVT::v4i32
303 for (MVT VT : VectorIntTypes) {
304 // Expand the following operations for the current type by default.
305 setOperationAction(ISD::ADD, VT, Expand);
306 setOperationAction(ISD::AND, VT, Expand);
307 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
308 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
309 setOperationAction(ISD::MUL, VT, Expand);
310 setOperationAction(ISD::OR, VT, Expand);
311 setOperationAction(ISD::SHL, VT, Expand);
312 setOperationAction(ISD::SRA, VT, Expand);
313 setOperationAction(ISD::SRL, VT, Expand);
314 setOperationAction(ISD::ROTL, VT, Expand);
315 setOperationAction(ISD::ROTR, VT, Expand);
316 setOperationAction(ISD::SUB, VT, Expand);
317 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
318 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
319 setOperationAction(ISD::SDIV, VT, Expand);
320 setOperationAction(ISD::UDIV, VT, Expand);
321 setOperationAction(ISD::SREM, VT, Expand);
322 setOperationAction(ISD::UREM, VT, Expand);
323 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
324 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
325 setOperationAction(ISD::SDIVREM, VT, Custom);
326 setOperationAction(ISD::UDIVREM, VT, Custom);
327 setOperationAction(ISD::ADDC, VT, Expand);
328 setOperationAction(ISD::SUBC, VT, Expand);
329 setOperationAction(ISD::ADDE, VT, Expand);
330 setOperationAction(ISD::SUBE, VT, Expand);
331 setOperationAction(ISD::SELECT, VT, Expand);
332 setOperationAction(ISD::VSELECT, VT, Expand);
333 setOperationAction(ISD::SELECT_CC, VT, Expand);
334 setOperationAction(ISD::XOR, VT, Expand);
335 setOperationAction(ISD::BSWAP, VT, Expand);
336 setOperationAction(ISD::CTPOP, VT, Expand);
337 setOperationAction(ISD::CTTZ, VT, Expand);
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
339 setOperationAction(ISD::CTLZ, VT, Expand);
340 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
341 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
344 static const MVT::SimpleValueType FloatVectorTypes[] = {
345 MVT::v2f32, MVT::v4f32
348 for (MVT VT : FloatVectorTypes) {
349 setOperationAction(ISD::FABS, VT, Expand);
350 setOperationAction(ISD::FADD, VT, Expand);
351 setOperationAction(ISD::FCEIL, VT, Expand);
352 setOperationAction(ISD::FCOS, VT, Expand);
353 setOperationAction(ISD::FDIV, VT, Expand);
354 setOperationAction(ISD::FEXP2, VT, Expand);
355 setOperationAction(ISD::FLOG2, VT, Expand);
356 setOperationAction(ISD::FREM, VT, Expand);
357 setOperationAction(ISD::FPOW, VT, Expand);
358 setOperationAction(ISD::FFLOOR, VT, Expand);
359 setOperationAction(ISD::FTRUNC, VT, Expand);
360 setOperationAction(ISD::FMUL, VT, Expand);
361 setOperationAction(ISD::FMA, VT, Expand);
362 setOperationAction(ISD::FRINT, VT, Expand);
363 setOperationAction(ISD::FNEARBYINT, VT, Expand);
364 setOperationAction(ISD::FSQRT, VT, Expand);
365 setOperationAction(ISD::FSIN, VT, Expand);
366 setOperationAction(ISD::FSUB, VT, Expand);
367 setOperationAction(ISD::FNEG, VT, Expand);
368 setOperationAction(ISD::SELECT, VT, Expand);
369 setOperationAction(ISD::VSELECT, VT, Expand);
370 setOperationAction(ISD::SELECT_CC, VT, Expand);
371 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
372 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
375 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
376 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
378 setTargetDAGCombine(ISD::MUL);
379 setTargetDAGCombine(ISD::SELECT_CC);
380 setTargetDAGCombine(ISD::STORE);
382 setSchedulingPreference(Sched::RegPressure);
383 setJumpIsExpensive(true);
385 // SI at least has hardware support for floating point exceptions, but no way
386 // of using or handling them is implemented. They are also optional in OpenCL
388 setHasFloatingPointExceptions(false);
390 setSelectIsExpensive(false);
391 PredictableSelectIsExpensive = false;
393 // There are no integer divide instructions, and these expand to a pretty
394 // large sequence of instructions.
395 setIntDivIsCheap(false);
396 setPow2SDivIsCheap(false);
398 // FIXME: Need to really handle these.
399 MaxStoresPerMemcpy = 4096;
400 MaxStoresPerMemmove = 4096;
401 MaxStoresPerMemset = 4096;
404 //===----------------------------------------------------------------------===//
405 // Target Information
406 //===----------------------------------------------------------------------===//
408 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
412 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
416 // The backend supports 32 and 64 bit floating point immediates.
417 // FIXME: Why are we reporting vectors of FP immediates as legal?
418 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
419 EVT ScalarVT = VT.getScalarType();
420 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
423 // We don't want to shrink f64 / f32 constants.
424 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
425 EVT ScalarVT = VT.getScalarType();
426 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
429 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
431 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
434 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
435 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
437 return ((LScalarSize <= CastScalarSize) ||
438 (CastScalarSize >= 32) ||
442 //===---------------------------------------------------------------------===//
444 //===---------------------------------------------------------------------===//
446 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
447 assert(VT.isFloatingPoint());
448 return VT == MVT::f32 || VT == MVT::f64;
451 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
452 assert(VT.isFloatingPoint());
453 return VT == MVT::f32 || VT == MVT::f64;
456 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
457 // Truncate is just accessing a subregister.
458 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
461 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
462 // Truncate is just accessing a subregister.
463 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
464 (Dest->getPrimitiveSizeInBits() % 32 == 0);
467 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
468 const DataLayout *DL = getDataLayout();
469 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
470 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
472 return SrcSize == 32 && DestSize == 64;
475 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
476 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
477 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
478 // this will enable reducing 64-bit operations the 32-bit, which is always
480 return Src == MVT::i32 && Dest == MVT::i64;
483 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
484 return isZExtFree(Val.getValueType(), VT2);
487 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
488 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
489 // limited number of native 64-bit operations. Shrinking an operation to fit
490 // in a single 32-bit register should always be helpful. As currently used,
491 // this is much less general than the name suggests, and is only used in
492 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
493 // not profitable, and may actually be harmful.
494 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
497 //===---------------------------------------------------------------------===//
498 // TargetLowering Callbacks
499 //===---------------------------------------------------------------------===//
501 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
502 const SmallVectorImpl<ISD::InputArg> &Ins) const {
504 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
507 SDValue AMDGPUTargetLowering::LowerReturn(
509 CallingConv::ID CallConv,
511 const SmallVectorImpl<ISD::OutputArg> &Outs,
512 const SmallVectorImpl<SDValue> &OutVals,
513 SDLoc DL, SelectionDAG &DAG) const {
514 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
517 //===---------------------------------------------------------------------===//
518 // Target specific lowering
519 //===---------------------------------------------------------------------===//
521 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
522 SmallVectorImpl<SDValue> &InVals) const {
523 SDValue Callee = CLI.Callee;
524 SelectionDAG &DAG = CLI.DAG;
526 const Function &Fn = *DAG.getMachineFunction().getFunction();
528 StringRef FuncName("<unknown>");
530 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
531 FuncName = G->getSymbol();
532 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
533 FuncName = G->getGlobal()->getName();
535 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
536 DAG.getContext()->diagnose(NoCalls);
540 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
541 SelectionDAG &DAG) const {
542 switch (Op.getOpcode()) {
544 Op.getNode()->dump();
545 llvm_unreachable("Custom lowering code for this"
546 "instruction is not implemented yet!");
548 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
549 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
550 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
551 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
552 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
553 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
554 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
555 case ISD::FREM: return LowerFREM(Op, DAG);
556 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
557 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
558 case ISD::FRINT: return LowerFRINT(Op, DAG);
559 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
560 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
561 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
562 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
563 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
564 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
569 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
570 SmallVectorImpl<SDValue> &Results,
571 SelectionDAG &DAG) const {
572 switch (N->getOpcode()) {
573 case ISD::SIGN_EXTEND_INREG:
574 // Different parts of legalization seem to interpret which type of
575 // sign_extend_inreg is the one to check for custom lowering. The extended
576 // from type is what really matters, but some places check for custom
577 // lowering of the result type. This results in trying to use
578 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
579 // nothing here and let the illegal result integer be handled normally.
582 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
586 Results.push_back(SDValue(Node, 0));
587 Results.push_back(SDValue(Node, 1));
588 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
590 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
594 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
595 if (Lowered.getNode())
596 Results.push_back(Lowered);
604 // FIXME: This implements accesses to initialized globals in the constant
605 // address space by copying them to private and accessing that. It does not
606 // properly handle illegal types or vectors. The private vector loads are not
607 // scalarized, and the illegal scalars hit an assertion. This technique will not
608 // work well with large initializers, and this should eventually be
609 // removed. Initialized globals should be placed into a data section that the
610 // runtime will load into a buffer before the kernel is executed. Uses of the
611 // global need to be replaced with a pointer loaded from an implicit kernel
612 // argument into this buffer holding the copy of the data, which will remove the
613 // need for any of this.
614 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
615 const GlobalValue *GV,
616 const SDValue &InitPtr,
618 SelectionDAG &DAG) const {
619 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
621 Type *InitTy = Init->getType();
623 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
624 EVT VT = EVT::getEVT(InitTy);
625 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
626 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
627 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
628 TD->getPrefTypeAlignment(InitTy));
631 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
632 EVT VT = EVT::getEVT(CFP->getType());
633 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
634 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
635 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
636 TD->getPrefTypeAlignment(CFP->getType()));
639 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
640 const StructLayout *SL = TD->getStructLayout(ST);
642 EVT PtrVT = InitPtr.getValueType();
643 SmallVector<SDValue, 8> Chains;
645 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
646 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
647 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
649 Constant *Elt = Init->getAggregateElement(I);
650 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
653 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
656 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
657 EVT PtrVT = InitPtr.getValueType();
659 unsigned NumElements;
660 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
661 NumElements = AT->getNumElements();
662 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
663 NumElements = VT->getNumElements();
665 llvm_unreachable("Unexpected type");
667 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
668 SmallVector<SDValue, 8> Chains;
669 for (unsigned i = 0; i < NumElements; ++i) {
670 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
671 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
673 Constant *Elt = Init->getAggregateElement(i);
674 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
677 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
680 if (isa<UndefValue>(Init)) {
681 EVT VT = EVT::getEVT(InitTy);
682 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
683 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
684 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
685 TD->getPrefTypeAlignment(InitTy));
689 llvm_unreachable("Unhandled constant initializer");
692 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
694 SelectionDAG &DAG) const {
696 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
697 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
698 const GlobalValue *GV = G->getGlobal();
700 switch (G->getAddressSpace()) {
701 default: llvm_unreachable("Global Address lowering not implemented for this "
703 case AMDGPUAS::LOCAL_ADDRESS: {
704 // XXX: What does the value of G->getOffset() mean?
705 assert(G->getOffset() == 0 &&
706 "Do not know what to do with an non-zero offset");
709 if (MFI->LocalMemoryObjects.count(GV) == 0) {
710 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
711 Offset = MFI->LDSSize;
712 MFI->LocalMemoryObjects[GV] = Offset;
713 // XXX: Account for alignment?
714 MFI->LDSSize += Size;
716 Offset = MFI->LocalMemoryObjects[GV];
719 return DAG.getConstant(Offset, getPointerTy(AMDGPUAS::LOCAL_ADDRESS));
721 case AMDGPUAS::CONSTANT_ADDRESS: {
722 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
723 Type *EltType = GV->getType()->getElementType();
724 unsigned Size = TD->getTypeAllocSize(EltType);
725 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
727 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
728 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
730 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
731 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
733 const GlobalVariable *Var = cast<GlobalVariable>(GV);
734 if (!Var->hasInitializer()) {
735 // This has no use, but bugpoint will hit it.
736 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
739 const Constant *Init = Var->getInitializer();
740 SmallVector<SDNode*, 8> WorkList;
742 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
743 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
744 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
746 WorkList.push_back(*I);
748 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
749 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
750 E = WorkList.end(); I != E; ++I) {
751 SmallVector<SDValue, 8> Ops;
752 Ops.push_back(Chain);
753 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
754 Ops.push_back((*I)->getOperand(i));
756 DAG.UpdateNodeOperands(*I, Ops);
758 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
763 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
764 SelectionDAG &DAG) const {
765 SmallVector<SDValue, 8> Args;
766 SDValue A = Op.getOperand(0);
767 SDValue B = Op.getOperand(1);
769 DAG.ExtractVectorElements(A, Args);
770 DAG.ExtractVectorElements(B, Args);
772 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
775 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
776 SelectionDAG &DAG) const {
778 SmallVector<SDValue, 8> Args;
779 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
780 EVT VT = Op.getValueType();
781 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
782 VT.getVectorNumElements());
784 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
787 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
788 SelectionDAG &DAG) const {
790 MachineFunction &MF = DAG.getMachineFunction();
791 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
792 getTargetMachine().getSubtargetImpl()->getFrameLowering());
794 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
796 unsigned FrameIndex = FIN->getIndex();
797 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
798 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
802 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
803 SelectionDAG &DAG) const {
804 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
806 EVT VT = Op.getValueType();
808 switch (IntrinsicID) {
810 case AMDGPUIntrinsic::AMDGPU_abs:
811 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
812 return LowerIntrinsicIABS(Op, DAG);
813 case AMDGPUIntrinsic::AMDGPU_lrp:
814 return LowerIntrinsicLRP(Op, DAG);
815 case AMDGPUIntrinsic::AMDGPU_fract:
816 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
817 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
819 case AMDGPUIntrinsic::AMDGPU_clamp:
820 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
821 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
822 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
824 case Intrinsic::AMDGPU_div_scale: {
825 // 3rd parameter required to be a constant.
826 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
828 return DAG.getUNDEF(VT);
830 // Translate to the operands expected by the machine instruction. The
831 // first parameter must be the same as the first instruction.
832 SDValue Numerator = Op.getOperand(1);
833 SDValue Denominator = Op.getOperand(2);
835 // Note this order is opposite of the machine instruction's operations,
836 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
837 // intrinsic has the numerator as the first operand to match a normal
838 // division operation.
840 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
842 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
843 Denominator, Numerator);
846 case Intrinsic::AMDGPU_div_fmas:
847 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
848 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
850 case Intrinsic::AMDGPU_div_fixup:
851 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
852 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
854 case Intrinsic::AMDGPU_trig_preop:
855 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
856 Op.getOperand(1), Op.getOperand(2));
858 case Intrinsic::AMDGPU_rcp:
859 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
861 case Intrinsic::AMDGPU_rsq:
862 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
864 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
865 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
867 case Intrinsic::AMDGPU_rsq_clamped:
868 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
870 case Intrinsic::AMDGPU_ldexp:
871 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
874 case AMDGPUIntrinsic::AMDGPU_imax:
875 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
877 case AMDGPUIntrinsic::AMDGPU_umax:
878 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
880 case AMDGPUIntrinsic::AMDGPU_imin:
881 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
883 case AMDGPUIntrinsic::AMDGPU_umin:
884 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
887 case AMDGPUIntrinsic::AMDGPU_umul24:
888 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
889 Op.getOperand(1), Op.getOperand(2));
891 case AMDGPUIntrinsic::AMDGPU_imul24:
892 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
893 Op.getOperand(1), Op.getOperand(2));
895 case AMDGPUIntrinsic::AMDGPU_umad24:
896 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
897 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
899 case AMDGPUIntrinsic::AMDGPU_imad24:
900 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
901 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
903 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
904 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
906 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
907 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
909 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
910 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
912 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
913 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
915 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
916 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
921 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
922 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
927 case AMDGPUIntrinsic::AMDGPU_bfi:
928 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
933 case AMDGPUIntrinsic::AMDGPU_bfm:
934 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
938 case AMDGPUIntrinsic::AMDGPU_brev:
939 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
941 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
942 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
944 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
945 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
946 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
947 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
951 ///IABS(a) = SMAX(sub(0, a), a)
952 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
953 SelectionDAG &DAG) const {
955 EVT VT = Op.getValueType();
956 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
959 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
962 /// Linear Interpolation
963 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
964 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
965 SelectionDAG &DAG) const {
967 EVT VT = Op.getValueType();
968 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
969 DAG.getConstantFP(1.0f, MVT::f32),
971 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
973 return DAG.getNode(ISD::FADD, DL, VT,
974 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
978 /// \brief Generate Min/Max node
979 SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
980 SelectionDAG &DAG) const {
982 EVT VT = N->getValueType(0);
984 SDValue LHS = N->getOperand(0);
985 SDValue RHS = N->getOperand(1);
986 SDValue True = N->getOperand(2);
987 SDValue False = N->getOperand(3);
988 SDValue CC = N->getOperand(4);
990 if (VT != MVT::f32 ||
991 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
995 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1004 case ISD::SETFALSE2:
1009 llvm_unreachable("Operation should already be optimised!");
1016 unsigned Opc = (LHS == True) ? AMDGPUISD::FMIN : AMDGPUISD::FMAX;
1017 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1025 unsigned Opc = (LHS == True) ? AMDGPUISD::FMAX : AMDGPUISD::FMIN;
1026 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1028 case ISD::SETCC_INVALID:
1029 llvm_unreachable("Invalid setcc condcode!");
1034 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1035 SelectionDAG &DAG) const {
1036 LoadSDNode *Load = cast<LoadSDNode>(Op);
1037 EVT MemVT = Load->getMemoryVT();
1038 EVT MemEltVT = MemVT.getVectorElementType();
1040 EVT LoadVT = Op.getValueType();
1041 EVT EltVT = LoadVT.getVectorElementType();
1042 EVT PtrVT = Load->getBasePtr().getValueType();
1044 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1045 SmallVector<SDValue, 8> Loads;
1046 SmallVector<SDValue, 8> Chains;
1049 unsigned MemEltSize = MemEltVT.getStoreSize();
1050 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1052 for (unsigned i = 0; i < NumElts; ++i) {
1053 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1054 DAG.getConstant(i * MemEltSize, PtrVT));
1057 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1058 Load->getChain(), Ptr,
1059 SrcValue.getWithOffset(i * MemEltSize),
1060 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1061 Load->isInvariant(), Load->getAlignment());
1062 Loads.push_back(NewLoad.getValue(0));
1063 Chains.push_back(NewLoad.getValue(1));
1067 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1068 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1071 return DAG.getMergeValues(Ops, SL);
1074 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1075 SelectionDAG &DAG) const {
1076 EVT VT = Op.getValueType();
1078 // If this is a 2 element vector, we really want to scalarize and not create
1079 // weird 1 element vectors.
1080 if (VT.getVectorNumElements() == 2)
1081 return ScalarizeVectorLoad(Op, DAG);
1083 LoadSDNode *Load = cast<LoadSDNode>(Op);
1084 SDValue BasePtr = Load->getBasePtr();
1085 EVT PtrVT = BasePtr.getValueType();
1086 EVT MemVT = Load->getMemoryVT();
1088 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1091 EVT LoMemVT, HiMemVT;
1094 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1095 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1096 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1098 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1099 Load->getChain(), BasePtr,
1101 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1102 Load->isInvariant(), Load->getAlignment());
1104 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1105 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1108 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1109 Load->getChain(), HiPtr,
1110 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1111 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1112 Load->isInvariant(), Load->getAlignment());
1115 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1116 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1117 LoLoad.getValue(1), HiLoad.getValue(1))
1120 return DAG.getMergeValues(Ops, SL);
1123 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1124 SelectionDAG &DAG) const {
1125 StoreSDNode *Store = cast<StoreSDNode>(Op);
1126 EVT MemVT = Store->getMemoryVT();
1127 unsigned MemBits = MemVT.getSizeInBits();
1129 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1130 // truncating store into an i32 store.
1131 // XXX: We could also handle optimize other vector bitwidths.
1132 if (!MemVT.isVector() || MemBits > 32) {
1137 SDValue Value = Store->getValue();
1138 EVT VT = Value.getValueType();
1139 EVT ElemVT = VT.getVectorElementType();
1140 SDValue Ptr = Store->getBasePtr();
1141 EVT MemEltVT = MemVT.getVectorElementType();
1142 unsigned MemEltBits = MemEltVT.getSizeInBits();
1143 unsigned MemNumElements = MemVT.getVectorNumElements();
1144 unsigned PackedSize = MemVT.getStoreSizeInBits();
1145 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1147 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1149 SDValue PackedValue;
1150 for (unsigned i = 0; i < MemNumElements; ++i) {
1151 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1152 DAG.getConstant(i, MVT::i32));
1153 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1154 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1156 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1157 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1162 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1166 if (PackedSize < 32) {
1167 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1168 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1169 Store->getMemOperand()->getPointerInfo(),
1171 Store->isNonTemporal(), Store->isVolatile(),
1172 Store->getAlignment());
1175 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1176 Store->getMemOperand()->getPointerInfo(),
1177 Store->isVolatile(), Store->isNonTemporal(),
1178 Store->getAlignment());
1181 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1182 SelectionDAG &DAG) const {
1183 StoreSDNode *Store = cast<StoreSDNode>(Op);
1184 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1185 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1186 EVT PtrVT = Store->getBasePtr().getValueType();
1187 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1190 SmallVector<SDValue, 8> Chains;
1192 unsigned EltSize = MemEltVT.getStoreSize();
1193 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1195 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1196 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1198 DAG.getConstant(i, MVT::i32));
1200 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), PtrVT);
1201 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1203 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1204 SrcValue.getWithOffset(i * EltSize),
1205 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1206 Store->getAlignment());
1207 Chains.push_back(NewStore);
1210 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1213 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1214 SelectionDAG &DAG) const {
1215 StoreSDNode *Store = cast<StoreSDNode>(Op);
1216 SDValue Val = Store->getValue();
1217 EVT VT = Val.getValueType();
1219 // If this is a 2 element vector, we really want to scalarize and not create
1220 // weird 1 element vectors.
1221 if (VT.getVectorNumElements() == 2)
1222 return ScalarizeVectorStore(Op, DAG);
1224 EVT MemVT = Store->getMemoryVT();
1225 SDValue Chain = Store->getChain();
1226 SDValue BasePtr = Store->getBasePtr();
1230 EVT LoMemVT, HiMemVT;
1233 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1234 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1235 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1237 EVT PtrVT = BasePtr.getValueType();
1238 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1239 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1241 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1243 = DAG.getTruncStore(Chain, SL, Lo,
1247 Store->isNonTemporal(),
1248 Store->isVolatile(),
1249 Store->getAlignment());
1251 = DAG.getTruncStore(Chain, SL, Hi,
1253 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1255 Store->isNonTemporal(),
1256 Store->isVolatile(),
1257 Store->getAlignment());
1259 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1263 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1265 LoadSDNode *Load = cast<LoadSDNode>(Op);
1266 ISD::LoadExtType ExtType = Load->getExtensionType();
1267 EVT VT = Op.getValueType();
1268 EVT MemVT = Load->getMemoryVT();
1270 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1271 // We can do the extload to 32-bits, and then need to separately extend to
1274 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1278 Load->getMemOperand());
1281 DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32),
1282 ExtLoad32.getValue(1)
1285 return DAG.getMergeValues(Ops, DL);
1288 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1289 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1290 // FIXME: Copied from PPC
1291 // First, load into 32 bits, then truncate to 1 bit.
1293 SDValue Chain = Load->getChain();
1294 SDValue BasePtr = Load->getBasePtr();
1295 MachineMemOperand *MMO = Load->getMemOperand();
1297 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1298 BasePtr, MVT::i8, MMO);
1301 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1305 return DAG.getMergeValues(Ops, DL);
1308 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1309 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1310 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1314 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1315 DAG.getConstant(2, MVT::i32));
1316 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1317 Load->getChain(), Ptr,
1318 DAG.getTargetConstant(0, MVT::i32),
1320 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1322 DAG.getConstant(0x3, MVT::i32));
1323 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1324 DAG.getConstant(3, MVT::i32));
1326 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1328 EVT MemEltVT = MemVT.getScalarType();
1329 if (ExtType == ISD::SEXTLOAD) {
1330 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1333 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1337 return DAG.getMergeValues(Ops, DL);
1341 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1345 return DAG.getMergeValues(Ops, DL);
1348 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1350 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1351 if (Result.getNode()) {
1355 StoreSDNode *Store = cast<StoreSDNode>(Op);
1356 SDValue Chain = Store->getChain();
1357 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1358 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1359 Store->getValue().getValueType().isVector()) {
1360 return ScalarizeVectorStore(Op, DAG);
1363 EVT MemVT = Store->getMemoryVT();
1364 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1365 MemVT.bitsLT(MVT::i32)) {
1367 if (Store->getMemoryVT() == MVT::i8) {
1369 } else if (Store->getMemoryVT() == MVT::i16) {
1372 SDValue BasePtr = Store->getBasePtr();
1373 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1374 DAG.getConstant(2, MVT::i32));
1375 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1376 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1378 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1379 DAG.getConstant(0x3, MVT::i32));
1381 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1382 DAG.getConstant(3, MVT::i32));
1384 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1387 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1389 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1390 MaskedValue, ShiftAmt);
1392 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1394 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1395 DAG.getConstant(0xffffffff, MVT::i32));
1396 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1398 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1399 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1400 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1405 // This is a shortcut for integer division because we have fast i32<->f32
1406 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1407 // float is enough to accurately represent up to a 24-bit integer.
1408 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1410 EVT VT = Op.getValueType();
1411 SDValue LHS = Op.getOperand(0);
1412 SDValue RHS = Op.getOperand(1);
1413 MVT IntVT = MVT::i32;
1414 MVT FltVT = MVT::f32;
1416 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1417 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1419 if (VT.isVector()) {
1420 unsigned NElts = VT.getVectorNumElements();
1421 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1422 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1425 unsigned BitSize = VT.getScalarType().getSizeInBits();
1427 SDValue jq = DAG.getConstant(1, IntVT);
1430 // char|short jq = ia ^ ib;
1431 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1433 // jq = jq >> (bitsize - 2)
1434 jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
1437 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));
1440 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1443 // int ia = (int)LHS;
1445 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1447 // int ib, (int)RHS;
1449 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1451 // float fa = (float)ia;
1452 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1454 // float fb = (float)ib;
1455 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1457 // float fq = native_divide(fa, fb);
1458 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1459 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1462 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1464 // float fqneg = -fq;
1465 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1467 // float fr = mad(fqneg, fb, fa);
1468 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1469 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1471 // int iq = (int)fq;
1472 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1475 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1478 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1480 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), VT);
1482 // int cv = fr >= fb;
1483 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1485 // jq = (cv ? jq : 0);
1486 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
1488 // dst = trunc/extend to legal type
1489 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1492 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1494 // Rem needs compensation, it's easier to recompute it
1495 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1496 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1502 return DAG.getMergeValues(Res, DL);
1505 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1506 SelectionDAG &DAG) const {
1508 EVT VT = Op.getValueType();
1510 SDValue Num = Op.getOperand(0);
1511 SDValue Den = Op.getOperand(1);
1513 if (VT == MVT::i32) {
1514 if (DAG.MaskedValueIsZero(Op.getOperand(0), APInt(32, 0xff << 24)) &&
1515 DAG.MaskedValueIsZero(Op.getOperand(1), APInt(32, 0xff << 24))) {
1516 // TODO: We technically could do this for i64, but shouldn't that just be
1517 // handled by something generally reducing 64-bit division on 32-bit
1518 // values to 32-bit?
1519 return LowerDIVREM24(Op, DAG, false);
1523 // RCP = URECIP(Den) = 2^32 / Den + e
1524 // e is rounding error.
1525 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1527 // RCP_LO = mul(RCP, Den) */
1528 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1530 // RCP_HI = mulhu (RCP, Den) */
1531 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1533 // NEG_RCP_LO = -RCP_LO
1534 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1537 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1538 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1541 // Calculate the rounding error from the URECIP instruction
1542 // E = mulhu(ABS_RCP_LO, RCP)
1543 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1545 // RCP_A_E = RCP + E
1546 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1548 // RCP_S_E = RCP - E
1549 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1551 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1552 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1555 // Quotient = mulhu(Tmp0, Num)
1556 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1558 // Num_S_Remainder = Quotient * Den
1559 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1561 // Remainder = Num - Num_S_Remainder
1562 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1564 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1565 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1566 DAG.getConstant(-1, VT),
1567 DAG.getConstant(0, VT),
1569 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1570 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1572 DAG.getConstant(-1, VT),
1573 DAG.getConstant(0, VT),
1575 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1576 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1579 // Calculate Division result:
1581 // Quotient_A_One = Quotient + 1
1582 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1583 DAG.getConstant(1, VT));
1585 // Quotient_S_One = Quotient - 1
1586 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1587 DAG.getConstant(1, VT));
1589 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1590 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1591 Quotient, Quotient_A_One, ISD::SETEQ);
1593 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1594 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1595 Quotient_S_One, Div, ISD::SETEQ);
1597 // Calculate Rem result:
1599 // Remainder_S_Den = Remainder - Den
1600 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1602 // Remainder_A_Den = Remainder + Den
1603 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1605 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1606 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1607 Remainder, Remainder_S_Den, ISD::SETEQ);
1609 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1610 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1611 Remainder_A_Den, Rem, ISD::SETEQ);
1616 return DAG.getMergeValues(Ops, DL);
1619 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1620 SelectionDAG &DAG) const {
1622 EVT VT = Op.getValueType();
1624 SDValue LHS = Op.getOperand(0);
1625 SDValue RHS = Op.getOperand(1);
1627 if (VT == MVT::i32) {
1628 if (DAG.ComputeNumSignBits(Op.getOperand(0)) > 8 &&
1629 DAG.ComputeNumSignBits(Op.getOperand(1)) > 8) {
1630 // TODO: We technically could do this for i64, but shouldn't that just be
1631 // handled by something generally reducing 64-bit division on 32-bit
1632 // values to 32-bit?
1633 return LowerDIVREM24(Op, DAG, true);
1637 SDValue Zero = DAG.getConstant(0, VT);
1638 SDValue NegOne = DAG.getConstant(-1, VT);
1640 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1641 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1642 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1643 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1645 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1646 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1648 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1649 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1651 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1652 SDValue Rem = Div.getValue(1);
1654 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1655 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1657 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1658 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1664 return DAG.getMergeValues(Res, DL);
1667 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1668 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1670 EVT VT = Op.getValueType();
1671 SDValue X = Op.getOperand(0);
1672 SDValue Y = Op.getOperand(1);
1674 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1675 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1676 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1678 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1681 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1683 SDValue Src = Op.getOperand(0);
1685 // result = trunc(src)
1686 // if (src > 0.0 && src != result)
1689 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1691 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1692 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1694 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1696 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1697 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1698 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1700 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1701 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1704 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1706 SDValue Src = Op.getOperand(0);
1708 assert(Op.getValueType() == MVT::f64);
1710 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1711 const SDValue One = DAG.getConstant(1, MVT::i32);
1713 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1715 // Extract the upper half, since this is where we will find the sign and
1717 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1719 const unsigned FractBits = 52;
1720 const unsigned ExpBits = 11;
1722 // Extract the exponent.
1723 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1725 DAG.getConstant(FractBits - 32, MVT::i32),
1726 DAG.getConstant(ExpBits, MVT::i32));
1727 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1728 DAG.getConstant(1023, MVT::i32));
1730 // Extract the sign bit.
1731 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1732 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1734 // Extend back to to 64-bits.
1735 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1737 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1739 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1740 const SDValue FractMask
1741 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1743 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1744 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1745 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1747 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1749 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1751 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1752 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1754 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1755 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1757 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1760 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1762 SDValue Src = Op.getOperand(0);
1764 assert(Op.getValueType() == MVT::f64);
1766 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1767 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1768 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1770 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1771 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1773 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1775 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1776 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
1778 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1779 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1781 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1784 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1785 // FNEARBYINT and FRINT are the same, except in their handling of FP
1786 // exceptions. Those aren't really meaningful for us, and OpenCL only has
1787 // rint, so just treat them as equivalent.
1788 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1791 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1793 SDValue Src = Op.getOperand(0);
1795 // result = trunc(src);
1796 // if (src < 0.0 && src != result)
1799 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1801 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1802 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
1804 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1806 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
1807 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1808 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1810 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
1811 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1814 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
1815 bool Signed) const {
1817 SDValue Src = Op.getOperand(0);
1819 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1821 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
1822 DAG.getConstant(0, MVT::i32));
1823 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
1824 DAG.getConstant(1, MVT::i32));
1826 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
1829 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
1831 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
1832 DAG.getConstant(32, MVT::i32));
1834 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
1837 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1838 SelectionDAG &DAG) const {
1839 SDValue S0 = Op.getOperand(0);
1840 if (S0.getValueType() != MVT::i64)
1843 EVT DestVT = Op.getValueType();
1844 if (DestVT == MVT::f64)
1845 return LowerINT_TO_FP64(Op, DAG, false);
1847 assert(DestVT == MVT::f32);
1851 // f32 uint_to_fp i64
1852 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1853 DAG.getConstant(0, MVT::i32));
1854 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1855 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1856 DAG.getConstant(1, MVT::i32));
1857 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1858 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1859 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1860 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1863 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
1864 SelectionDAG &DAG) const {
1865 SDValue Src = Op.getOperand(0);
1866 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
1867 return LowerINT_TO_FP64(Op, DAG, true);
1872 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
1873 bool Signed) const {
1876 SDValue Src = Op.getOperand(0);
1878 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1881 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), MVT::f64);
1883 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), MVT::f64);
1885 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
1887 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
1890 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
1892 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
1893 MVT::i32, FloorMul);
1894 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
1896 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
1898 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
1901 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
1902 SelectionDAG &DAG) const {
1903 SDValue Src = Op.getOperand(0);
1905 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
1906 return LowerFP64_TO_INT(Op, DAG, true);
1911 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
1912 SelectionDAG &DAG) const {
1913 SDValue Src = Op.getOperand(0);
1915 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
1916 return LowerFP64_TO_INT(Op, DAG, false);
1921 SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
1923 SelectionDAG &DAG) const {
1924 MVT VT = Op.getSimpleValueType();
1926 SDValue Shift = DAG.getConstant(BitsDiff, VT);
1927 // Shift left by 'Shift' bits.
1928 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
1929 // Signed shift Right by 'Shift' bits.
1930 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
1933 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1934 SelectionDAG &DAG) const {
1935 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1936 MVT VT = Op.getSimpleValueType();
1937 MVT ScalarVT = VT.getScalarType();
1942 SDValue Src = Op.getOperand(0);
1945 // TODO: Don't scalarize on Evergreen?
1946 unsigned NElts = VT.getVectorNumElements();
1947 SmallVector<SDValue, 8> Args;
1948 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1950 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1951 for (unsigned I = 0; I < NElts; ++I)
1952 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1954 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1957 //===----------------------------------------------------------------------===//
1958 // Custom DAG optimizations
1959 //===----------------------------------------------------------------------===//
1961 static bool isU24(SDValue Op, SelectionDAG &DAG) {
1962 APInt KnownZero, KnownOne;
1963 EVT VT = Op.getValueType();
1964 DAG.computeKnownBits(Op, KnownZero, KnownOne);
1966 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1969 static bool isI24(SDValue Op, SelectionDAG &DAG) {
1970 EVT VT = Op.getValueType();
1972 // In order for this to be a signed 24-bit value, bit 23, must
1974 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1975 // as unsigned 24-bit values.
1976 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1979 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
1981 SelectionDAG &DAG = DCI.DAG;
1982 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1983 EVT VT = Op.getValueType();
1985 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
1986 APInt KnownZero, KnownOne;
1987 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
1988 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
1989 DCI.CommitTargetLoweringOpt(TLO);
1992 template <typename IntTy>
1993 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
1994 uint32_t Offset, uint32_t Width) {
1995 if (Width + Offset < 32) {
1996 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
1997 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
1998 return DAG.getConstant(Result, MVT::i32);
2001 return DAG.getConstant(Src0 >> Offset, MVT::i32);
2004 static bool usesAllNormalStores(SDNode *LoadVal) {
2005 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2006 if (!ISD::isNormalStore(*I))
2013 // If we have a copy of an illegal type, replace it with a load / store of an
2014 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2015 // instructions emitted when handling extloads and truncstores. Ideally we could
2016 // recognize the pack / unpack pattern to eliminate it.
2017 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2018 DAGCombinerInfo &DCI) const {
2019 if (!DCI.isBeforeLegalize())
2022 StoreSDNode *SN = cast<StoreSDNode>(N);
2023 SDValue Value = SN->getValue();
2024 EVT VT = Value.getValueType();
2026 if (isTypeLegal(VT) || SN->isVolatile() || !ISD::isNormalLoad(Value.getNode()))
2029 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2030 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2033 EVT MemVT = LoadVal->getMemoryVT();
2036 SelectionDAG &DAG = DCI.DAG;
2037 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2039 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2041 LoadVal->getChain(),
2042 LoadVal->getBasePtr(),
2043 LoadVal->getOffset(),
2045 LoadVal->getMemOperand());
2047 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2048 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2050 return DAG.getStore(SN->getChain(), SL, NewLoad,
2051 SN->getBasePtr(), SN->getMemOperand());
2054 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2055 DAGCombinerInfo &DCI) const {
2056 EVT VT = N->getValueType(0);
2058 if (VT.isVector() || VT.getSizeInBits() > 32)
2061 SelectionDAG &DAG = DCI.DAG;
2064 SDValue N0 = N->getOperand(0);
2065 SDValue N1 = N->getOperand(1);
2068 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2069 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2070 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2071 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2072 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2073 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2074 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2075 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2080 // We need to use sext even for MUL_U24, because MUL_U24 is used
2081 // for signed multiply of 8 and 16-bit types.
2082 return DAG.getSExtOrTrunc(Mul, DL, VT);
2085 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2086 DAGCombinerInfo &DCI) const {
2087 SelectionDAG &DAG = DCI.DAG;
2090 switch(N->getOpcode()) {
2093 return performMulCombine(N, DCI);
2094 case AMDGPUISD::MUL_I24:
2095 case AMDGPUISD::MUL_U24: {
2096 SDValue N0 = N->getOperand(0);
2097 SDValue N1 = N->getOperand(1);
2098 simplifyI24(N0, DCI);
2099 simplifyI24(N1, DCI);
2102 case ISD::SELECT_CC: {
2103 return CombineMinMax(N, DAG);
2105 case AMDGPUISD::BFE_I32:
2106 case AMDGPUISD::BFE_U32: {
2107 assert(!N->getValueType(0).isVector() &&
2108 "Vector handling of BFE not implemented");
2109 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2113 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2115 return DAG.getConstant(0, MVT::i32);
2117 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2121 SDValue BitsFrom = N->getOperand(0);
2122 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2124 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2126 if (OffsetVal == 0) {
2127 // This is already sign / zero extended, so try to fold away extra BFEs.
2128 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2130 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2131 if (OpSignBits >= SignBits)
2134 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2136 // This is a sign_extend_inreg. Replace it to take advantage of existing
2137 // DAG Combines. If not eliminated, we will match back to BFE during
2140 // TODO: The sext_inreg of extended types ends, although we can could
2141 // handle them in a single BFE.
2142 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2143 DAG.getValueType(SmallVT));
2146 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2149 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2151 // Avoid undefined left shift of a negative in the constant fold.
2152 // TODO: I'm not sure what the behavior of the hardware is, this should
2153 // probably follow that instead.
2154 return constantFoldBFE<int32_t>(DAG,
2155 CVal->getSExtValue(),
2160 return constantFoldBFE<uint32_t>(DAG,
2161 CVal->getZExtValue(),
2166 APInt Demanded = APInt::getBitsSet(32,
2168 OffsetVal + WidthVal);
2170 if ((OffsetVal + WidthVal) >= 32) {
2171 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
2172 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2173 BitsFrom, ShiftVal);
2176 APInt KnownZero, KnownOne;
2177 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2178 !DCI.isBeforeLegalizeOps());
2179 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2180 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2181 TLI.SimplifyDemandedBits(BitsFrom, Demanded, KnownZero, KnownOne, TLO)) {
2182 DCI.CommitTargetLoweringOpt(TLO);
2189 return performStoreCombine(N, DCI);
2194 //===----------------------------------------------------------------------===//
2196 //===----------------------------------------------------------------------===//
2198 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2201 const SmallVectorImpl<ISD::InputArg> &Ins,
2202 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2204 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2205 if (Ins[i].ArgVT == Ins[i].VT) {
2206 OrigIns.push_back(Ins[i]);
2211 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2212 // Vector has been split into scalars.
2213 VT = Ins[i].ArgVT.getVectorElementType();
2214 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2215 Ins[i].ArgVT.getVectorElementType() !=
2216 Ins[i].VT.getVectorElementType()) {
2217 // Vector elements have been promoted
2220 // Vector has been spilt into smaller vectors.
2224 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2225 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2226 OrigIns.push_back(Arg);
2230 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2231 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2232 return CFP->isExactlyValue(1.0);
2234 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2235 return C->isAllOnesValue();
2240 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2241 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2242 return CFP->getValueAPF().isZero();
2244 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2245 return C->isNullValue();
2250 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2251 const TargetRegisterClass *RC,
2252 unsigned Reg, EVT VT) const {
2253 MachineFunction &MF = DAG.getMachineFunction();
2254 MachineRegisterInfo &MRI = MF.getRegInfo();
2255 unsigned VirtualRegister;
2256 if (!MRI.isLiveIn(Reg)) {
2257 VirtualRegister = MRI.createVirtualRegister(RC);
2258 MRI.addLiveIn(Reg, VirtualRegister);
2260 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2262 return DAG.getRegister(VirtualRegister, VT);
2265 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2267 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2269 default: return nullptr;
2271 NODE_NAME_CASE(CALL);
2272 NODE_NAME_CASE(UMUL);
2273 NODE_NAME_CASE(RET_FLAG);
2274 NODE_NAME_CASE(BRANCH_COND);
2277 NODE_NAME_CASE(DWORDADDR)
2278 NODE_NAME_CASE(FRACT)
2279 NODE_NAME_CASE(CLAMP)
2281 NODE_NAME_CASE(FMAX)
2282 NODE_NAME_CASE(SMAX)
2283 NODE_NAME_CASE(UMAX)
2284 NODE_NAME_CASE(FMIN)
2285 NODE_NAME_CASE(SMIN)
2286 NODE_NAME_CASE(UMIN)
2287 NODE_NAME_CASE(URECIP)
2288 NODE_NAME_CASE(DIV_SCALE)
2289 NODE_NAME_CASE(DIV_FMAS)
2290 NODE_NAME_CASE(DIV_FIXUP)
2291 NODE_NAME_CASE(TRIG_PREOP)
2294 NODE_NAME_CASE(RSQ_LEGACY)
2295 NODE_NAME_CASE(RSQ_CLAMPED)
2296 NODE_NAME_CASE(LDEXP)
2297 NODE_NAME_CASE(DOT4)
2298 NODE_NAME_CASE(BFE_U32)
2299 NODE_NAME_CASE(BFE_I32)
2302 NODE_NAME_CASE(BREV)
2303 NODE_NAME_CASE(MUL_U24)
2304 NODE_NAME_CASE(MUL_I24)
2305 NODE_NAME_CASE(MAD_U24)
2306 NODE_NAME_CASE(MAD_I24)
2307 NODE_NAME_CASE(EXPORT)
2308 NODE_NAME_CASE(CONST_ADDRESS)
2309 NODE_NAME_CASE(REGISTER_LOAD)
2310 NODE_NAME_CASE(REGISTER_STORE)
2311 NODE_NAME_CASE(LOAD_CONSTANT)
2312 NODE_NAME_CASE(LOAD_INPUT)
2313 NODE_NAME_CASE(SAMPLE)
2314 NODE_NAME_CASE(SAMPLEB)
2315 NODE_NAME_CASE(SAMPLED)
2316 NODE_NAME_CASE(SAMPLEL)
2317 NODE_NAME_CASE(CVT_F32_UBYTE0)
2318 NODE_NAME_CASE(CVT_F32_UBYTE1)
2319 NODE_NAME_CASE(CVT_F32_UBYTE2)
2320 NODE_NAME_CASE(CVT_F32_UBYTE3)
2321 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2322 NODE_NAME_CASE(CONST_DATA_PTR)
2323 NODE_NAME_CASE(STORE_MSKOR)
2324 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2328 static void computeKnownBitsForMinMax(const SDValue Op0,
2332 const SelectionDAG &DAG,
2334 APInt Op0Zero, Op0One;
2335 APInt Op1Zero, Op1One;
2336 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2337 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2339 KnownZero = Op0Zero & Op1Zero;
2340 KnownOne = Op0One & Op1One;
2343 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2347 const SelectionDAG &DAG,
2348 unsigned Depth) const {
2350 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2354 unsigned Opc = Op.getOpcode();
2359 case ISD::INTRINSIC_WO_CHAIN: {
2360 // FIXME: The intrinsic should just use the node.
2361 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2362 case AMDGPUIntrinsic::AMDGPU_imax:
2363 case AMDGPUIntrinsic::AMDGPU_umax:
2364 case AMDGPUIntrinsic::AMDGPU_imin:
2365 case AMDGPUIntrinsic::AMDGPU_umin:
2366 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2367 KnownZero, KnownOne, DAG, Depth);
2375 case AMDGPUISD::SMAX:
2376 case AMDGPUISD::UMAX:
2377 case AMDGPUISD::SMIN:
2378 case AMDGPUISD::UMIN:
2379 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2380 KnownZero, KnownOne, DAG, Depth);
2383 case AMDGPUISD::BFE_I32:
2384 case AMDGPUISD::BFE_U32: {
2385 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2389 unsigned BitWidth = 32;
2390 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2392 KnownZero = APInt::getAllOnesValue(BitWidth);
2393 KnownOne = APInt::getNullValue(BitWidth);
2397 // FIXME: This could do a lot more. If offset is 0, should be the same as
2398 // sign_extend_inreg implementation, but that involves duplicating it.
2399 if (Opc == AMDGPUISD::BFE_I32)
2400 KnownOne = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2402 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2409 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2411 const SelectionDAG &DAG,
2412 unsigned Depth) const {
2413 switch (Op.getOpcode()) {
2414 case AMDGPUISD::BFE_I32: {
2415 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2419 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2420 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2421 if (!Offset || !Offset->isNullValue())
2424 // TODO: Could probably figure something out with non-0 offsets.
2425 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2426 return std::max(SignBits, Op0SignBits);
2429 case AMDGPUISD::BFE_U32: {
2430 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2431 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;