1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPURegisterInfo.h"
19 #include "AMDGPUSubtarget.h"
20 #include "AMDILIntrinsicInfo.h"
21 #include "R600MachineFunctionInfo.h"
22 #include "SIMachineFunctionInfo.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/DataLayout.h"
32 #include "AMDGPUGenCallingConv.inc"
34 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
35 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
37 // Initialize target lowering borrowed from AMDIL
40 // We need to custom lower some of the intrinsics
41 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
43 // Library functions. These default to Expand, but we have instructions
45 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
46 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
47 setOperationAction(ISD::FPOW, MVT::f32, Legal);
48 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
49 setOperationAction(ISD::FABS, MVT::f32, Legal);
50 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
51 setOperationAction(ISD::FRINT, MVT::f32, Legal);
53 // The hardware supports ROTR, but not ROTL
54 setOperationAction(ISD::ROTL, MVT::i32, Expand);
56 // Lower floating point store/load to integer store/load to reduce the number
57 // of patterns in tablegen.
58 setOperationAction(ISD::STORE, MVT::f32, Promote);
59 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
61 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
62 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
64 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
65 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
67 setOperationAction(ISD::STORE, MVT::f64, Promote);
68 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
70 setOperationAction(ISD::LOAD, MVT::f32, Promote);
71 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
73 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
74 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
76 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
77 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
79 setOperationAction(ISD::LOAD, MVT::f64, Promote);
80 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
82 setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
83 setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
85 setOperationAction(ISD::MUL, MVT::i64, Expand);
87 setOperationAction(ISD::UDIV, MVT::i32, Expand);
88 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
89 setOperationAction(ISD::UREM, MVT::i32, Expand);
90 setOperationAction(ISD::VSELECT, MVT::v2f32, Expand);
91 setOperationAction(ISD::VSELECT, MVT::v4f32, Expand);
93 static const int types[] = {
97 const size_t NumTypes = array_lengthof(types);
99 for (unsigned int x = 0; x < NumTypes; ++x) {
100 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
101 //Expand the following operations for the current type by default
102 setOperationAction(ISD::ADD, VT, Expand);
103 setOperationAction(ISD::AND, VT, Expand);
104 setOperationAction(ISD::MUL, VT, Expand);
105 setOperationAction(ISD::OR, VT, Expand);
106 setOperationAction(ISD::SHL, VT, Expand);
107 setOperationAction(ISD::SRL, VT, Expand);
108 setOperationAction(ISD::SRA, VT, Expand);
109 setOperationAction(ISD::SUB, VT, Expand);
110 setOperationAction(ISD::UDIV, VT, Expand);
111 setOperationAction(ISD::UREM, VT, Expand);
112 setOperationAction(ISD::VSELECT, VT, Expand);
113 setOperationAction(ISD::XOR, VT, Expand);
117 //===---------------------------------------------------------------------===//
119 //===---------------------------------------------------------------------===//
121 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
122 assert(VT.isFloatingPoint());
123 return VT == MVT::f32;
126 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
127 assert(VT.isFloatingPoint());
128 return VT == MVT::f32;
131 //===---------------------------------------------------------------------===//
132 // TargetLowering Callbacks
133 //===---------------------------------------------------------------------===//
135 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
136 const SmallVectorImpl<ISD::InputArg> &Ins) const {
138 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
141 SDValue AMDGPUTargetLowering::LowerReturn(
143 CallingConv::ID CallConv,
145 const SmallVectorImpl<ISD::OutputArg> &Outs,
146 const SmallVectorImpl<SDValue> &OutVals,
147 SDLoc DL, SelectionDAG &DAG) const {
148 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
151 //===---------------------------------------------------------------------===//
152 // Target specific lowering
153 //===---------------------------------------------------------------------===//
155 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
157 switch (Op.getOpcode()) {
159 Op.getNode()->dump();
160 assert(0 && "Custom lowering code for this"
161 "instruction is not implemented yet!");
163 // AMDIL DAG lowering
164 case ISD::SDIV: return LowerSDIV(Op, DAG);
165 case ISD::SREM: return LowerSREM(Op, DAG);
166 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
167 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
168 // AMDGPU DAG lowering
169 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
170 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
175 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
177 SelectionDAG &DAG) const {
179 const DataLayout *TD = getTargetMachine().getDataLayout();
180 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
181 // XXX: What does the value of G->getOffset() mean?
182 assert(G->getOffset() == 0 &&
183 "Do not know what to do with an non-zero offset");
185 unsigned Offset = MFI->LDSSize;
186 const GlobalValue *GV = G->getGlobal();
187 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
189 // XXX: Account for alignment?
190 MFI->LDSSize += Size;
192 return DAG.getConstant(Offset, TD->getPointerSize() == 8 ? MVT::i64 : MVT::i32);
195 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
196 SelectionDAG &DAG) const {
197 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
199 EVT VT = Op.getValueType();
201 switch (IntrinsicID) {
203 case AMDGPUIntrinsic::AMDIL_abs:
204 return LowerIntrinsicIABS(Op, DAG);
205 case AMDGPUIntrinsic::AMDIL_exp:
206 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
207 case AMDGPUIntrinsic::AMDGPU_lrp:
208 return LowerIntrinsicLRP(Op, DAG);
209 case AMDGPUIntrinsic::AMDIL_fraction:
210 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
211 case AMDGPUIntrinsic::AMDIL_max:
212 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
214 case AMDGPUIntrinsic::AMDGPU_imax:
215 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
217 case AMDGPUIntrinsic::AMDGPU_umax:
218 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
220 case AMDGPUIntrinsic::AMDIL_min:
221 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
223 case AMDGPUIntrinsic::AMDGPU_imin:
224 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
226 case AMDGPUIntrinsic::AMDGPU_umin:
227 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
229 case AMDGPUIntrinsic::AMDIL_round_nearest:
230 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
234 ///IABS(a) = SMAX(sub(0, a), a)
235 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
236 SelectionDAG &DAG) const {
239 EVT VT = Op.getValueType();
240 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
243 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
246 /// Linear Interpolation
247 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
248 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
249 SelectionDAG &DAG) const {
251 EVT VT = Op.getValueType();
252 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
253 DAG.getConstantFP(1.0f, MVT::f32),
255 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
257 return DAG.getNode(ISD::FADD, DL, VT,
258 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
262 /// \brief Generate Min/Max node
263 SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
264 SelectionDAG &DAG) const {
266 EVT VT = Op.getValueType();
268 SDValue LHS = Op.getOperand(0);
269 SDValue RHS = Op.getOperand(1);
270 SDValue True = Op.getOperand(2);
271 SDValue False = Op.getOperand(3);
272 SDValue CC = Op.getOperand(4);
274 if (VT != MVT::f32 ||
275 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
279 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
293 assert(0 && "Operation should already be optimised !");
301 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
303 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
312 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
314 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
316 case ISD::SETCC_INVALID:
317 assert(0 && "Invalid setcc condcode !");
324 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
325 SelectionDAG &DAG) const {
327 EVT VT = Op.getValueType();
329 SDValue Num = Op.getOperand(0);
330 SDValue Den = Op.getOperand(1);
332 SmallVector<SDValue, 8> Results;
334 // RCP = URECIP(Den) = 2^32 / Den + e
335 // e is rounding error.
336 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
338 // RCP_LO = umulo(RCP, Den) */
339 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
341 // RCP_HI = mulhu (RCP, Den) */
342 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
344 // NEG_RCP_LO = -RCP_LO
345 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
348 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
349 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
352 // Calculate the rounding error from the URECIP instruction
353 // E = mulhu(ABS_RCP_LO, RCP)
354 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
357 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
360 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
362 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
363 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
366 // Quotient = mulhu(Tmp0, Num)
367 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
369 // Num_S_Remainder = Quotient * Den
370 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
372 // Remainder = Num - Num_S_Remainder
373 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
375 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
376 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
377 DAG.getConstant(-1, VT),
378 DAG.getConstant(0, VT),
380 // Remainder_GE_Zero = (Remainder >= 0 ? -1 : 0)
381 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Remainder,
382 DAG.getConstant(0, VT),
383 DAG.getConstant(-1, VT),
384 DAG.getConstant(0, VT),
386 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
387 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
390 // Calculate Division result:
392 // Quotient_A_One = Quotient + 1
393 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
394 DAG.getConstant(1, VT));
396 // Quotient_S_One = Quotient - 1
397 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
398 DAG.getConstant(1, VT));
400 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
401 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
402 Quotient, Quotient_A_One, ISD::SETEQ);
404 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
405 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
406 Quotient_S_One, Div, ISD::SETEQ);
408 // Calculate Rem result:
410 // Remainder_S_Den = Remainder - Den
411 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
413 // Remainder_A_Den = Remainder + Den
414 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
416 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
417 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
418 Remainder, Remainder_S_Den, ISD::SETEQ);
420 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
421 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
422 Remainder_A_Den, Rem, ISD::SETEQ);
426 return DAG.getMergeValues(Ops, 2, DL);
429 //===----------------------------------------------------------------------===//
431 //===----------------------------------------------------------------------===//
433 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
434 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
435 return CFP->isExactlyValue(1.0);
437 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
438 return C->isAllOnesValue();
443 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
444 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
445 return CFP->getValueAPF().isZero();
447 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
448 return C->isNullValue();
453 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
454 const TargetRegisterClass *RC,
455 unsigned Reg, EVT VT) const {
456 MachineFunction &MF = DAG.getMachineFunction();
457 MachineRegisterInfo &MRI = MF.getRegInfo();
458 unsigned VirtualRegister;
459 if (!MRI.isLiveIn(Reg)) {
460 VirtualRegister = MRI.createVirtualRegister(RC);
461 MRI.addLiveIn(Reg, VirtualRegister);
463 VirtualRegister = MRI.getLiveInVirtReg(Reg);
465 return DAG.getRegister(VirtualRegister, VT);
468 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
470 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
474 NODE_NAME_CASE(CALL);
475 NODE_NAME_CASE(UMUL);
476 NODE_NAME_CASE(DIV_INF);
477 NODE_NAME_CASE(RET_FLAG);
478 NODE_NAME_CASE(BRANCH_COND);
481 NODE_NAME_CASE(DWORDADDR)
482 NODE_NAME_CASE(FRACT)
489 NODE_NAME_CASE(URECIP)
490 NODE_NAME_CASE(EXPORT)
491 NODE_NAME_CASE(CONST_ADDRESS)
492 NODE_NAME_CASE(REGISTER_LOAD)
493 NODE_NAME_CASE(REGISTER_STORE)