1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
106 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
108 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
110 setOperationAction(ISD::Constant, MVT::i32, Legal);
111 setOperationAction(ISD::Constant, MVT::i64, Legal);
112 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
113 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
115 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
116 setOperationAction(ISD::BRIND, MVT::Other, Expand);
118 // We need to custom lower some of the intrinsics
119 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
121 // Library functions. These default to Expand, but we have instructions
123 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
124 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
125 setOperationAction(ISD::FPOW, MVT::f32, Legal);
126 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
127 setOperationAction(ISD::FABS, MVT::f32, Legal);
128 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
129 setOperationAction(ISD::FRINT, MVT::f32, Legal);
130 setOperationAction(ISD::FROUND, MVT::f32, Legal);
131 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
133 // Lower floating point store/load to integer store/load to reduce the number
134 // of patterns in tablegen.
135 setOperationAction(ISD::STORE, MVT::f32, Promote);
136 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
138 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
139 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
141 setOperationAction(ISD::STORE, MVT::i64, Promote);
142 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
144 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
145 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
147 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
148 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
150 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
153 setOperationAction(ISD::STORE, MVT::f64, Promote);
154 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
156 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
157 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
159 // Custom lowering of vector stores is required for local address space
161 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
162 // XXX: Native v2i32 local address space stores are possible, but not
163 // currently implemented.
164 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
166 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
167 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
168 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
170 // XXX: This can be change to Custom, once ExpandVectorStores can
171 // handle 64-bit stores.
172 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
174 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
175 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
176 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
177 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
178 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
181 setOperationAction(ISD::LOAD, MVT::f32, Promote);
182 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
184 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
185 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
187 setOperationAction(ISD::LOAD, MVT::i64, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
190 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
193 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
196 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
199 setOperationAction(ISD::LOAD, MVT::f64, Promote);
200 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
202 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
203 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
205 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
206 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
207 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
209 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
210 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
211 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
216 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
217 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
218 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
219 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
220 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
221 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
222 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
223 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
224 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
225 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
226 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
227 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
229 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
231 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
232 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
233 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
234 setOperationAction(ISD::FRINT, MVT::f64, Custom);
235 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
238 if (!Subtarget->hasBFI()) {
239 // fcopysign can be done in a single instruction with BFI.
240 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
241 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
244 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
246 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
247 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
248 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
250 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
251 for (MVT VT : ScalarIntVTs) {
252 setOperationAction(ISD::SREM, VT, Expand);
253 setOperationAction(ISD::SDIV, VT, Expand);
255 // GPU does not have divrem function for signed or unsigned.
256 setOperationAction(ISD::SDIVREM, VT, Custom);
257 setOperationAction(ISD::UDIVREM, VT, Custom);
259 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
260 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
261 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
263 setOperationAction(ISD::BSWAP, VT, Expand);
264 setOperationAction(ISD::CTTZ, VT, Expand);
265 setOperationAction(ISD::CTLZ, VT, Expand);
268 if (!Subtarget->hasBCNT(32))
269 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
271 if (!Subtarget->hasBCNT(64))
272 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
274 // The hardware supports 32-bit ROTR, but not ROTL.
275 setOperationAction(ISD::ROTL, MVT::i32, Expand);
276 setOperationAction(ISD::ROTL, MVT::i64, Expand);
277 setOperationAction(ISD::ROTR, MVT::i64, Expand);
279 setOperationAction(ISD::MUL, MVT::i64, Expand);
280 setOperationAction(ISD::MULHU, MVT::i64, Expand);
281 setOperationAction(ISD::MULHS, MVT::i64, Expand);
282 setOperationAction(ISD::UDIV, MVT::i32, Expand);
283 setOperationAction(ISD::UREM, MVT::i32, Expand);
284 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
285 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
287 if (!Subtarget->hasFFBH())
288 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
290 if (!Subtarget->hasFFBL())
291 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
293 static const MVT::SimpleValueType VectorIntTypes[] = {
294 MVT::v2i32, MVT::v4i32
297 for (MVT VT : VectorIntTypes) {
298 // Expand the following operations for the current type by default.
299 setOperationAction(ISD::ADD, VT, Expand);
300 setOperationAction(ISD::AND, VT, Expand);
301 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
302 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
303 setOperationAction(ISD::MUL, VT, Expand);
304 setOperationAction(ISD::OR, VT, Expand);
305 setOperationAction(ISD::SHL, VT, Expand);
306 setOperationAction(ISD::SRA, VT, Expand);
307 setOperationAction(ISD::SRL, VT, Expand);
308 setOperationAction(ISD::ROTL, VT, Expand);
309 setOperationAction(ISD::ROTR, VT, Expand);
310 setOperationAction(ISD::SUB, VT, Expand);
311 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
312 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
313 setOperationAction(ISD::SDIV, VT, Expand);
314 setOperationAction(ISD::UDIV, VT, Expand);
315 setOperationAction(ISD::SREM, VT, Expand);
316 setOperationAction(ISD::UREM, VT, Expand);
317 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
318 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
319 setOperationAction(ISD::SDIVREM, VT, Custom);
320 setOperationAction(ISD::UDIVREM, VT, Custom);
321 setOperationAction(ISD::ADDC, VT, Expand);
322 setOperationAction(ISD::SUBC, VT, Expand);
323 setOperationAction(ISD::ADDE, VT, Expand);
324 setOperationAction(ISD::SUBE, VT, Expand);
325 setOperationAction(ISD::SELECT, VT, Expand);
326 setOperationAction(ISD::VSELECT, VT, Expand);
327 setOperationAction(ISD::SELECT_CC, VT, Expand);
328 setOperationAction(ISD::XOR, VT, Expand);
329 setOperationAction(ISD::BSWAP, VT, Expand);
330 setOperationAction(ISD::CTPOP, VT, Expand);
331 setOperationAction(ISD::CTTZ, VT, Expand);
332 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
333 setOperationAction(ISD::CTLZ, VT, Expand);
334 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
335 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
338 static const MVT::SimpleValueType FloatVectorTypes[] = {
339 MVT::v2f32, MVT::v4f32
342 for (MVT VT : FloatVectorTypes) {
343 setOperationAction(ISD::FABS, VT, Expand);
344 setOperationAction(ISD::FADD, VT, Expand);
345 setOperationAction(ISD::FCEIL, VT, Expand);
346 setOperationAction(ISD::FCOS, VT, Expand);
347 setOperationAction(ISD::FDIV, VT, Expand);
348 setOperationAction(ISD::FEXP2, VT, Expand);
349 setOperationAction(ISD::FLOG2, VT, Expand);
350 setOperationAction(ISD::FPOW, VT, Expand);
351 setOperationAction(ISD::FFLOOR, VT, Expand);
352 setOperationAction(ISD::FTRUNC, VT, Expand);
353 setOperationAction(ISD::FMUL, VT, Expand);
354 setOperationAction(ISD::FMA, VT, Expand);
355 setOperationAction(ISD::FRINT, VT, Expand);
356 setOperationAction(ISD::FNEARBYINT, VT, Expand);
357 setOperationAction(ISD::FSQRT, VT, Expand);
358 setOperationAction(ISD::FSIN, VT, Expand);
359 setOperationAction(ISD::FSUB, VT, Expand);
360 setOperationAction(ISD::FNEG, VT, Expand);
361 setOperationAction(ISD::SELECT, VT, Expand);
362 setOperationAction(ISD::VSELECT, VT, Expand);
363 setOperationAction(ISD::SELECT_CC, VT, Expand);
364 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
365 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
368 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
369 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
371 setTargetDAGCombine(ISD::MUL);
372 setTargetDAGCombine(ISD::SELECT_CC);
373 setTargetDAGCombine(ISD::STORE);
375 setSchedulingPreference(Sched::RegPressure);
376 setJumpIsExpensive(true);
378 // SI at least has hardware support for floating point exceptions, but no way
379 // of using or handling them is implemented. They are also optional in OpenCL
381 setHasFloatingPointExceptions(false);
383 setSelectIsExpensive(false);
384 PredictableSelectIsExpensive = false;
386 // There are no integer divide instructions, and these expand to a pretty
387 // large sequence of instructions.
388 setIntDivIsCheap(false);
389 setPow2SDivIsCheap(false);
391 // TODO: Investigate this when 64-bit divides are implemented.
392 addBypassSlowDiv(64, 32);
394 // FIXME: Need to really handle these.
395 MaxStoresPerMemcpy = 4096;
396 MaxStoresPerMemmove = 4096;
397 MaxStoresPerMemset = 4096;
400 //===----------------------------------------------------------------------===//
401 // Target Information
402 //===----------------------------------------------------------------------===//
404 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
408 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
412 // The backend supports 32 and 64 bit floating point immediates.
413 // FIXME: Why are we reporting vectors of FP immediates as legal?
414 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
415 EVT ScalarVT = VT.getScalarType();
416 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
419 // We don't want to shrink f64 / f32 constants.
420 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
421 EVT ScalarVT = VT.getScalarType();
422 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
425 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
427 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
430 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
431 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
433 return ((LScalarSize <= CastScalarSize) ||
434 (CastScalarSize >= 32) ||
438 //===---------------------------------------------------------------------===//
440 //===---------------------------------------------------------------------===//
442 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
443 assert(VT.isFloatingPoint());
444 return VT == MVT::f32 || VT == MVT::f64;
447 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
448 assert(VT.isFloatingPoint());
449 return VT == MVT::f32 || VT == MVT::f64;
452 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
453 // Truncate is just accessing a subregister.
454 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
457 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
458 // Truncate is just accessing a subregister.
459 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
460 (Dest->getPrimitiveSizeInBits() % 32 == 0);
463 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
464 const DataLayout *DL = getDataLayout();
465 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
466 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
468 return SrcSize == 32 && DestSize == 64;
471 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
472 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
473 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
474 // this will enable reducing 64-bit operations the 32-bit, which is always
476 return Src == MVT::i32 && Dest == MVT::i64;
479 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
480 return isZExtFree(Val.getValueType(), VT2);
483 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
484 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
485 // limited number of native 64-bit operations. Shrinking an operation to fit
486 // in a single 32-bit register should always be helpful. As currently used,
487 // this is much less general than the name suggests, and is only used in
488 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
489 // not profitable, and may actually be harmful.
490 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
493 //===---------------------------------------------------------------------===//
494 // TargetLowering Callbacks
495 //===---------------------------------------------------------------------===//
497 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
498 const SmallVectorImpl<ISD::InputArg> &Ins) const {
500 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
503 SDValue AMDGPUTargetLowering::LowerReturn(
505 CallingConv::ID CallConv,
507 const SmallVectorImpl<ISD::OutputArg> &Outs,
508 const SmallVectorImpl<SDValue> &OutVals,
509 SDLoc DL, SelectionDAG &DAG) const {
510 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
513 //===---------------------------------------------------------------------===//
514 // Target specific lowering
515 //===---------------------------------------------------------------------===//
517 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
518 SmallVectorImpl<SDValue> &InVals) const {
519 SDValue Callee = CLI.Callee;
520 SelectionDAG &DAG = CLI.DAG;
522 const Function &Fn = *DAG.getMachineFunction().getFunction();
524 StringRef FuncName("<unknown>");
526 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
527 FuncName = G->getSymbol();
528 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
529 FuncName = G->getGlobal()->getName();
531 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
532 DAG.getContext()->diagnose(NoCalls);
536 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
537 SelectionDAG &DAG) const {
538 switch (Op.getOpcode()) {
540 Op.getNode()->dump();
541 llvm_unreachable("Custom lowering code for this"
542 "instruction is not implemented yet!");
544 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
545 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
546 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
547 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
548 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
549 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
550 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
551 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
552 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
553 case ISD::FRINT: return LowerFRINT(Op, DAG);
554 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
555 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
556 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
561 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
562 SmallVectorImpl<SDValue> &Results,
563 SelectionDAG &DAG) const {
564 switch (N->getOpcode()) {
565 case ISD::SIGN_EXTEND_INREG:
566 // Different parts of legalization seem to interpret which type of
567 // sign_extend_inreg is the one to check for custom lowering. The extended
568 // from type is what really matters, but some places check for custom
569 // lowering of the result type. This results in trying to use
570 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
571 // nothing here and let the illegal result integer be handled normally.
574 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
578 Results.push_back(SDValue(Node, 0));
579 Results.push_back(SDValue(Node, 1));
580 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
582 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
586 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
587 if (Lowered.getNode())
588 Results.push_back(Lowered);
596 // FIXME: This implements accesses to initialized globals in the constant
597 // address space by copying them to private and accessing that. It does not
598 // properly handle illegal types or vectors. The private vector loads are not
599 // scalarized, and the illegal scalars hit an assertion. This technique will not
600 // work well with large initializers, and this should eventually be
601 // removed. Initialized globals should be placed into a data section that the
602 // runtime will load into a buffer before the kernel is executed. Uses of the
603 // global need to be replaced with a pointer loaded from an implicit kernel
604 // argument into this buffer holding the copy of the data, which will remove the
605 // need for any of this.
606 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
607 const GlobalValue *GV,
608 const SDValue &InitPtr,
610 SelectionDAG &DAG) const {
611 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
613 Type *InitTy = Init->getType();
615 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
616 EVT VT = EVT::getEVT(InitTy);
617 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
618 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
619 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
620 TD->getPrefTypeAlignment(InitTy));
623 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
624 EVT VT = EVT::getEVT(CFP->getType());
625 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
626 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
627 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
628 TD->getPrefTypeAlignment(CFP->getType()));
631 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
632 const StructLayout *SL = TD->getStructLayout(ST);
634 EVT PtrVT = InitPtr.getValueType();
635 SmallVector<SDValue, 8> Chains;
637 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
638 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
639 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
641 Constant *Elt = Init->getAggregateElement(I);
642 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
645 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
648 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
649 EVT PtrVT = InitPtr.getValueType();
651 unsigned NumElements;
652 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
653 NumElements = AT->getNumElements();
654 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
655 NumElements = VT->getNumElements();
657 llvm_unreachable("Unexpected type");
659 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
660 SmallVector<SDValue, 8> Chains;
661 for (unsigned i = 0; i < NumElements; ++i) {
662 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
663 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
665 Constant *Elt = Init->getAggregateElement(i);
666 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
669 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
672 if (isa<UndefValue>(Init)) {
673 EVT VT = EVT::getEVT(InitTy);
674 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
675 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
676 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
677 TD->getPrefTypeAlignment(InitTy));
681 llvm_unreachable("Unhandled constant initializer");
684 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
686 SelectionDAG &DAG) const {
688 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
689 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
690 const GlobalValue *GV = G->getGlobal();
692 switch (G->getAddressSpace()) {
693 default: llvm_unreachable("Global Address lowering not implemented for this "
695 case AMDGPUAS::LOCAL_ADDRESS: {
696 // XXX: What does the value of G->getOffset() mean?
697 assert(G->getOffset() == 0 &&
698 "Do not know what to do with an non-zero offset");
701 if (MFI->LocalMemoryObjects.count(GV) == 0) {
702 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
703 Offset = MFI->LDSSize;
704 MFI->LocalMemoryObjects[GV] = Offset;
705 // XXX: Account for alignment?
706 MFI->LDSSize += Size;
708 Offset = MFI->LocalMemoryObjects[GV];
711 return DAG.getConstant(Offset, getPointerTy(AMDGPUAS::LOCAL_ADDRESS));
713 case AMDGPUAS::CONSTANT_ADDRESS: {
714 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
715 Type *EltType = GV->getType()->getElementType();
716 unsigned Size = TD->getTypeAllocSize(EltType);
717 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
719 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
720 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
722 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
723 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
725 const GlobalVariable *Var = cast<GlobalVariable>(GV);
726 if (!Var->hasInitializer()) {
727 // This has no use, but bugpoint will hit it.
728 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
731 const Constant *Init = Var->getInitializer();
732 SmallVector<SDNode*, 8> WorkList;
734 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
735 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
736 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
738 WorkList.push_back(*I);
740 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
741 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
742 E = WorkList.end(); I != E; ++I) {
743 SmallVector<SDValue, 8> Ops;
744 Ops.push_back(Chain);
745 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
746 Ops.push_back((*I)->getOperand(i));
748 DAG.UpdateNodeOperands(*I, Ops);
750 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
755 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
756 SelectionDAG &DAG) const {
757 SmallVector<SDValue, 8> Args;
758 SDValue A = Op.getOperand(0);
759 SDValue B = Op.getOperand(1);
761 DAG.ExtractVectorElements(A, Args);
762 DAG.ExtractVectorElements(B, Args);
764 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
767 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
768 SelectionDAG &DAG) const {
770 SmallVector<SDValue, 8> Args;
771 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
772 EVT VT = Op.getValueType();
773 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
774 VT.getVectorNumElements());
776 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
779 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
780 SelectionDAG &DAG) const {
782 MachineFunction &MF = DAG.getMachineFunction();
783 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
784 getTargetMachine().getSubtargetImpl()->getFrameLowering());
786 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
788 unsigned FrameIndex = FIN->getIndex();
789 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
790 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
794 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
795 SelectionDAG &DAG) const {
796 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
798 EVT VT = Op.getValueType();
800 switch (IntrinsicID) {
802 case AMDGPUIntrinsic::AMDGPU_abs:
803 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
804 return LowerIntrinsicIABS(Op, DAG);
805 case AMDGPUIntrinsic::AMDGPU_lrp:
806 return LowerIntrinsicLRP(Op, DAG);
807 case AMDGPUIntrinsic::AMDGPU_fract:
808 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
809 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
811 case AMDGPUIntrinsic::AMDGPU_clamp:
812 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
813 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
814 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
816 case Intrinsic::AMDGPU_div_scale: {
817 // 3rd parameter required to be a constant.
818 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
820 return DAG.getUNDEF(VT);
822 // Translate to the operands expected by the machine instruction. The
823 // first parameter must be the same as the first instruction.
824 SDValue Numerator = Op.getOperand(1);
825 SDValue Denominator = Op.getOperand(2);
826 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
828 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
829 Denominator, Numerator);
832 case Intrinsic::AMDGPU_div_fmas:
833 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
834 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
836 case Intrinsic::AMDGPU_div_fixup:
837 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
838 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
840 case Intrinsic::AMDGPU_trig_preop:
841 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
842 Op.getOperand(1), Op.getOperand(2));
844 case Intrinsic::AMDGPU_rcp:
845 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
847 case Intrinsic::AMDGPU_rsq:
848 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
850 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
851 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
853 case Intrinsic::AMDGPU_rsq_clamped:
854 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
856 case Intrinsic::AMDGPU_ldexp:
857 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
860 case AMDGPUIntrinsic::AMDGPU_imax:
861 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
863 case AMDGPUIntrinsic::AMDGPU_umax:
864 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
866 case AMDGPUIntrinsic::AMDGPU_imin:
867 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
869 case AMDGPUIntrinsic::AMDGPU_umin:
870 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
873 case AMDGPUIntrinsic::AMDGPU_umul24:
874 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
875 Op.getOperand(1), Op.getOperand(2));
877 case AMDGPUIntrinsic::AMDGPU_imul24:
878 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
879 Op.getOperand(1), Op.getOperand(2));
881 case AMDGPUIntrinsic::AMDGPU_umad24:
882 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
883 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
885 case AMDGPUIntrinsic::AMDGPU_imad24:
886 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
887 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
889 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
890 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
892 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
893 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
895 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
896 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
898 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
899 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
901 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
902 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
907 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
908 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
913 case AMDGPUIntrinsic::AMDGPU_bfi:
914 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
919 case AMDGPUIntrinsic::AMDGPU_bfm:
920 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
924 case AMDGPUIntrinsic::AMDGPU_brev:
925 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
927 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
928 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
930 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
931 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
932 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
933 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
937 ///IABS(a) = SMAX(sub(0, a), a)
938 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
939 SelectionDAG &DAG) const {
941 EVT VT = Op.getValueType();
942 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
945 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
948 /// Linear Interpolation
949 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
950 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
951 SelectionDAG &DAG) const {
953 EVT VT = Op.getValueType();
954 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
955 DAG.getConstantFP(1.0f, MVT::f32),
957 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
959 return DAG.getNode(ISD::FADD, DL, VT,
960 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
964 /// \brief Generate Min/Max node
965 SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
966 SelectionDAG &DAG) const {
968 EVT VT = N->getValueType(0);
970 SDValue LHS = N->getOperand(0);
971 SDValue RHS = N->getOperand(1);
972 SDValue True = N->getOperand(2);
973 SDValue False = N->getOperand(3);
974 SDValue CC = N->getOperand(4);
976 if (VT != MVT::f32 ||
977 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
981 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
995 llvm_unreachable("Operation should already be optimised!");
1002 unsigned Opc = (LHS == True) ? AMDGPUISD::FMIN : AMDGPUISD::FMAX;
1003 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1011 unsigned Opc = (LHS == True) ? AMDGPUISD::FMAX : AMDGPUISD::FMIN;
1012 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1014 case ISD::SETCC_INVALID:
1015 llvm_unreachable("Invalid setcc condcode!");
1020 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1021 SelectionDAG &DAG) const {
1022 LoadSDNode *Load = cast<LoadSDNode>(Op);
1023 EVT MemVT = Load->getMemoryVT();
1024 EVT MemEltVT = MemVT.getVectorElementType();
1026 EVT LoadVT = Op.getValueType();
1027 EVT EltVT = LoadVT.getVectorElementType();
1028 EVT PtrVT = Load->getBasePtr().getValueType();
1030 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1031 SmallVector<SDValue, 8> Loads;
1032 SmallVector<SDValue, 8> Chains;
1035 unsigned MemEltSize = MemEltVT.getStoreSize();
1036 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1038 for (unsigned i = 0; i < NumElts; ++i) {
1039 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1040 DAG.getConstant(i * MemEltSize, PtrVT));
1043 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1044 Load->getChain(), Ptr,
1045 SrcValue.getWithOffset(i * MemEltSize),
1046 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1047 Load->isInvariant(), Load->getAlignment());
1048 Loads.push_back(NewLoad.getValue(0));
1049 Chains.push_back(NewLoad.getValue(1));
1053 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1054 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1057 return DAG.getMergeValues(Ops, SL);
1060 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1061 SelectionDAG &DAG) const {
1062 EVT VT = Op.getValueType();
1064 // If this is a 2 element vector, we really want to scalarize and not create
1065 // weird 1 element vectors.
1066 if (VT.getVectorNumElements() == 2)
1067 return ScalarizeVectorLoad(Op, DAG);
1069 LoadSDNode *Load = cast<LoadSDNode>(Op);
1070 SDValue BasePtr = Load->getBasePtr();
1071 EVT PtrVT = BasePtr.getValueType();
1072 EVT MemVT = Load->getMemoryVT();
1074 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1077 EVT LoMemVT, HiMemVT;
1080 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1081 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1082 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1084 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1085 Load->getChain(), BasePtr,
1087 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1088 Load->isInvariant(), Load->getAlignment());
1090 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1091 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1094 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1095 Load->getChain(), HiPtr,
1096 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1097 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1098 Load->isInvariant(), Load->getAlignment());
1101 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1102 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1103 LoLoad.getValue(1), HiLoad.getValue(1))
1106 return DAG.getMergeValues(Ops, SL);
1109 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1110 SelectionDAG &DAG) const {
1111 StoreSDNode *Store = cast<StoreSDNode>(Op);
1112 EVT MemVT = Store->getMemoryVT();
1113 unsigned MemBits = MemVT.getSizeInBits();
1115 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1116 // truncating store into an i32 store.
1117 // XXX: We could also handle optimize other vector bitwidths.
1118 if (!MemVT.isVector() || MemBits > 32) {
1123 SDValue Value = Store->getValue();
1124 EVT VT = Value.getValueType();
1125 EVT ElemVT = VT.getVectorElementType();
1126 SDValue Ptr = Store->getBasePtr();
1127 EVT MemEltVT = MemVT.getVectorElementType();
1128 unsigned MemEltBits = MemEltVT.getSizeInBits();
1129 unsigned MemNumElements = MemVT.getVectorNumElements();
1130 unsigned PackedSize = MemVT.getStoreSizeInBits();
1131 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1133 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1135 SDValue PackedValue;
1136 for (unsigned i = 0; i < MemNumElements; ++i) {
1137 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1138 DAG.getConstant(i, MVT::i32));
1139 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1140 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1142 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1143 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1148 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1152 if (PackedSize < 32) {
1153 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1154 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1155 Store->getMemOperand()->getPointerInfo(),
1157 Store->isNonTemporal(), Store->isVolatile(),
1158 Store->getAlignment());
1161 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1162 Store->getMemOperand()->getPointerInfo(),
1163 Store->isVolatile(), Store->isNonTemporal(),
1164 Store->getAlignment());
1167 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1168 SelectionDAG &DAG) const {
1169 StoreSDNode *Store = cast<StoreSDNode>(Op);
1170 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1171 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1172 EVT PtrVT = Store->getBasePtr().getValueType();
1173 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1176 SmallVector<SDValue, 8> Chains;
1178 unsigned EltSize = MemEltVT.getStoreSize();
1179 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1181 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1182 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1184 DAG.getConstant(i, MVT::i32));
1186 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), PtrVT);
1187 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1189 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1190 SrcValue.getWithOffset(i * EltSize),
1191 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1192 Store->getAlignment());
1193 Chains.push_back(NewStore);
1196 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1199 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1200 SelectionDAG &DAG) const {
1201 StoreSDNode *Store = cast<StoreSDNode>(Op);
1202 SDValue Val = Store->getValue();
1203 EVT VT = Val.getValueType();
1205 // If this is a 2 element vector, we really want to scalarize and not create
1206 // weird 1 element vectors.
1207 if (VT.getVectorNumElements() == 2)
1208 return ScalarizeVectorStore(Op, DAG);
1210 EVT MemVT = Store->getMemoryVT();
1211 SDValue Chain = Store->getChain();
1212 SDValue BasePtr = Store->getBasePtr();
1216 EVT LoMemVT, HiMemVT;
1219 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1220 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1221 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1223 EVT PtrVT = BasePtr.getValueType();
1224 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1225 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1227 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1229 = DAG.getTruncStore(Chain, SL, Lo,
1233 Store->isNonTemporal(),
1234 Store->isVolatile(),
1235 Store->getAlignment());
1237 = DAG.getTruncStore(Chain, SL, Hi,
1239 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1241 Store->isNonTemporal(),
1242 Store->isVolatile(),
1243 Store->getAlignment());
1245 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1249 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1251 LoadSDNode *Load = cast<LoadSDNode>(Op);
1252 ISD::LoadExtType ExtType = Load->getExtensionType();
1253 EVT VT = Op.getValueType();
1254 EVT MemVT = Load->getMemoryVT();
1256 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1257 // We can do the extload to 32-bits, and then need to separately extend to
1260 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1264 Load->getMemOperand());
1267 DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32),
1268 ExtLoad32.getValue(1)
1271 return DAG.getMergeValues(Ops, DL);
1274 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1275 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1276 // FIXME: Copied from PPC
1277 // First, load into 32 bits, then truncate to 1 bit.
1279 SDValue Chain = Load->getChain();
1280 SDValue BasePtr = Load->getBasePtr();
1281 MachineMemOperand *MMO = Load->getMemOperand();
1283 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1284 BasePtr, MVT::i8, MMO);
1287 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1291 return DAG.getMergeValues(Ops, DL);
1294 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1295 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1296 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1300 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1301 DAG.getConstant(2, MVT::i32));
1302 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1303 Load->getChain(), Ptr,
1304 DAG.getTargetConstant(0, MVT::i32),
1306 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1308 DAG.getConstant(0x3, MVT::i32));
1309 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1310 DAG.getConstant(3, MVT::i32));
1312 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1314 EVT MemEltVT = MemVT.getScalarType();
1315 if (ExtType == ISD::SEXTLOAD) {
1316 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1319 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1323 return DAG.getMergeValues(Ops, DL);
1327 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1331 return DAG.getMergeValues(Ops, DL);
1334 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1336 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1337 if (Result.getNode()) {
1341 StoreSDNode *Store = cast<StoreSDNode>(Op);
1342 SDValue Chain = Store->getChain();
1343 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1344 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1345 Store->getValue().getValueType().isVector()) {
1346 return ScalarizeVectorStore(Op, DAG);
1349 EVT MemVT = Store->getMemoryVT();
1350 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1351 MemVT.bitsLT(MVT::i32)) {
1353 if (Store->getMemoryVT() == MVT::i8) {
1355 } else if (Store->getMemoryVT() == MVT::i16) {
1358 SDValue BasePtr = Store->getBasePtr();
1359 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1360 DAG.getConstant(2, MVT::i32));
1361 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1362 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1364 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1365 DAG.getConstant(0x3, MVT::i32));
1367 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1368 DAG.getConstant(3, MVT::i32));
1370 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1373 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1375 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1376 MaskedValue, ShiftAmt);
1378 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1380 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1381 DAG.getConstant(0xffffffff, MVT::i32));
1382 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1384 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1385 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1386 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1391 // This is a shortcut for integer division because we have fast i32<->f32
1392 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1393 // float is enough to accurately represent up to a 24-bit integer.
1394 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1396 EVT VT = Op.getValueType();
1397 SDValue LHS = Op.getOperand(0);
1398 SDValue RHS = Op.getOperand(1);
1399 MVT IntVT = MVT::i32;
1400 MVT FltVT = MVT::f32;
1402 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1403 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1405 if (VT.isVector()) {
1406 unsigned NElts = VT.getVectorNumElements();
1407 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1408 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1411 unsigned BitSize = VT.getScalarType().getSizeInBits();
1413 SDValue jq = DAG.getConstant(1, IntVT);
1416 // char|short jq = ia ^ ib;
1417 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1419 // jq = jq >> (bitsize - 2)
1420 jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
1423 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));
1426 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1429 // int ia = (int)LHS;
1431 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1433 // int ib, (int)RHS;
1435 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1437 // float fa = (float)ia;
1438 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1440 // float fb = (float)ib;
1441 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1443 // float fq = native_divide(fa, fb);
1444 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1445 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1448 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1450 // float fqneg = -fq;
1451 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1453 // float fr = mad(fqneg, fb, fa);
1454 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1455 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1457 // int iq = (int)fq;
1458 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1461 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1464 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1466 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), VT);
1468 // int cv = fr >= fb;
1469 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1471 // jq = (cv ? jq : 0);
1472 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
1474 // dst = trunc/extend to legal type
1475 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1478 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1480 // Rem needs compensation, it's easier to recompute it
1481 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1482 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1488 return DAG.getMergeValues(Res, DL);
1491 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1492 SelectionDAG &DAG) const {
1494 EVT VT = Op.getValueType();
1496 SDValue Num = Op.getOperand(0);
1497 SDValue Den = Op.getOperand(1);
1499 if (VT == MVT::i32) {
1500 if (DAG.MaskedValueIsZero(Op.getOperand(0), APInt(32, 0xff << 24)) &&
1501 DAG.MaskedValueIsZero(Op.getOperand(1), APInt(32, 0xff << 24))) {
1502 // TODO: We technically could do this for i64, but shouldn't that just be
1503 // handled by something generally reducing 64-bit division on 32-bit
1504 // values to 32-bit?
1505 return LowerDIVREM24(Op, DAG, false);
1509 // RCP = URECIP(Den) = 2^32 / Den + e
1510 // e is rounding error.
1511 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1513 // RCP_LO = umulo(RCP, Den) */
1514 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
1516 // RCP_HI = mulhu (RCP, Den) */
1517 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1519 // NEG_RCP_LO = -RCP_LO
1520 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1523 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1524 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1527 // Calculate the rounding error from the URECIP instruction
1528 // E = mulhu(ABS_RCP_LO, RCP)
1529 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1531 // RCP_A_E = RCP + E
1532 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1534 // RCP_S_E = RCP - E
1535 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1537 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1538 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1541 // Quotient = mulhu(Tmp0, Num)
1542 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1544 // Num_S_Remainder = Quotient * Den
1545 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
1547 // Remainder = Num - Num_S_Remainder
1548 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1550 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1551 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1552 DAG.getConstant(-1, VT),
1553 DAG.getConstant(0, VT),
1555 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1556 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1558 DAG.getConstant(-1, VT),
1559 DAG.getConstant(0, VT),
1561 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1562 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1565 // Calculate Division result:
1567 // Quotient_A_One = Quotient + 1
1568 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1569 DAG.getConstant(1, VT));
1571 // Quotient_S_One = Quotient - 1
1572 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1573 DAG.getConstant(1, VT));
1575 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1576 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1577 Quotient, Quotient_A_One, ISD::SETEQ);
1579 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1580 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1581 Quotient_S_One, Div, ISD::SETEQ);
1583 // Calculate Rem result:
1585 // Remainder_S_Den = Remainder - Den
1586 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1588 // Remainder_A_Den = Remainder + Den
1589 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1591 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1592 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1593 Remainder, Remainder_S_Den, ISD::SETEQ);
1595 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1596 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1597 Remainder_A_Den, Rem, ISD::SETEQ);
1602 return DAG.getMergeValues(Ops, DL);
1605 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1606 SelectionDAG &DAG) const {
1608 EVT VT = Op.getValueType();
1610 SDValue LHS = Op.getOperand(0);
1611 SDValue RHS = Op.getOperand(1);
1613 if (VT == MVT::i32) {
1614 if (DAG.ComputeNumSignBits(Op.getOperand(0)) > 8 &&
1615 DAG.ComputeNumSignBits(Op.getOperand(1)) > 8) {
1616 // TODO: We technically could do this for i64, but shouldn't that just be
1617 // handled by something generally reducing 64-bit division on 32-bit
1618 // values to 32-bit?
1619 return LowerDIVREM24(Op, DAG, true);
1623 SDValue Zero = DAG.getConstant(0, VT);
1624 SDValue NegOne = DAG.getConstant(-1, VT);
1626 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1627 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1628 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1629 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1631 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1632 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1634 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1635 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1637 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1638 SDValue Rem = Div.getValue(1);
1640 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1641 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1643 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1644 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1650 return DAG.getMergeValues(Res, DL);
1653 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1655 SDValue Src = Op.getOperand(0);
1657 // result = trunc(src)
1658 // if (src > 0.0 && src != result)
1661 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1663 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1664 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1666 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1668 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1669 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1670 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1672 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1673 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1676 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1678 SDValue Src = Op.getOperand(0);
1680 assert(Op.getValueType() == MVT::f64);
1682 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1683 const SDValue One = DAG.getConstant(1, MVT::i32);
1685 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1687 // Extract the upper half, since this is where we will find the sign and
1689 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1691 const unsigned FractBits = 52;
1692 const unsigned ExpBits = 11;
1694 // Extract the exponent.
1695 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_I32, SL, MVT::i32,
1697 DAG.getConstant(FractBits - 32, MVT::i32),
1698 DAG.getConstant(ExpBits, MVT::i32));
1699 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1700 DAG.getConstant(1023, MVT::i32));
1702 // Extract the sign bit.
1703 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1704 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1706 // Extend back to to 64-bits.
1707 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1709 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1711 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1712 const SDValue FractMask
1713 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1715 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1716 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1717 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1719 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1721 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1723 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1724 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1726 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1727 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1729 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1732 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1734 SDValue Src = Op.getOperand(0);
1736 assert(Op.getValueType() == MVT::f64);
1738 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1739 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1740 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1742 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1743 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1745 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1747 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1748 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
1750 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1751 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1753 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1756 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1757 // FNEARBYINT and FRINT are the same, except in their handling of FP
1758 // exceptions. Those aren't really meaningful for us, and OpenCL only has
1759 // rint, so just treat them as equivalent.
1760 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1763 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1765 SDValue Src = Op.getOperand(0);
1767 // result = trunc(src);
1768 // if (src < 0.0 && src != result)
1771 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1773 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1774 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
1776 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1778 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
1779 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1780 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1782 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
1783 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1786 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1787 SelectionDAG &DAG) const {
1788 SDValue S0 = Op.getOperand(0);
1790 if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64)
1793 // f32 uint_to_fp i64
1794 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1795 DAG.getConstant(0, MVT::i32));
1796 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1797 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1798 DAG.getConstant(1, MVT::i32));
1799 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1800 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1801 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1802 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1805 SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
1807 SelectionDAG &DAG) const {
1808 MVT VT = Op.getSimpleValueType();
1810 SDValue Shift = DAG.getConstant(BitsDiff, VT);
1811 // Shift left by 'Shift' bits.
1812 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
1813 // Signed shift Right by 'Shift' bits.
1814 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
1817 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1818 SelectionDAG &DAG) const {
1819 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1820 MVT VT = Op.getSimpleValueType();
1821 MVT ScalarVT = VT.getScalarType();
1826 SDValue Src = Op.getOperand(0);
1829 // TODO: Don't scalarize on Evergreen?
1830 unsigned NElts = VT.getVectorNumElements();
1831 SmallVector<SDValue, 8> Args;
1832 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1834 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1835 for (unsigned I = 0; I < NElts; ++I)
1836 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1838 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1841 //===----------------------------------------------------------------------===//
1842 // Custom DAG optimizations
1843 //===----------------------------------------------------------------------===//
1845 static bool isU24(SDValue Op, SelectionDAG &DAG) {
1846 APInt KnownZero, KnownOne;
1847 EVT VT = Op.getValueType();
1848 DAG.computeKnownBits(Op, KnownZero, KnownOne);
1850 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1853 static bool isI24(SDValue Op, SelectionDAG &DAG) {
1854 EVT VT = Op.getValueType();
1856 // In order for this to be a signed 24-bit value, bit 23, must
1858 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1859 // as unsigned 24-bit values.
1860 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1863 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
1865 SelectionDAG &DAG = DCI.DAG;
1866 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1867 EVT VT = Op.getValueType();
1869 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
1870 APInt KnownZero, KnownOne;
1871 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
1872 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
1873 DCI.CommitTargetLoweringOpt(TLO);
1876 template <typename IntTy>
1877 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
1878 uint32_t Offset, uint32_t Width) {
1879 if (Width + Offset < 32) {
1880 IntTy Result = (Src0 << (32 - Offset - Width)) >> (32 - Width);
1881 return DAG.getConstant(Result, MVT::i32);
1884 return DAG.getConstant(Src0 >> Offset, MVT::i32);
1887 static bool usesAllNormalStores(SDNode *LoadVal) {
1888 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
1889 if (!ISD::isNormalStore(*I))
1896 // If we have a copy of an illegal type, replace it with a load / store of an
1897 // equivalently sized legal type. This avoids intermediate bit pack / unpack
1898 // instructions emitted when handling extloads and truncstores. Ideally we could
1899 // recognize the pack / unpack pattern to eliminate it.
1900 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
1901 DAGCombinerInfo &DCI) const {
1902 if (!DCI.isBeforeLegalize())
1905 StoreSDNode *SN = cast<StoreSDNode>(N);
1906 SDValue Value = SN->getValue();
1907 EVT VT = Value.getValueType();
1909 if (isTypeLegal(VT) || SN->isVolatile() || !ISD::isNormalLoad(Value.getNode()))
1912 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
1913 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
1916 EVT MemVT = LoadVal->getMemoryVT();
1919 SelectionDAG &DAG = DCI.DAG;
1920 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
1922 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
1924 LoadVal->getChain(),
1925 LoadVal->getBasePtr(),
1926 LoadVal->getOffset(),
1928 LoadVal->getMemOperand());
1930 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
1931 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
1933 return DAG.getStore(SN->getChain(), SL, NewLoad,
1934 SN->getBasePtr(), SN->getMemOperand());
1937 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
1938 DAGCombinerInfo &DCI) const {
1939 EVT VT = N->getValueType(0);
1941 if (VT.isVector() || VT.getSizeInBits() > 32)
1944 SelectionDAG &DAG = DCI.DAG;
1947 SDValue N0 = N->getOperand(0);
1948 SDValue N1 = N->getOperand(1);
1951 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
1952 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
1953 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
1954 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
1955 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
1956 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
1957 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
1958 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
1963 // We need to use sext even for MUL_U24, because MUL_U24 is used
1964 // for signed multiply of 8 and 16-bit types.
1965 return DAG.getSExtOrTrunc(Mul, DL, VT);
1968 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
1969 DAGCombinerInfo &DCI) const {
1970 SelectionDAG &DAG = DCI.DAG;
1973 switch(N->getOpcode()) {
1976 return performMulCombine(N, DCI);
1977 case AMDGPUISD::MUL_I24:
1978 case AMDGPUISD::MUL_U24: {
1979 SDValue N0 = N->getOperand(0);
1980 SDValue N1 = N->getOperand(1);
1981 simplifyI24(N0, DCI);
1982 simplifyI24(N1, DCI);
1985 case ISD::SELECT_CC: {
1986 return CombineMinMax(N, DAG);
1988 case AMDGPUISD::BFE_I32:
1989 case AMDGPUISD::BFE_U32: {
1990 assert(!N->getValueType(0).isVector() &&
1991 "Vector handling of BFE not implemented");
1992 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
1996 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
1998 return DAG.getConstant(0, MVT::i32);
2000 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2004 SDValue BitsFrom = N->getOperand(0);
2005 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2007 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2009 if (OffsetVal == 0) {
2010 // This is already sign / zero extended, so try to fold away extra BFEs.
2011 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2013 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2014 if (OpSignBits >= SignBits)
2017 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2019 // This is a sign_extend_inreg. Replace it to take advantage of existing
2020 // DAG Combines. If not eliminated, we will match back to BFE during
2023 // TODO: The sext_inreg of extended types ends, although we can could
2024 // handle them in a single BFE.
2025 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2026 DAG.getValueType(SmallVT));
2029 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2032 if (ConstantSDNode *Val = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2034 return constantFoldBFE<int32_t>(DAG,
2035 Val->getSExtValue(),
2040 return constantFoldBFE<uint32_t>(DAG,
2041 Val->getZExtValue(),
2046 APInt Demanded = APInt::getBitsSet(32,
2048 OffsetVal + WidthVal);
2050 if ((OffsetVal + WidthVal) >= 32) {
2051 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
2052 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2053 BitsFrom, ShiftVal);
2056 APInt KnownZero, KnownOne;
2057 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2058 !DCI.isBeforeLegalizeOps());
2059 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2060 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2061 TLI.SimplifyDemandedBits(BitsFrom, Demanded, KnownZero, KnownOne, TLO)) {
2062 DCI.CommitTargetLoweringOpt(TLO);
2069 return performStoreCombine(N, DCI);
2074 //===----------------------------------------------------------------------===//
2076 //===----------------------------------------------------------------------===//
2078 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2081 const SmallVectorImpl<ISD::InputArg> &Ins,
2082 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2084 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2085 if (Ins[i].ArgVT == Ins[i].VT) {
2086 OrigIns.push_back(Ins[i]);
2091 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2092 // Vector has been split into scalars.
2093 VT = Ins[i].ArgVT.getVectorElementType();
2094 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2095 Ins[i].ArgVT.getVectorElementType() !=
2096 Ins[i].VT.getVectorElementType()) {
2097 // Vector elements have been promoted
2100 // Vector has been spilt into smaller vectors.
2104 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2105 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2106 OrigIns.push_back(Arg);
2110 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2111 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2112 return CFP->isExactlyValue(1.0);
2114 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2115 return C->isAllOnesValue();
2120 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2121 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2122 return CFP->getValueAPF().isZero();
2124 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2125 return C->isNullValue();
2130 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2131 const TargetRegisterClass *RC,
2132 unsigned Reg, EVT VT) const {
2133 MachineFunction &MF = DAG.getMachineFunction();
2134 MachineRegisterInfo &MRI = MF.getRegInfo();
2135 unsigned VirtualRegister;
2136 if (!MRI.isLiveIn(Reg)) {
2137 VirtualRegister = MRI.createVirtualRegister(RC);
2138 MRI.addLiveIn(Reg, VirtualRegister);
2140 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2142 return DAG.getRegister(VirtualRegister, VT);
2145 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2147 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2149 default: return nullptr;
2151 NODE_NAME_CASE(CALL);
2152 NODE_NAME_CASE(UMUL);
2153 NODE_NAME_CASE(RET_FLAG);
2154 NODE_NAME_CASE(BRANCH_COND);
2157 NODE_NAME_CASE(DWORDADDR)
2158 NODE_NAME_CASE(FRACT)
2159 NODE_NAME_CASE(CLAMP)
2161 NODE_NAME_CASE(FMAX)
2162 NODE_NAME_CASE(SMAX)
2163 NODE_NAME_CASE(UMAX)
2164 NODE_NAME_CASE(FMIN)
2165 NODE_NAME_CASE(SMIN)
2166 NODE_NAME_CASE(UMIN)
2167 NODE_NAME_CASE(URECIP)
2168 NODE_NAME_CASE(DIV_SCALE)
2169 NODE_NAME_CASE(DIV_FMAS)
2170 NODE_NAME_CASE(DIV_FIXUP)
2171 NODE_NAME_CASE(TRIG_PREOP)
2174 NODE_NAME_CASE(RSQ_LEGACY)
2175 NODE_NAME_CASE(RSQ_CLAMPED)
2176 NODE_NAME_CASE(LDEXP)
2177 NODE_NAME_CASE(DOT4)
2178 NODE_NAME_CASE(BFE_U32)
2179 NODE_NAME_CASE(BFE_I32)
2182 NODE_NAME_CASE(BREV)
2183 NODE_NAME_CASE(MUL_U24)
2184 NODE_NAME_CASE(MUL_I24)
2185 NODE_NAME_CASE(MAD_U24)
2186 NODE_NAME_CASE(MAD_I24)
2187 NODE_NAME_CASE(EXPORT)
2188 NODE_NAME_CASE(CONST_ADDRESS)
2189 NODE_NAME_CASE(REGISTER_LOAD)
2190 NODE_NAME_CASE(REGISTER_STORE)
2191 NODE_NAME_CASE(LOAD_CONSTANT)
2192 NODE_NAME_CASE(LOAD_INPUT)
2193 NODE_NAME_CASE(SAMPLE)
2194 NODE_NAME_CASE(SAMPLEB)
2195 NODE_NAME_CASE(SAMPLED)
2196 NODE_NAME_CASE(SAMPLEL)
2197 NODE_NAME_CASE(CVT_F32_UBYTE0)
2198 NODE_NAME_CASE(CVT_F32_UBYTE1)
2199 NODE_NAME_CASE(CVT_F32_UBYTE2)
2200 NODE_NAME_CASE(CVT_F32_UBYTE3)
2201 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2202 NODE_NAME_CASE(CONST_DATA_PTR)
2203 NODE_NAME_CASE(STORE_MSKOR)
2204 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2208 static void computeKnownBitsForMinMax(const SDValue Op0,
2212 const SelectionDAG &DAG,
2214 APInt Op0Zero, Op0One;
2215 APInt Op1Zero, Op1One;
2216 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2217 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2219 KnownZero = Op0Zero & Op1Zero;
2220 KnownOne = Op0One & Op1One;
2223 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2227 const SelectionDAG &DAG,
2228 unsigned Depth) const {
2230 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2234 unsigned Opc = Op.getOpcode();
2239 case ISD::INTRINSIC_WO_CHAIN: {
2240 // FIXME: The intrinsic should just use the node.
2241 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2242 case AMDGPUIntrinsic::AMDGPU_imax:
2243 case AMDGPUIntrinsic::AMDGPU_umax:
2244 case AMDGPUIntrinsic::AMDGPU_imin:
2245 case AMDGPUIntrinsic::AMDGPU_umin:
2246 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2247 KnownZero, KnownOne, DAG, Depth);
2255 case AMDGPUISD::SMAX:
2256 case AMDGPUISD::UMAX:
2257 case AMDGPUISD::SMIN:
2258 case AMDGPUISD::UMIN:
2259 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2260 KnownZero, KnownOne, DAG, Depth);
2263 case AMDGPUISD::BFE_I32:
2264 case AMDGPUISD::BFE_U32: {
2265 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2269 unsigned BitWidth = 32;
2270 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2272 KnownZero = APInt::getAllOnesValue(BitWidth);
2273 KnownOne = APInt::getNullValue(BitWidth);
2277 // FIXME: This could do a lot more. If offset is 0, should be the same as
2278 // sign_extend_inreg implementation, but that involves duplicating it.
2279 if (Opc == AMDGPUISD::BFE_I32)
2280 KnownOne = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2282 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2289 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2291 const SelectionDAG &DAG,
2292 unsigned Depth) const {
2293 switch (Op.getOpcode()) {
2294 case AMDGPUISD::BFE_I32: {
2295 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2299 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2300 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2301 if (!Offset || !Offset->isNullValue())
2304 // TODO: Could probably figure something out with non-0 offsets.
2305 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2306 return std::max(SignBits, Op0SignBits);
2309 case AMDGPUISD::BFE_U32: {
2310 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2311 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;