1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
106 const AMDGPUSubtarget &STI)
107 : TargetLowering(TM), Subtarget(&STI) {
108 setOperationAction(ISD::Constant, MVT::i32, Legal);
109 setOperationAction(ISD::Constant, MVT::i64, Legal);
110 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
111 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
113 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
114 setOperationAction(ISD::BRIND, MVT::Other, Expand);
116 // We need to custom lower some of the intrinsics
117 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
119 // Library functions. These default to Expand, but we have instructions
121 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
122 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
123 setOperationAction(ISD::FPOW, MVT::f32, Legal);
124 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
125 setOperationAction(ISD::FABS, MVT::f32, Legal);
126 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
127 setOperationAction(ISD::FRINT, MVT::f32, Legal);
128 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
130 setOperationAction(ISD::FROUND, MVT::f32, Custom);
131 setOperationAction(ISD::FROUND, MVT::f64, Custom);
133 setOperationAction(ISD::FREM, MVT::f32, Custom);
134 setOperationAction(ISD::FREM, MVT::f64, Custom);
136 // Lower floating point store/load to integer store/load to reduce the number
137 // of patterns in tablegen.
138 setOperationAction(ISD::STORE, MVT::f32, Promote);
139 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
141 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
142 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
144 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
145 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
147 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
148 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
150 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
153 setOperationAction(ISD::STORE, MVT::f64, Promote);
154 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
156 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
157 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
159 // Custom lowering of vector stores is required for local address space
161 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
163 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
164 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
165 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
167 // XXX: This can be change to Custom, once ExpandVectorStores can
168 // handle 64-bit stores.
169 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
171 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
172 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
173 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
174 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
175 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
178 setOperationAction(ISD::LOAD, MVT::f32, Promote);
179 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
181 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
182 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
184 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
185 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
187 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
190 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
193 setOperationAction(ISD::LOAD, MVT::f64, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
196 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
199 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
200 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
201 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
202 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
203 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
204 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
205 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
206 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
207 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
208 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
210 // There are no 64-bit extloads. These should be done as a 32-bit extload and
211 // an extension to 64-bit.
212 for (MVT VT : MVT::integer_valuetypes()) {
213 setLoadExtAction(ISD::EXTLOAD, MVT::i64, VT, Expand);
214 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, VT, Expand);
215 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
218 for (MVT VT : MVT::integer_vector_valuetypes()) {
219 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
220 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
221 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
222 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
223 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
224 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
225 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
226 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
227 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
228 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
229 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
230 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
233 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
235 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
236 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
237 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
238 setOperationAction(ISD::FRINT, MVT::f64, Custom);
239 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
242 if (!Subtarget->hasBFI()) {
243 // fcopysign can be done in a single instruction with BFI.
244 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
245 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
248 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
250 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
251 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
252 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
253 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
255 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
256 for (MVT VT : ScalarIntVTs) {
257 setOperationAction(ISD::SREM, VT, Expand);
258 setOperationAction(ISD::SDIV, VT, Expand);
260 // GPU does not have divrem function for signed or unsigned.
261 setOperationAction(ISD::SDIVREM, VT, Custom);
262 setOperationAction(ISD::UDIVREM, VT, Custom);
264 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
265 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
266 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
268 setOperationAction(ISD::BSWAP, VT, Expand);
269 setOperationAction(ISD::CTTZ, VT, Expand);
270 setOperationAction(ISD::CTLZ, VT, Expand);
273 if (!Subtarget->hasBCNT(32))
274 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
276 if (!Subtarget->hasBCNT(64))
277 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
279 // The hardware supports 32-bit ROTR, but not ROTL.
280 setOperationAction(ISD::ROTL, MVT::i32, Expand);
281 setOperationAction(ISD::ROTL, MVT::i64, Expand);
282 setOperationAction(ISD::ROTR, MVT::i64, Expand);
284 setOperationAction(ISD::MUL, MVT::i64, Expand);
285 setOperationAction(ISD::MULHU, MVT::i64, Expand);
286 setOperationAction(ISD::MULHS, MVT::i64, Expand);
287 setOperationAction(ISD::UDIV, MVT::i32, Expand);
288 setOperationAction(ISD::UREM, MVT::i32, Expand);
289 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
290 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
291 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
292 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
293 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
295 if (!Subtarget->hasFFBH())
296 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
298 if (!Subtarget->hasFFBL())
299 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
301 static const MVT::SimpleValueType VectorIntTypes[] = {
302 MVT::v2i32, MVT::v4i32
305 for (MVT VT : VectorIntTypes) {
306 // Expand the following operations for the current type by default.
307 setOperationAction(ISD::ADD, VT, Expand);
308 setOperationAction(ISD::AND, VT, Expand);
309 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
310 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
311 setOperationAction(ISD::MUL, VT, Expand);
312 setOperationAction(ISD::OR, VT, Expand);
313 setOperationAction(ISD::SHL, VT, Expand);
314 setOperationAction(ISD::SRA, VT, Expand);
315 setOperationAction(ISD::SRL, VT, Expand);
316 setOperationAction(ISD::ROTL, VT, Expand);
317 setOperationAction(ISD::ROTR, VT, Expand);
318 setOperationAction(ISD::SUB, VT, Expand);
319 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
320 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
321 setOperationAction(ISD::SDIV, VT, Expand);
322 setOperationAction(ISD::UDIV, VT, Expand);
323 setOperationAction(ISD::SREM, VT, Expand);
324 setOperationAction(ISD::UREM, VT, Expand);
325 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
326 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
327 setOperationAction(ISD::SDIVREM, VT, Custom);
328 setOperationAction(ISD::UDIVREM, VT, Custom);
329 setOperationAction(ISD::ADDC, VT, Expand);
330 setOperationAction(ISD::SUBC, VT, Expand);
331 setOperationAction(ISD::ADDE, VT, Expand);
332 setOperationAction(ISD::SUBE, VT, Expand);
333 setOperationAction(ISD::SELECT, VT, Expand);
334 setOperationAction(ISD::VSELECT, VT, Expand);
335 setOperationAction(ISD::SELECT_CC, VT, Expand);
336 setOperationAction(ISD::XOR, VT, Expand);
337 setOperationAction(ISD::BSWAP, VT, Expand);
338 setOperationAction(ISD::CTPOP, VT, Expand);
339 setOperationAction(ISD::CTTZ, VT, Expand);
340 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
341 setOperationAction(ISD::CTLZ, VT, Expand);
342 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
343 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
346 static const MVT::SimpleValueType FloatVectorTypes[] = {
347 MVT::v2f32, MVT::v4f32
350 for (MVT VT : FloatVectorTypes) {
351 setOperationAction(ISD::FABS, VT, Expand);
352 setOperationAction(ISD::FMINNUM, VT, Expand);
353 setOperationAction(ISD::FMAXNUM, VT, Expand);
354 setOperationAction(ISD::FADD, VT, Expand);
355 setOperationAction(ISD::FCEIL, VT, Expand);
356 setOperationAction(ISD::FCOS, VT, Expand);
357 setOperationAction(ISD::FDIV, VT, Expand);
358 setOperationAction(ISD::FEXP2, VT, Expand);
359 setOperationAction(ISD::FLOG2, VT, Expand);
360 setOperationAction(ISD::FREM, VT, Expand);
361 setOperationAction(ISD::FPOW, VT, Expand);
362 setOperationAction(ISD::FFLOOR, VT, Expand);
363 setOperationAction(ISD::FTRUNC, VT, Expand);
364 setOperationAction(ISD::FMUL, VT, Expand);
365 setOperationAction(ISD::FMA, VT, Expand);
366 setOperationAction(ISD::FRINT, VT, Expand);
367 setOperationAction(ISD::FNEARBYINT, VT, Expand);
368 setOperationAction(ISD::FSQRT, VT, Expand);
369 setOperationAction(ISD::FSIN, VT, Expand);
370 setOperationAction(ISD::FSUB, VT, Expand);
371 setOperationAction(ISD::FNEG, VT, Expand);
372 setOperationAction(ISD::SELECT, VT, Expand);
373 setOperationAction(ISD::VSELECT, VT, Expand);
374 setOperationAction(ISD::SELECT_CC, VT, Expand);
375 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
376 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
379 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
380 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
382 setTargetDAGCombine(ISD::MUL);
383 setTargetDAGCombine(ISD::SELECT);
384 setTargetDAGCombine(ISD::SELECT_CC);
385 setTargetDAGCombine(ISD::STORE);
387 setBooleanContents(ZeroOrNegativeOneBooleanContent);
388 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
390 setSchedulingPreference(Sched::RegPressure);
391 setJumpIsExpensive(true);
393 // SI at least has hardware support for floating point exceptions, but no way
394 // of using or handling them is implemented. They are also optional in OpenCL
396 setHasFloatingPointExceptions(false);
398 setSelectIsExpensive(false);
399 PredictableSelectIsExpensive = false;
401 // There are no integer divide instructions, and these expand to a pretty
402 // large sequence of instructions.
403 setIntDivIsCheap(false);
404 setPow2SDivIsCheap(false);
405 setFsqrtIsCheap(true);
407 // FIXME: Need to really handle these.
408 MaxStoresPerMemcpy = 4096;
409 MaxStoresPerMemmove = 4096;
410 MaxStoresPerMemset = 4096;
413 //===----------------------------------------------------------------------===//
414 // Target Information
415 //===----------------------------------------------------------------------===//
417 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
421 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
425 // The backend supports 32 and 64 bit floating point immediates.
426 // FIXME: Why are we reporting vectors of FP immediates as legal?
427 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
428 EVT ScalarVT = VT.getScalarType();
429 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
432 // We don't want to shrink f64 / f32 constants.
433 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
434 EVT ScalarVT = VT.getScalarType();
435 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
438 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
442 unsigned NewSize = NewVT.getStoreSizeInBits();
444 // If we are reducing to a 32-bit load, this is always better.
448 EVT OldVT = N->getValueType(0);
449 unsigned OldSize = OldVT.getStoreSizeInBits();
451 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
452 // extloads, so doing one requires using a buffer_load. In cases where we
453 // still couldn't use a scalar load, using the wider load shouldn't really
456 // If the old size already had to be an extload, there's no harm in continuing
457 // to reduce the width.
458 return (OldSize < 32);
461 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
463 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
466 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
467 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
469 return ((LScalarSize <= CastScalarSize) ||
470 (CastScalarSize >= 32) ||
474 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
475 // profitable with the expansion for 64-bit since it's generally good to
477 // FIXME: These should really have the size as a parameter.
478 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
482 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
486 //===---------------------------------------------------------------------===//
488 //===---------------------------------------------------------------------===//
490 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
491 assert(VT.isFloatingPoint());
492 return VT == MVT::f32 || VT == MVT::f64;
495 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
496 assert(VT.isFloatingPoint());
497 return VT == MVT::f32 || VT == MVT::f64;
500 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
501 // Truncate is just accessing a subregister.
502 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
505 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
506 // Truncate is just accessing a subregister.
507 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
508 (Dest->getPrimitiveSizeInBits() % 32 == 0);
511 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
512 const DataLayout *DL = getDataLayout();
513 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
514 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
516 return SrcSize == 32 && DestSize == 64;
519 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
520 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
521 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
522 // this will enable reducing 64-bit operations the 32-bit, which is always
524 return Src == MVT::i32 && Dest == MVT::i64;
527 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
528 return isZExtFree(Val.getValueType(), VT2);
531 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
532 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
533 // limited number of native 64-bit operations. Shrinking an operation to fit
534 // in a single 32-bit register should always be helpful. As currently used,
535 // this is much less general than the name suggests, and is only used in
536 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
537 // not profitable, and may actually be harmful.
538 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
541 //===---------------------------------------------------------------------===//
542 // TargetLowering Callbacks
543 //===---------------------------------------------------------------------===//
545 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
546 const SmallVectorImpl<ISD::InputArg> &Ins) const {
548 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
551 SDValue AMDGPUTargetLowering::LowerReturn(
553 CallingConv::ID CallConv,
555 const SmallVectorImpl<ISD::OutputArg> &Outs,
556 const SmallVectorImpl<SDValue> &OutVals,
557 SDLoc DL, SelectionDAG &DAG) const {
558 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
561 //===---------------------------------------------------------------------===//
562 // Target specific lowering
563 //===---------------------------------------------------------------------===//
565 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
566 SmallVectorImpl<SDValue> &InVals) const {
567 SDValue Callee = CLI.Callee;
568 SelectionDAG &DAG = CLI.DAG;
570 const Function &Fn = *DAG.getMachineFunction().getFunction();
572 StringRef FuncName("<unknown>");
574 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
575 FuncName = G->getSymbol();
576 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
577 FuncName = G->getGlobal()->getName();
579 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
580 DAG.getContext()->diagnose(NoCalls);
584 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
585 SelectionDAG &DAG) const {
586 switch (Op.getOpcode()) {
588 Op.getNode()->dump();
589 llvm_unreachable("Custom lowering code for this"
590 "instruction is not implemented yet!");
592 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
593 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
594 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
595 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
596 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
597 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
598 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
599 case ISD::FREM: return LowerFREM(Op, DAG);
600 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
601 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
602 case ISD::FRINT: return LowerFRINT(Op, DAG);
603 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
604 case ISD::FROUND: return LowerFROUND(Op, DAG);
605 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
606 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
607 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
608 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
609 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
614 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
615 SmallVectorImpl<SDValue> &Results,
616 SelectionDAG &DAG) const {
617 switch (N->getOpcode()) {
618 case ISD::SIGN_EXTEND_INREG:
619 // Different parts of legalization seem to interpret which type of
620 // sign_extend_inreg is the one to check for custom lowering. The extended
621 // from type is what really matters, but some places check for custom
622 // lowering of the result type. This results in trying to use
623 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
624 // nothing here and let the illegal result integer be handled normally.
627 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
631 Results.push_back(SDValue(Node, 0));
632 Results.push_back(SDValue(Node, 1));
633 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
635 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
639 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
640 if (Lowered.getNode())
641 Results.push_back(Lowered);
649 // FIXME: This implements accesses to initialized globals in the constant
650 // address space by copying them to private and accessing that. It does not
651 // properly handle illegal types or vectors. The private vector loads are not
652 // scalarized, and the illegal scalars hit an assertion. This technique will not
653 // work well with large initializers, and this should eventually be
654 // removed. Initialized globals should be placed into a data section that the
655 // runtime will load into a buffer before the kernel is executed. Uses of the
656 // global need to be replaced with a pointer loaded from an implicit kernel
657 // argument into this buffer holding the copy of the data, which will remove the
658 // need for any of this.
659 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
660 const GlobalValue *GV,
661 const SDValue &InitPtr,
663 SelectionDAG &DAG) const {
664 const DataLayout *TD = getDataLayout();
666 Type *InitTy = Init->getType();
668 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
669 EVT VT = EVT::getEVT(InitTy);
670 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
671 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
672 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
673 TD->getPrefTypeAlignment(InitTy));
676 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
677 EVT VT = EVT::getEVT(CFP->getType());
678 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
679 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
680 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
681 TD->getPrefTypeAlignment(CFP->getType()));
684 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
685 const StructLayout *SL = TD->getStructLayout(ST);
687 EVT PtrVT = InitPtr.getValueType();
688 SmallVector<SDValue, 8> Chains;
690 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
691 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
692 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
694 Constant *Elt = Init->getAggregateElement(I);
695 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
698 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
701 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
702 EVT PtrVT = InitPtr.getValueType();
704 unsigned NumElements;
705 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
706 NumElements = AT->getNumElements();
707 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
708 NumElements = VT->getNumElements();
710 llvm_unreachable("Unexpected type");
712 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
713 SmallVector<SDValue, 8> Chains;
714 for (unsigned i = 0; i < NumElements; ++i) {
715 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
716 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
718 Constant *Elt = Init->getAggregateElement(i);
719 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
722 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
725 if (isa<UndefValue>(Init)) {
726 EVT VT = EVT::getEVT(InitTy);
727 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
728 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
729 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
730 TD->getPrefTypeAlignment(InitTy));
734 llvm_unreachable("Unhandled constant initializer");
737 static bool hasDefinedInitializer(const GlobalValue *GV) {
738 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
739 if (!GVar || !GVar->hasInitializer())
742 if (isa<UndefValue>(GVar->getInitializer()))
748 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
750 SelectionDAG &DAG) const {
752 const DataLayout *TD = getDataLayout();
753 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
754 const GlobalValue *GV = G->getGlobal();
756 switch (G->getAddressSpace()) {
757 case AMDGPUAS::LOCAL_ADDRESS: {
758 // XXX: What does the value of G->getOffset() mean?
759 assert(G->getOffset() == 0 &&
760 "Do not know what to do with an non-zero offset");
762 // TODO: We could emit code to handle the initialization somewhere.
763 if (hasDefinedInitializer(GV))
767 if (MFI->LocalMemoryObjects.count(GV) == 0) {
768 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
769 Offset = MFI->LDSSize;
770 MFI->LocalMemoryObjects[GV] = Offset;
771 // XXX: Account for alignment?
772 MFI->LDSSize += Size;
774 Offset = MFI->LocalMemoryObjects[GV];
777 return DAG.getConstant(Offset, getPointerTy(AMDGPUAS::LOCAL_ADDRESS));
779 case AMDGPUAS::CONSTANT_ADDRESS: {
780 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
781 Type *EltType = GV->getType()->getElementType();
782 unsigned Size = TD->getTypeAllocSize(EltType);
783 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
785 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
786 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
788 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
789 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
791 const GlobalVariable *Var = cast<GlobalVariable>(GV);
792 if (!Var->hasInitializer()) {
793 // This has no use, but bugpoint will hit it.
794 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
797 const Constant *Init = Var->getInitializer();
798 SmallVector<SDNode*, 8> WorkList;
800 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
801 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
802 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
804 WorkList.push_back(*I);
806 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
807 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
808 E = WorkList.end(); I != E; ++I) {
809 SmallVector<SDValue, 8> Ops;
810 Ops.push_back(Chain);
811 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
812 Ops.push_back((*I)->getOperand(i));
814 DAG.UpdateNodeOperands(*I, Ops);
816 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
820 const Function &Fn = *DAG.getMachineFunction().getFunction();
821 DiagnosticInfoUnsupported BadInit(Fn,
822 "initializer for address space");
823 DAG.getContext()->diagnose(BadInit);
827 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
828 SelectionDAG &DAG) const {
829 SmallVector<SDValue, 8> Args;
830 SDValue A = Op.getOperand(0);
831 SDValue B = Op.getOperand(1);
833 DAG.ExtractVectorElements(A, Args);
834 DAG.ExtractVectorElements(B, Args);
836 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
839 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
840 SelectionDAG &DAG) const {
842 SmallVector<SDValue, 8> Args;
843 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
844 EVT VT = Op.getValueType();
845 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
846 VT.getVectorNumElements());
848 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
851 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
852 SelectionDAG &DAG) const {
854 MachineFunction &MF = DAG.getMachineFunction();
855 const AMDGPUFrameLowering *TFL = Subtarget->getFrameLowering();
857 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
859 unsigned FrameIndex = FIN->getIndex();
860 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
861 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
865 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
866 SelectionDAG &DAG) const {
867 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
869 EVT VT = Op.getValueType();
871 switch (IntrinsicID) {
873 case AMDGPUIntrinsic::AMDGPU_abs:
874 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
875 return LowerIntrinsicIABS(Op, DAG);
876 case AMDGPUIntrinsic::AMDGPU_lrp:
877 return LowerIntrinsicLRP(Op, DAG);
878 case AMDGPUIntrinsic::AMDGPU_fract:
879 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
880 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
882 case AMDGPUIntrinsic::AMDGPU_clamp:
883 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
884 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
885 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
887 case Intrinsic::AMDGPU_div_scale: {
888 // 3rd parameter required to be a constant.
889 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
891 return DAG.getUNDEF(VT);
893 // Translate to the operands expected by the machine instruction. The
894 // first parameter must be the same as the first instruction.
895 SDValue Numerator = Op.getOperand(1);
896 SDValue Denominator = Op.getOperand(2);
898 // Note this order is opposite of the machine instruction's operations,
899 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
900 // intrinsic has the numerator as the first operand to match a normal
901 // division operation.
903 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
905 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
906 Denominator, Numerator);
909 case Intrinsic::AMDGPU_div_fmas:
910 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
911 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
914 case Intrinsic::AMDGPU_div_fixup:
915 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
916 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
918 case Intrinsic::AMDGPU_trig_preop:
919 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
920 Op.getOperand(1), Op.getOperand(2));
922 case Intrinsic::AMDGPU_rcp:
923 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
925 case Intrinsic::AMDGPU_rsq:
926 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
928 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
929 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
931 case Intrinsic::AMDGPU_rsq_clamped:
932 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
933 Type *Type = VT.getTypeForEVT(*DAG.getContext());
934 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
935 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
937 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
938 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
939 DAG.getConstantFP(Max, VT));
940 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
941 DAG.getConstantFP(Min, VT));
943 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
946 case Intrinsic::AMDGPU_ldexp:
947 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
950 case AMDGPUIntrinsic::AMDGPU_imax:
951 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
953 case AMDGPUIntrinsic::AMDGPU_umax:
954 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
956 case AMDGPUIntrinsic::AMDGPU_imin:
957 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
959 case AMDGPUIntrinsic::AMDGPU_umin:
960 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
963 case AMDGPUIntrinsic::AMDGPU_umul24:
964 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
965 Op.getOperand(1), Op.getOperand(2));
967 case AMDGPUIntrinsic::AMDGPU_imul24:
968 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
969 Op.getOperand(1), Op.getOperand(2));
971 case AMDGPUIntrinsic::AMDGPU_umad24:
972 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
973 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
975 case AMDGPUIntrinsic::AMDGPU_imad24:
976 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
977 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
979 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
980 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
982 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
983 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
985 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
986 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
988 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
989 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
991 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
992 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
997 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
998 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
1003 case AMDGPUIntrinsic::AMDGPU_bfi:
1004 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
1009 case AMDGPUIntrinsic::AMDGPU_bfm:
1010 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
1014 case AMDGPUIntrinsic::AMDGPU_brev:
1015 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
1017 case Intrinsic::AMDGPU_class:
1018 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
1019 Op.getOperand(1), Op.getOperand(2));
1021 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
1022 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
1024 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
1025 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
1026 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
1027 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
1031 ///IABS(a) = SMAX(sub(0, a), a)
1032 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
1033 SelectionDAG &DAG) const {
1035 EVT VT = Op.getValueType();
1036 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1039 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
1042 /// Linear Interpolation
1043 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
1044 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
1045 SelectionDAG &DAG) const {
1047 EVT VT = Op.getValueType();
1048 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
1049 DAG.getConstantFP(1.0f, MVT::f32),
1051 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
1053 return DAG.getNode(ISD::FADD, DL, VT,
1054 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1058 /// \brief Generate Min/Max node
1059 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
1066 DAGCombinerInfo &DCI) const {
1067 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1070 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1073 SelectionDAG &DAG = DCI.DAG;
1074 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1083 case ISD::SETFALSE2:
1092 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1093 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1099 // Ordered. Assume ordered for undefined.
1101 // Only do this after legalization to avoid interfering with other combines
1102 // which might occur.
1103 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1104 !DCI.isCalledByLegalizer())
1107 // We need to permute the operands to get the correct NaN behavior. The
1108 // selected operand is the second one based on the failing compare with NaN,
1109 // so permute it based on the compare type the hardware uses.
1111 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1112 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1117 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1118 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1124 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1125 !DCI.isCalledByLegalizer())
1129 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1130 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1132 case ISD::SETCC_INVALID:
1133 llvm_unreachable("Invalid setcc condcode!");
1138 /// \brief Generate Min/Max node
1139 SDValue AMDGPUTargetLowering::CombineIMinMax(SDLoc DL,
1146 SelectionDAG &DAG) const {
1147 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1150 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1154 unsigned Opc = (LHS == True) ? AMDGPUISD::UMIN : AMDGPUISD::UMAX;
1155 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1159 unsigned Opc = (LHS == True) ? AMDGPUISD::SMIN : AMDGPUISD::SMAX;
1160 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1164 unsigned Opc = (LHS == True) ? AMDGPUISD::SMAX : AMDGPUISD::SMIN;
1165 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1169 unsigned Opc = (LHS == True) ? AMDGPUISD::UMAX : AMDGPUISD::UMIN;
1170 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1177 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1178 SelectionDAG &DAG) const {
1179 LoadSDNode *Load = cast<LoadSDNode>(Op);
1180 EVT MemVT = Load->getMemoryVT();
1181 EVT MemEltVT = MemVT.getVectorElementType();
1183 EVT LoadVT = Op.getValueType();
1184 EVT EltVT = LoadVT.getVectorElementType();
1185 EVT PtrVT = Load->getBasePtr().getValueType();
1187 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1188 SmallVector<SDValue, 8> Loads;
1189 SmallVector<SDValue, 8> Chains;
1192 unsigned MemEltSize = MemEltVT.getStoreSize();
1193 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1195 for (unsigned i = 0; i < NumElts; ++i) {
1196 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1197 DAG.getConstant(i * MemEltSize, PtrVT));
1200 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1201 Load->getChain(), Ptr,
1202 SrcValue.getWithOffset(i * MemEltSize),
1203 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1204 Load->isInvariant(), Load->getAlignment());
1205 Loads.push_back(NewLoad.getValue(0));
1206 Chains.push_back(NewLoad.getValue(1));
1210 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1211 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1214 return DAG.getMergeValues(Ops, SL);
1217 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1218 SelectionDAG &DAG) const {
1219 EVT VT = Op.getValueType();
1221 // If this is a 2 element vector, we really want to scalarize and not create
1222 // weird 1 element vectors.
1223 if (VT.getVectorNumElements() == 2)
1224 return ScalarizeVectorLoad(Op, DAG);
1226 LoadSDNode *Load = cast<LoadSDNode>(Op);
1227 SDValue BasePtr = Load->getBasePtr();
1228 EVT PtrVT = BasePtr.getValueType();
1229 EVT MemVT = Load->getMemoryVT();
1231 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1234 EVT LoMemVT, HiMemVT;
1237 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1238 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1239 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1241 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1242 Load->getChain(), BasePtr,
1244 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1245 Load->isInvariant(), Load->getAlignment());
1247 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1248 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1251 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1252 Load->getChain(), HiPtr,
1253 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1254 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1255 Load->isInvariant(), Load->getAlignment());
1258 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1259 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1260 LoLoad.getValue(1), HiLoad.getValue(1))
1263 return DAG.getMergeValues(Ops, SL);
1266 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1267 SelectionDAG &DAG) const {
1268 StoreSDNode *Store = cast<StoreSDNode>(Op);
1269 EVT MemVT = Store->getMemoryVT();
1270 unsigned MemBits = MemVT.getSizeInBits();
1272 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1273 // truncating store into an i32 store.
1274 // XXX: We could also handle optimize other vector bitwidths.
1275 if (!MemVT.isVector() || MemBits > 32) {
1280 SDValue Value = Store->getValue();
1281 EVT VT = Value.getValueType();
1282 EVT ElemVT = VT.getVectorElementType();
1283 SDValue Ptr = Store->getBasePtr();
1284 EVT MemEltVT = MemVT.getVectorElementType();
1285 unsigned MemEltBits = MemEltVT.getSizeInBits();
1286 unsigned MemNumElements = MemVT.getVectorNumElements();
1287 unsigned PackedSize = MemVT.getStoreSizeInBits();
1288 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1290 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1292 SDValue PackedValue;
1293 for (unsigned i = 0; i < MemNumElements; ++i) {
1294 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1295 DAG.getConstant(i, MVT::i32));
1296 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1297 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1299 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1300 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1305 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1309 if (PackedSize < 32) {
1310 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1311 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1312 Store->getMemOperand()->getPointerInfo(),
1314 Store->isNonTemporal(), Store->isVolatile(),
1315 Store->getAlignment());
1318 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1319 Store->getMemOperand()->getPointerInfo(),
1320 Store->isVolatile(), Store->isNonTemporal(),
1321 Store->getAlignment());
1324 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1325 SelectionDAG &DAG) const {
1326 StoreSDNode *Store = cast<StoreSDNode>(Op);
1327 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1328 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1329 EVT PtrVT = Store->getBasePtr().getValueType();
1330 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1333 SmallVector<SDValue, 8> Chains;
1335 unsigned EltSize = MemEltVT.getStoreSize();
1336 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1338 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1339 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1341 DAG.getConstant(i, MVT::i32));
1343 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), PtrVT);
1344 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1346 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1347 SrcValue.getWithOffset(i * EltSize),
1348 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1349 Store->getAlignment());
1350 Chains.push_back(NewStore);
1353 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1356 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1357 SelectionDAG &DAG) const {
1358 StoreSDNode *Store = cast<StoreSDNode>(Op);
1359 SDValue Val = Store->getValue();
1360 EVT VT = Val.getValueType();
1362 // If this is a 2 element vector, we really want to scalarize and not create
1363 // weird 1 element vectors.
1364 if (VT.getVectorNumElements() == 2)
1365 return ScalarizeVectorStore(Op, DAG);
1367 EVT MemVT = Store->getMemoryVT();
1368 SDValue Chain = Store->getChain();
1369 SDValue BasePtr = Store->getBasePtr();
1373 EVT LoMemVT, HiMemVT;
1376 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1377 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1378 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1380 EVT PtrVT = BasePtr.getValueType();
1381 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1382 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1384 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1386 = DAG.getTruncStore(Chain, SL, Lo,
1390 Store->isNonTemporal(),
1391 Store->isVolatile(),
1392 Store->getAlignment());
1394 = DAG.getTruncStore(Chain, SL, Hi,
1396 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1398 Store->isNonTemporal(),
1399 Store->isVolatile(),
1400 Store->getAlignment());
1402 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1406 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1408 LoadSDNode *Load = cast<LoadSDNode>(Op);
1409 ISD::LoadExtType ExtType = Load->getExtensionType();
1410 EVT VT = Op.getValueType();
1411 EVT MemVT = Load->getMemoryVT();
1413 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1414 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1415 // FIXME: Copied from PPC
1416 // First, load into 32 bits, then truncate to 1 bit.
1418 SDValue Chain = Load->getChain();
1419 SDValue BasePtr = Load->getBasePtr();
1420 MachineMemOperand *MMO = Load->getMemOperand();
1422 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1423 BasePtr, MVT::i8, MMO);
1426 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1430 return DAG.getMergeValues(Ops, DL);
1433 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1434 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1435 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1439 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1440 DAG.getConstant(2, MVT::i32));
1441 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1442 Load->getChain(), Ptr,
1443 DAG.getTargetConstant(0, MVT::i32),
1445 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1447 DAG.getConstant(0x3, MVT::i32));
1448 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1449 DAG.getConstant(3, MVT::i32));
1451 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1453 EVT MemEltVT = MemVT.getScalarType();
1454 if (ExtType == ISD::SEXTLOAD) {
1455 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1458 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1462 return DAG.getMergeValues(Ops, DL);
1466 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1470 return DAG.getMergeValues(Ops, DL);
1473 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1475 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1476 if (Result.getNode()) {
1480 StoreSDNode *Store = cast<StoreSDNode>(Op);
1481 SDValue Chain = Store->getChain();
1482 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1483 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1484 Store->getValue().getValueType().isVector()) {
1485 return ScalarizeVectorStore(Op, DAG);
1488 EVT MemVT = Store->getMemoryVT();
1489 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1490 MemVT.bitsLT(MVT::i32)) {
1492 if (Store->getMemoryVT() == MVT::i8) {
1494 } else if (Store->getMemoryVT() == MVT::i16) {
1497 SDValue BasePtr = Store->getBasePtr();
1498 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1499 DAG.getConstant(2, MVT::i32));
1500 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1501 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1503 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1504 DAG.getConstant(0x3, MVT::i32));
1506 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1507 DAG.getConstant(3, MVT::i32));
1509 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1512 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1514 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1515 MaskedValue, ShiftAmt);
1517 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1519 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1520 DAG.getConstant(0xffffffff, MVT::i32));
1521 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1523 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1524 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1525 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1530 // This is a shortcut for integer division because we have fast i32<->f32
1531 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1532 // float is enough to accurately represent up to a 24-bit integer.
1533 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1535 EVT VT = Op.getValueType();
1536 SDValue LHS = Op.getOperand(0);
1537 SDValue RHS = Op.getOperand(1);
1538 MVT IntVT = MVT::i32;
1539 MVT FltVT = MVT::f32;
1541 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1542 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1544 if (VT.isVector()) {
1545 unsigned NElts = VT.getVectorNumElements();
1546 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1547 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1550 unsigned BitSize = VT.getScalarType().getSizeInBits();
1552 SDValue jq = DAG.getConstant(1, IntVT);
1555 // char|short jq = ia ^ ib;
1556 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1558 // jq = jq >> (bitsize - 2)
1559 jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
1562 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));
1565 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1568 // int ia = (int)LHS;
1570 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1572 // int ib, (int)RHS;
1574 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1576 // float fa = (float)ia;
1577 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1579 // float fb = (float)ib;
1580 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1582 // float fq = native_divide(fa, fb);
1583 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1584 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1587 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1589 // float fqneg = -fq;
1590 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1592 // float fr = mad(fqneg, fb, fa);
1593 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1594 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1596 // int iq = (int)fq;
1597 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1600 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1603 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1605 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), VT);
1607 // int cv = fr >= fb;
1608 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1610 // jq = (cv ? jq : 0);
1611 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
1613 // dst = trunc/extend to legal type
1614 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1617 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1619 // Rem needs compensation, it's easier to recompute it
1620 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1621 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1627 return DAG.getMergeValues(Res, DL);
1630 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1632 SmallVectorImpl<SDValue> &Results) const {
1633 assert(Op.getValueType() == MVT::i64);
1636 EVT VT = Op.getValueType();
1637 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1639 SDValue one = DAG.getConstant(1, HalfVT);
1640 SDValue zero = DAG.getConstant(0, HalfVT);
1643 SDValue LHS = Op.getOperand(0);
1644 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1645 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1647 SDValue RHS = Op.getOperand(1);
1648 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1649 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1651 if (VT == MVT::i64 &&
1652 DAG.MaskedValueIsZero(RHS, APInt::getHighBitsSet(64, 32)) &&
1653 DAG.MaskedValueIsZero(LHS, APInt::getHighBitsSet(64, 32))) {
1655 SDValue Res = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1658 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(0), zero);
1659 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, Res.getValue(1), zero);
1660 Results.push_back(DIV);
1661 Results.push_back(REM);
1665 // Get Speculative values
1666 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1667 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1669 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1670 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, zero);
1672 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1673 SDValue DIV_Lo = zero;
1675 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1677 for (unsigned i = 0; i < halfBitWidth; ++i) {
1678 const unsigned bitPos = halfBitWidth - i - 1;
1679 SDValue POS = DAG.getConstant(bitPos, HalfVT);
1680 // Get value of high bit
1681 // TODO: Remove the BFE part when the optimization is fixed
1683 if (halfBitWidth == 32 && Subtarget->hasBFE()) {
1684 HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
1686 HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1687 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1689 HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
1692 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, VT));
1694 REM = DAG.getNode(ISD::OR, DL, VT, REM, HBit);
1696 SDValue BIT = DAG.getConstant(1 << bitPos, HalfVT);
1697 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1699 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1702 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1703 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1706 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
1707 Results.push_back(DIV);
1708 Results.push_back(REM);
1711 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1712 SelectionDAG &DAG) const {
1714 EVT VT = Op.getValueType();
1716 if (VT == MVT::i64) {
1717 SmallVector<SDValue, 2> Results;
1718 LowerUDIVREM64(Op, DAG, Results);
1719 return DAG.getMergeValues(Results, DL);
1722 SDValue Num = Op.getOperand(0);
1723 SDValue Den = Op.getOperand(1);
1725 if (VT == MVT::i32) {
1726 if (DAG.MaskedValueIsZero(Num, APInt::getHighBitsSet(32, 8)) &&
1727 DAG.MaskedValueIsZero(Den, APInt::getHighBitsSet(32, 8))) {
1728 // TODO: We technically could do this for i64, but shouldn't that just be
1729 // handled by something generally reducing 64-bit division on 32-bit
1730 // values to 32-bit?
1731 return LowerDIVREM24(Op, DAG, false);
1735 // RCP = URECIP(Den) = 2^32 / Den + e
1736 // e is rounding error.
1737 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1739 // RCP_LO = mul(RCP, Den) */
1740 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1742 // RCP_HI = mulhu (RCP, Den) */
1743 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1745 // NEG_RCP_LO = -RCP_LO
1746 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1749 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1750 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1753 // Calculate the rounding error from the URECIP instruction
1754 // E = mulhu(ABS_RCP_LO, RCP)
1755 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1757 // RCP_A_E = RCP + E
1758 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1760 // RCP_S_E = RCP - E
1761 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1763 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1764 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1767 // Quotient = mulhu(Tmp0, Num)
1768 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1770 // Num_S_Remainder = Quotient * Den
1771 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1773 // Remainder = Num - Num_S_Remainder
1774 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1776 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1777 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1778 DAG.getConstant(-1, VT),
1779 DAG.getConstant(0, VT),
1781 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1782 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1784 DAG.getConstant(-1, VT),
1785 DAG.getConstant(0, VT),
1787 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1788 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1791 // Calculate Division result:
1793 // Quotient_A_One = Quotient + 1
1794 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1795 DAG.getConstant(1, VT));
1797 // Quotient_S_One = Quotient - 1
1798 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1799 DAG.getConstant(1, VT));
1801 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1802 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1803 Quotient, Quotient_A_One, ISD::SETEQ);
1805 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1806 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1807 Quotient_S_One, Div, ISD::SETEQ);
1809 // Calculate Rem result:
1811 // Remainder_S_Den = Remainder - Den
1812 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1814 // Remainder_A_Den = Remainder + Den
1815 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1817 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1818 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1819 Remainder, Remainder_S_Den, ISD::SETEQ);
1821 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1822 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1823 Remainder_A_Den, Rem, ISD::SETEQ);
1828 return DAG.getMergeValues(Ops, DL);
1831 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1832 SelectionDAG &DAG) const {
1834 EVT VT = Op.getValueType();
1836 SDValue LHS = Op.getOperand(0);
1837 SDValue RHS = Op.getOperand(1);
1839 SDValue Zero = DAG.getConstant(0, VT);
1840 SDValue NegOne = DAG.getConstant(-1, VT);
1842 if (VT == MVT::i32 &&
1843 DAG.ComputeNumSignBits(LHS) > 8 &&
1844 DAG.ComputeNumSignBits(RHS) > 8) {
1845 return LowerDIVREM24(Op, DAG, true);
1847 if (VT == MVT::i64 &&
1848 DAG.ComputeNumSignBits(LHS) > 32 &&
1849 DAG.ComputeNumSignBits(RHS) > 32) {
1850 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1853 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, Zero);
1854 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, Zero);
1855 SDValue DIVREM = DAG.getNode(ISD::SDIVREM, DL, DAG.getVTList(HalfVT, HalfVT),
1858 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(0)),
1859 DAG.getNode(ISD::SIGN_EXTEND, DL, VT, DIVREM.getValue(1))
1861 return DAG.getMergeValues(Res, DL);
1864 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1865 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1866 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1867 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1869 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1870 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1872 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1873 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1875 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1876 SDValue Rem = Div.getValue(1);
1878 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1879 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1881 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1882 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1888 return DAG.getMergeValues(Res, DL);
1891 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1892 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1894 EVT VT = Op.getValueType();
1895 SDValue X = Op.getOperand(0);
1896 SDValue Y = Op.getOperand(1);
1898 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1899 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1900 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1902 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1905 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1907 SDValue Src = Op.getOperand(0);
1909 // result = trunc(src)
1910 // if (src > 0.0 && src != result)
1913 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1915 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1916 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1918 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1920 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1921 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1922 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1924 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1925 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1928 static SDValue extractF64Exponent(SDValue Hi, SDLoc SL, SelectionDAG &DAG) {
1929 const unsigned FractBits = 52;
1930 const unsigned ExpBits = 11;
1932 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1934 DAG.getConstant(FractBits - 32, MVT::i32),
1935 DAG.getConstant(ExpBits, MVT::i32));
1936 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1937 DAG.getConstant(1023, MVT::i32));
1942 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1944 SDValue Src = Op.getOperand(0);
1946 assert(Op.getValueType() == MVT::f64);
1948 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1949 const SDValue One = DAG.getConstant(1, MVT::i32);
1951 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1953 // Extract the upper half, since this is where we will find the sign and
1955 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1957 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
1959 const unsigned FractBits = 52;
1961 // Extract the sign bit.
1962 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1963 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1965 // Extend back to to 64-bits.
1966 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1968 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1970 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1971 const SDValue FractMask
1972 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1974 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1975 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1976 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1978 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1980 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1982 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1983 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1985 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1986 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1988 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1991 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1993 SDValue Src = Op.getOperand(0);
1995 assert(Op.getValueType() == MVT::f64);
1997 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1998 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1999 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
2001 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
2002 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
2004 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2006 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
2007 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
2009 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
2010 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2012 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2015 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2016 // FNEARBYINT and FRINT are the same, except in their handling of FP
2017 // exceptions. Those aren't really meaningful for us, and OpenCL only has
2018 // rint, so just treat them as equivalent.
2019 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2022 // XXX - May require not supporting f32 denormals?
2023 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {
2025 SDValue X = Op.getOperand(0);
2027 SDValue T = DAG.getNode(ISD::FTRUNC, SL, MVT::f32, X);
2029 SDValue Diff = DAG.getNode(ISD::FSUB, SL, MVT::f32, X, T);
2031 SDValue AbsDiff = DAG.getNode(ISD::FABS, SL, MVT::f32, Diff);
2033 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f32);
2034 const SDValue One = DAG.getConstantFP(1.0, MVT::f32);
2035 const SDValue Half = DAG.getConstantFP(0.5, MVT::f32);
2037 SDValue SignOne = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f32, One, X);
2039 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f32);
2041 SDValue Cmp = DAG.getSetCC(SL, SetCCVT, AbsDiff, Half, ISD::SETOGE);
2043 SDValue Sel = DAG.getNode(ISD::SELECT, SL, MVT::f32, Cmp, SignOne, Zero);
2045 return DAG.getNode(ISD::FADD, SL, MVT::f32, T, Sel);
2048 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
2050 SDValue X = Op.getOperand(0);
2052 SDValue L = DAG.getNode(ISD::BITCAST, SL, MVT::i64, X);
2054 const SDValue Zero = DAG.getConstant(0, MVT::i32);
2055 const SDValue One = DAG.getConstant(1, MVT::i32);
2056 const SDValue NegOne = DAG.getConstant(-1, MVT::i32);
2057 const SDValue FiftyOne = DAG.getConstant(51, MVT::i32);
2058 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
2061 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2063 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, One);
2065 SDValue Exp = extractF64Exponent(Hi, SL, DAG);
2067 const SDValue Mask = DAG.getConstant(INT64_C(0x000fffffffffffff), MVT::i64);
2069 SDValue M = DAG.getNode(ISD::SRA, SL, MVT::i64, Mask, Exp);
2070 SDValue D = DAG.getNode(ISD::SRA, SL, MVT::i64,
2071 DAG.getConstant(INT64_C(0x0008000000000000), MVT::i64),
2074 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, L, M);
2075 SDValue Tmp1 = DAG.getSetCC(SL, SetCCVT,
2076 DAG.getConstant(0, MVT::i64), Tmp0,
2079 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, Tmp1,
2080 D, DAG.getConstant(0, MVT::i64));
2081 SDValue K = DAG.getNode(ISD::ADD, SL, MVT::i64, L, Tmp2);
2083 K = DAG.getNode(ISD::AND, SL, MVT::i64, K, DAG.getNOT(SL, M, MVT::i64));
2084 K = DAG.getNode(ISD::BITCAST, SL, MVT::f64, K);
2086 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
2087 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
2088 SDValue ExpEqNegOne = DAG.getSetCC(SL, SetCCVT, NegOne, Exp, ISD::SETEQ);
2090 SDValue Mag = DAG.getNode(ISD::SELECT, SL, MVT::f64,
2092 DAG.getConstantFP(1.0, MVT::f64),
2093 DAG.getConstantFP(0.0, MVT::f64));
2095 SDValue S = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, Mag, X);
2097 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpLt0, S, K);
2098 K = DAG.getNode(ISD::SELECT, SL, MVT::f64, ExpGt51, X, K);
2103 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
2104 EVT VT = Op.getValueType();
2107 return LowerFROUND32(Op, DAG);
2110 return LowerFROUND64(Op, DAG);
2112 llvm_unreachable("unhandled type");
2115 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2117 SDValue Src = Op.getOperand(0);
2119 // result = trunc(src);
2120 // if (src < 0.0 && src != result)
2123 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2125 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
2126 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
2128 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
2130 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2131 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2132 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2134 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2135 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2138 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2139 bool Signed) const {
2141 SDValue Src = Op.getOperand(0);
2143 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2145 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2146 DAG.getConstant(0, MVT::i32));
2147 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2148 DAG.getConstant(1, MVT::i32));
2150 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2153 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2155 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2156 DAG.getConstant(32, MVT::i32));
2158 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2161 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2162 SelectionDAG &DAG) const {
2163 SDValue S0 = Op.getOperand(0);
2164 if (S0.getValueType() != MVT::i64)
2167 EVT DestVT = Op.getValueType();
2168 if (DestVT == MVT::f64)
2169 return LowerINT_TO_FP64(Op, DAG, false);
2171 assert(DestVT == MVT::f32);
2175 // f32 uint_to_fp i64
2176 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2177 DAG.getConstant(0, MVT::i32));
2178 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
2179 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2180 DAG.getConstant(1, MVT::i32));
2181 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
2182 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
2183 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
2184 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
2187 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2188 SelectionDAG &DAG) const {
2189 SDValue Src = Op.getOperand(0);
2190 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
2191 return LowerINT_TO_FP64(Op, DAG, true);
2196 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2197 bool Signed) const {
2200 SDValue Src = Op.getOperand(0);
2202 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2205 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), MVT::f64);
2207 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), MVT::f64);
2209 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2211 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2214 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2216 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2217 MVT::i32, FloorMul);
2218 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2220 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
2222 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2225 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2226 SelectionDAG &DAG) const {
2227 SDValue Src = Op.getOperand(0);
2229 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2230 return LowerFP64_TO_INT(Op, DAG, true);
2235 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2236 SelectionDAG &DAG) const {
2237 SDValue Src = Op.getOperand(0);
2239 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2240 return LowerFP64_TO_INT(Op, DAG, false);
2245 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2246 SelectionDAG &DAG) const {
2247 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2248 MVT VT = Op.getSimpleValueType();
2249 MVT ScalarVT = VT.getScalarType();
2254 SDValue Src = Op.getOperand(0);
2257 // TODO: Don't scalarize on Evergreen?
2258 unsigned NElts = VT.getVectorNumElements();
2259 SmallVector<SDValue, 8> Args;
2260 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2262 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2263 for (unsigned I = 0; I < NElts; ++I)
2264 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2266 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2269 //===----------------------------------------------------------------------===//
2270 // Custom DAG optimizations
2271 //===----------------------------------------------------------------------===//
2273 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2274 APInt KnownZero, KnownOne;
2275 EVT VT = Op.getValueType();
2276 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2278 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2281 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2282 EVT VT = Op.getValueType();
2284 // In order for this to be a signed 24-bit value, bit 23, must
2286 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2287 // as unsigned 24-bit values.
2288 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2291 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2293 SelectionDAG &DAG = DCI.DAG;
2294 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2295 EVT VT = Op.getValueType();
2297 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2298 APInt KnownZero, KnownOne;
2299 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2300 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2301 DCI.CommitTargetLoweringOpt(TLO);
2304 template <typename IntTy>
2305 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2306 uint32_t Offset, uint32_t Width) {
2307 if (Width + Offset < 32) {
2308 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2309 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2310 return DAG.getConstant(Result, MVT::i32);
2313 return DAG.getConstant(Src0 >> Offset, MVT::i32);
2316 static bool usesAllNormalStores(SDNode *LoadVal) {
2317 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2318 if (!ISD::isNormalStore(*I))
2325 // If we have a copy of an illegal type, replace it with a load / store of an
2326 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2327 // instructions emitted when handling extloads and truncstores. Ideally we could
2328 // recognize the pack / unpack pattern to eliminate it.
2329 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2330 DAGCombinerInfo &DCI) const {
2331 if (!DCI.isBeforeLegalize())
2334 StoreSDNode *SN = cast<StoreSDNode>(N);
2335 SDValue Value = SN->getValue();
2336 EVT VT = Value.getValueType();
2338 if (isTypeLegal(VT) || SN->isVolatile() ||
2339 !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2342 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2343 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2346 EVT MemVT = LoadVal->getMemoryVT();
2349 SelectionDAG &DAG = DCI.DAG;
2350 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2352 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2354 LoadVal->getChain(),
2355 LoadVal->getBasePtr(),
2356 LoadVal->getOffset(),
2358 LoadVal->getMemOperand());
2360 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2361 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2363 return DAG.getStore(SN->getChain(), SL, NewLoad,
2364 SN->getBasePtr(), SN->getMemOperand());
2367 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2368 DAGCombinerInfo &DCI) const {
2369 EVT VT = N->getValueType(0);
2371 if (VT.isVector() || VT.getSizeInBits() > 32)
2374 SelectionDAG &DAG = DCI.DAG;
2377 SDValue N0 = N->getOperand(0);
2378 SDValue N1 = N->getOperand(1);
2381 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2382 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2383 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2384 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2385 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2386 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2387 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2388 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2393 // We need to use sext even for MUL_U24, because MUL_U24 is used
2394 // for signed multiply of 8 and 16-bit types.
2395 return DAG.getSExtOrTrunc(Mul, DL, VT);
2398 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2399 DAGCombinerInfo &DCI) const {
2400 SelectionDAG &DAG = DCI.DAG;
2403 switch(N->getOpcode()) {
2406 return performMulCombine(N, DCI);
2407 case AMDGPUISD::MUL_I24:
2408 case AMDGPUISD::MUL_U24: {
2409 SDValue N0 = N->getOperand(0);
2410 SDValue N1 = N->getOperand(1);
2411 simplifyI24(N0, DCI);
2412 simplifyI24(N1, DCI);
2416 SDValue Cond = N->getOperand(0);
2417 if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) {
2419 EVT VT = N->getValueType(0);
2420 SDValue LHS = Cond.getOperand(0);
2421 SDValue RHS = Cond.getOperand(1);
2422 SDValue CC = Cond.getOperand(2);
2424 SDValue True = N->getOperand(1);
2425 SDValue False = N->getOperand(2);
2428 return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
2430 // TODO: Implement min / max Evergreen instructions.
2431 if (VT == MVT::i32 &&
2432 Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
2433 return CombineIMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
2439 case AMDGPUISD::BFE_I32:
2440 case AMDGPUISD::BFE_U32: {
2441 assert(!N->getValueType(0).isVector() &&
2442 "Vector handling of BFE not implemented");
2443 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2447 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2449 return DAG.getConstant(0, MVT::i32);
2451 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2455 SDValue BitsFrom = N->getOperand(0);
2456 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2458 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2460 if (OffsetVal == 0) {
2461 // This is already sign / zero extended, so try to fold away extra BFEs.
2462 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2464 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2465 if (OpSignBits >= SignBits)
2468 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2470 // This is a sign_extend_inreg. Replace it to take advantage of existing
2471 // DAG Combines. If not eliminated, we will match back to BFE during
2474 // TODO: The sext_inreg of extended types ends, although we can could
2475 // handle them in a single BFE.
2476 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2477 DAG.getValueType(SmallVT));
2480 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2483 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2485 return constantFoldBFE<int32_t>(DAG,
2486 CVal->getSExtValue(),
2491 return constantFoldBFE<uint32_t>(DAG,
2492 CVal->getZExtValue(),
2497 if ((OffsetVal + WidthVal) >= 32) {
2498 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
2499 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2500 BitsFrom, ShiftVal);
2503 if (BitsFrom.hasOneUse()) {
2504 APInt Demanded = APInt::getBitsSet(32,
2506 OffsetVal + WidthVal);
2508 APInt KnownZero, KnownOne;
2509 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2510 !DCI.isBeforeLegalizeOps());
2511 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2512 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2513 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2514 KnownZero, KnownOne, TLO)) {
2515 DCI.CommitTargetLoweringOpt(TLO);
2523 return performStoreCombine(N, DCI);
2528 //===----------------------------------------------------------------------===//
2530 //===----------------------------------------------------------------------===//
2532 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2535 const SmallVectorImpl<ISD::InputArg> &Ins,
2536 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2538 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2539 if (Ins[i].ArgVT == Ins[i].VT) {
2540 OrigIns.push_back(Ins[i]);
2545 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2546 // Vector has been split into scalars.
2547 VT = Ins[i].ArgVT.getVectorElementType();
2548 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2549 Ins[i].ArgVT.getVectorElementType() !=
2550 Ins[i].VT.getVectorElementType()) {
2551 // Vector elements have been promoted
2554 // Vector has been spilt into smaller vectors.
2558 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2559 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2560 OrigIns.push_back(Arg);
2564 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2565 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2566 return CFP->isExactlyValue(1.0);
2568 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2569 return C->isAllOnesValue();
2574 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2575 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2576 return CFP->getValueAPF().isZero();
2578 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2579 return C->isNullValue();
2584 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2585 const TargetRegisterClass *RC,
2586 unsigned Reg, EVT VT) const {
2587 MachineFunction &MF = DAG.getMachineFunction();
2588 MachineRegisterInfo &MRI = MF.getRegInfo();
2589 unsigned VirtualRegister;
2590 if (!MRI.isLiveIn(Reg)) {
2591 VirtualRegister = MRI.createVirtualRegister(RC);
2592 MRI.addLiveIn(Reg, VirtualRegister);
2594 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2596 return DAG.getRegister(VirtualRegister, VT);
2599 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2601 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2603 default: return nullptr;
2605 NODE_NAME_CASE(CALL);
2606 NODE_NAME_CASE(UMUL);
2607 NODE_NAME_CASE(RET_FLAG);
2608 NODE_NAME_CASE(BRANCH_COND);
2611 NODE_NAME_CASE(DWORDADDR)
2612 NODE_NAME_CASE(FRACT)
2613 NODE_NAME_CASE(CLAMP)
2615 NODE_NAME_CASE(FMAX_LEGACY)
2616 NODE_NAME_CASE(SMAX)
2617 NODE_NAME_CASE(UMAX)
2618 NODE_NAME_CASE(FMIN_LEGACY)
2619 NODE_NAME_CASE(SMIN)
2620 NODE_NAME_CASE(UMIN)
2621 NODE_NAME_CASE(FMAX3)
2622 NODE_NAME_CASE(SMAX3)
2623 NODE_NAME_CASE(UMAX3)
2624 NODE_NAME_CASE(FMIN3)
2625 NODE_NAME_CASE(SMIN3)
2626 NODE_NAME_CASE(UMIN3)
2627 NODE_NAME_CASE(URECIP)
2628 NODE_NAME_CASE(DIV_SCALE)
2629 NODE_NAME_CASE(DIV_FMAS)
2630 NODE_NAME_CASE(DIV_FIXUP)
2631 NODE_NAME_CASE(TRIG_PREOP)
2634 NODE_NAME_CASE(RSQ_LEGACY)
2635 NODE_NAME_CASE(RSQ_CLAMPED)
2636 NODE_NAME_CASE(LDEXP)
2637 NODE_NAME_CASE(FP_CLASS)
2638 NODE_NAME_CASE(DOT4)
2639 NODE_NAME_CASE(BFE_U32)
2640 NODE_NAME_CASE(BFE_I32)
2643 NODE_NAME_CASE(BREV)
2644 NODE_NAME_CASE(MUL_U24)
2645 NODE_NAME_CASE(MUL_I24)
2646 NODE_NAME_CASE(MAD_U24)
2647 NODE_NAME_CASE(MAD_I24)
2648 NODE_NAME_CASE(EXPORT)
2649 NODE_NAME_CASE(CONST_ADDRESS)
2650 NODE_NAME_CASE(REGISTER_LOAD)
2651 NODE_NAME_CASE(REGISTER_STORE)
2652 NODE_NAME_CASE(LOAD_CONSTANT)
2653 NODE_NAME_CASE(LOAD_INPUT)
2654 NODE_NAME_CASE(SAMPLE)
2655 NODE_NAME_CASE(SAMPLEB)
2656 NODE_NAME_CASE(SAMPLED)
2657 NODE_NAME_CASE(SAMPLEL)
2658 NODE_NAME_CASE(CVT_F32_UBYTE0)
2659 NODE_NAME_CASE(CVT_F32_UBYTE1)
2660 NODE_NAME_CASE(CVT_F32_UBYTE2)
2661 NODE_NAME_CASE(CVT_F32_UBYTE3)
2662 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2663 NODE_NAME_CASE(CONST_DATA_PTR)
2664 NODE_NAME_CASE(STORE_MSKOR)
2665 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2669 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2670 DAGCombinerInfo &DCI,
2671 unsigned &RefinementSteps,
2672 bool &UseOneConstNR) const {
2673 SelectionDAG &DAG = DCI.DAG;
2674 EVT VT = Operand.getValueType();
2676 if (VT == MVT::f32) {
2677 RefinementSteps = 0;
2678 return DAG.getNode(AMDGPUISD::RSQ, SDLoc(Operand), VT, Operand);
2681 // TODO: There is also f64 rsq instruction, but the documentation is less
2682 // clear on its precision.
2687 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2688 DAGCombinerInfo &DCI,
2689 unsigned &RefinementSteps) const {
2690 SelectionDAG &DAG = DCI.DAG;
2691 EVT VT = Operand.getValueType();
2693 if (VT == MVT::f32) {
2694 // Reciprocal, < 1 ulp error.
2696 // This reciprocal approximation converges to < 0.5 ulp error with one
2697 // newton rhapson performed with two fused multiple adds (FMAs).
2699 RefinementSteps = 0;
2700 return DAG.getNode(AMDGPUISD::RCP, SDLoc(Operand), VT, Operand);
2703 // TODO: There is also f64 rcp instruction, but the documentation is less
2704 // clear on its precision.
2709 static void computeKnownBitsForMinMax(const SDValue Op0,
2713 const SelectionDAG &DAG,
2715 APInt Op0Zero, Op0One;
2716 APInt Op1Zero, Op1One;
2717 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2718 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2720 KnownZero = Op0Zero & Op1Zero;
2721 KnownOne = Op0One & Op1One;
2724 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2728 const SelectionDAG &DAG,
2729 unsigned Depth) const {
2731 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2735 unsigned Opc = Op.getOpcode();
2740 case ISD::INTRINSIC_WO_CHAIN: {
2741 // FIXME: The intrinsic should just use the node.
2742 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2743 case AMDGPUIntrinsic::AMDGPU_imax:
2744 case AMDGPUIntrinsic::AMDGPU_umax:
2745 case AMDGPUIntrinsic::AMDGPU_imin:
2746 case AMDGPUIntrinsic::AMDGPU_umin:
2747 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2748 KnownZero, KnownOne, DAG, Depth);
2756 case AMDGPUISD::SMAX:
2757 case AMDGPUISD::UMAX:
2758 case AMDGPUISD::SMIN:
2759 case AMDGPUISD::UMIN:
2760 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2761 KnownZero, KnownOne, DAG, Depth);
2764 case AMDGPUISD::BFE_I32:
2765 case AMDGPUISD::BFE_U32: {
2766 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2770 unsigned BitWidth = 32;
2771 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2773 if (Opc == AMDGPUISD::BFE_U32)
2774 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2781 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2783 const SelectionDAG &DAG,
2784 unsigned Depth) const {
2785 switch (Op.getOpcode()) {
2786 case AMDGPUISD::BFE_I32: {
2787 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2791 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2792 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2793 if (!Offset || !Offset->isNullValue())
2796 // TODO: Could probably figure something out with non-0 offsets.
2797 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2798 return std::max(SignBits, Op0SignBits);
2801 case AMDGPUISD::BFE_U32: {
2802 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2803 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;