1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
108 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
110 setOperationAction(ISD::Constant, MVT::i32, Legal);
111 setOperationAction(ISD::Constant, MVT::i64, Legal);
112 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
113 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
115 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
116 setOperationAction(ISD::BRIND, MVT::Other, Expand);
118 // We need to custom lower some of the intrinsics
119 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
121 // Library functions. These default to Expand, but we have instructions
123 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
124 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
125 setOperationAction(ISD::FPOW, MVT::f32, Legal);
126 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
127 setOperationAction(ISD::FABS, MVT::f32, Legal);
128 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
129 setOperationAction(ISD::FRINT, MVT::f32, Legal);
130 setOperationAction(ISD::FROUND, MVT::f32, Legal);
131 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
133 setOperationAction(ISD::FREM, MVT::f32, Custom);
134 setOperationAction(ISD::FREM, MVT::f64, Custom);
136 // Lower floating point store/load to integer store/load to reduce the number
137 // of patterns in tablegen.
138 setOperationAction(ISD::STORE, MVT::f32, Promote);
139 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
141 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
142 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
144 setOperationAction(ISD::STORE, MVT::i64, Promote);
145 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
147 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
148 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
150 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
153 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
154 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
156 setOperationAction(ISD::STORE, MVT::f64, Promote);
157 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
159 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
160 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
162 // Custom lowering of vector stores is required for local address space
164 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
165 // XXX: Native v2i32 local address space stores are possible, but not
166 // currently implemented.
167 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
169 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
170 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
171 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
173 // XXX: This can be change to Custom, once ExpandVectorStores can
174 // handle 64-bit stores.
175 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
177 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
178 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
179 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
180 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
181 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
184 setOperationAction(ISD::LOAD, MVT::f32, Promote);
185 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
187 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
190 setOperationAction(ISD::LOAD, MVT::i64, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
193 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
196 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
199 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
200 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
202 setOperationAction(ISD::LOAD, MVT::f64, Promote);
203 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
205 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
206 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
210 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
211 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
216 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
217 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
219 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
220 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
221 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
222 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
223 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
224 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
225 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
226 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
227 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
228 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
229 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
230 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
232 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
234 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
235 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
236 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
237 setOperationAction(ISD::FRINT, MVT::f64, Custom);
238 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
241 if (!Subtarget->hasBFI()) {
242 // fcopysign can be done in a single instruction with BFI.
243 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
244 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
247 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
249 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
250 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
251 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
253 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
254 for (MVT VT : ScalarIntVTs) {
255 setOperationAction(ISD::SREM, VT, Expand);
256 setOperationAction(ISD::SDIV, VT, Expand);
258 // GPU does not have divrem function for signed or unsigned.
259 setOperationAction(ISD::SDIVREM, VT, Custom);
260 setOperationAction(ISD::UDIVREM, VT, Custom);
262 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
263 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
264 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
266 setOperationAction(ISD::BSWAP, VT, Expand);
267 setOperationAction(ISD::CTTZ, VT, Expand);
268 setOperationAction(ISD::CTLZ, VT, Expand);
271 if (!Subtarget->hasBCNT(32))
272 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
274 if (!Subtarget->hasBCNT(64))
275 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
277 // The hardware supports 32-bit ROTR, but not ROTL.
278 setOperationAction(ISD::ROTL, MVT::i32, Expand);
279 setOperationAction(ISD::ROTL, MVT::i64, Expand);
280 setOperationAction(ISD::ROTR, MVT::i64, Expand);
282 setOperationAction(ISD::MUL, MVT::i64, Expand);
283 setOperationAction(ISD::MULHU, MVT::i64, Expand);
284 setOperationAction(ISD::MULHS, MVT::i64, Expand);
285 setOperationAction(ISD::UDIV, MVT::i32, Expand);
286 setOperationAction(ISD::UREM, MVT::i32, Expand);
287 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
288 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
289 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
290 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
291 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
293 if (!Subtarget->hasFFBH())
294 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
296 if (!Subtarget->hasFFBL())
297 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
299 static const MVT::SimpleValueType VectorIntTypes[] = {
300 MVT::v2i32, MVT::v4i32
303 for (MVT VT : VectorIntTypes) {
304 // Expand the following operations for the current type by default.
305 setOperationAction(ISD::ADD, VT, Expand);
306 setOperationAction(ISD::AND, VT, Expand);
307 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
308 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
309 setOperationAction(ISD::MUL, VT, Expand);
310 setOperationAction(ISD::OR, VT, Expand);
311 setOperationAction(ISD::SHL, VT, Expand);
312 setOperationAction(ISD::SRA, VT, Expand);
313 setOperationAction(ISD::SRL, VT, Expand);
314 setOperationAction(ISD::ROTL, VT, Expand);
315 setOperationAction(ISD::ROTR, VT, Expand);
316 setOperationAction(ISD::SUB, VT, Expand);
317 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
318 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
319 setOperationAction(ISD::SDIV, VT, Expand);
320 setOperationAction(ISD::UDIV, VT, Expand);
321 setOperationAction(ISD::SREM, VT, Expand);
322 setOperationAction(ISD::UREM, VT, Expand);
323 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
324 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
325 setOperationAction(ISD::SDIVREM, VT, Custom);
326 setOperationAction(ISD::UDIVREM, VT, Custom);
327 setOperationAction(ISD::ADDC, VT, Expand);
328 setOperationAction(ISD::SUBC, VT, Expand);
329 setOperationAction(ISD::ADDE, VT, Expand);
330 setOperationAction(ISD::SUBE, VT, Expand);
331 setOperationAction(ISD::SELECT, VT, Expand);
332 setOperationAction(ISD::VSELECT, VT, Expand);
333 setOperationAction(ISD::SELECT_CC, VT, Expand);
334 setOperationAction(ISD::XOR, VT, Expand);
335 setOperationAction(ISD::BSWAP, VT, Expand);
336 setOperationAction(ISD::CTPOP, VT, Expand);
337 setOperationAction(ISD::CTTZ, VT, Expand);
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
339 setOperationAction(ISD::CTLZ, VT, Expand);
340 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
341 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
344 static const MVT::SimpleValueType FloatVectorTypes[] = {
345 MVT::v2f32, MVT::v4f32
348 for (MVT VT : FloatVectorTypes) {
349 setOperationAction(ISD::FABS, VT, Expand);
350 setOperationAction(ISD::FMINNUM, VT, Expand);
351 setOperationAction(ISD::FMAXNUM, VT, Expand);
352 setOperationAction(ISD::FADD, VT, Expand);
353 setOperationAction(ISD::FCEIL, VT, Expand);
354 setOperationAction(ISD::FCOS, VT, Expand);
355 setOperationAction(ISD::FDIV, VT, Expand);
356 setOperationAction(ISD::FEXP2, VT, Expand);
357 setOperationAction(ISD::FLOG2, VT, Expand);
358 setOperationAction(ISD::FREM, VT, Expand);
359 setOperationAction(ISD::FPOW, VT, Expand);
360 setOperationAction(ISD::FFLOOR, VT, Expand);
361 setOperationAction(ISD::FTRUNC, VT, Expand);
362 setOperationAction(ISD::FMUL, VT, Expand);
363 setOperationAction(ISD::FMA, VT, Expand);
364 setOperationAction(ISD::FRINT, VT, Expand);
365 setOperationAction(ISD::FNEARBYINT, VT, Expand);
366 setOperationAction(ISD::FSQRT, VT, Expand);
367 setOperationAction(ISD::FSIN, VT, Expand);
368 setOperationAction(ISD::FSUB, VT, Expand);
369 setOperationAction(ISD::FNEG, VT, Expand);
370 setOperationAction(ISD::SELECT, VT, Expand);
371 setOperationAction(ISD::VSELECT, VT, Expand);
372 setOperationAction(ISD::SELECT_CC, VT, Expand);
373 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
374 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
377 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
378 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
380 setTargetDAGCombine(ISD::MUL);
381 setTargetDAGCombine(ISD::SELECT);
382 setTargetDAGCombine(ISD::SELECT_CC);
383 setTargetDAGCombine(ISD::STORE);
385 setBooleanContents(ZeroOrNegativeOneBooleanContent);
386 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
388 setSchedulingPreference(Sched::RegPressure);
389 setJumpIsExpensive(true);
391 // SI at least has hardware support for floating point exceptions, but no way
392 // of using or handling them is implemented. They are also optional in OpenCL
394 setHasFloatingPointExceptions(false);
396 setSelectIsExpensive(false);
397 PredictableSelectIsExpensive = false;
399 // There are no integer divide instructions, and these expand to a pretty
400 // large sequence of instructions.
401 setIntDivIsCheap(false);
402 setPow2SDivIsCheap(false);
404 // FIXME: Need to really handle these.
405 MaxStoresPerMemcpy = 4096;
406 MaxStoresPerMemmove = 4096;
407 MaxStoresPerMemset = 4096;
410 //===----------------------------------------------------------------------===//
411 // Target Information
412 //===----------------------------------------------------------------------===//
414 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
418 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
422 // The backend supports 32 and 64 bit floating point immediates.
423 // FIXME: Why are we reporting vectors of FP immediates as legal?
424 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
425 EVT ScalarVT = VT.getScalarType();
426 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
429 // We don't want to shrink f64 / f32 constants.
430 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
431 EVT ScalarVT = VT.getScalarType();
432 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
435 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
439 unsigned NewSize = NewVT.getStoreSizeInBits();
441 // If we are reducing to a 32-bit load, this is always better.
445 EVT OldVT = N->getValueType(0);
446 unsigned OldSize = OldVT.getStoreSizeInBits();
448 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
449 // extloads, so doing one requires using a buffer_load. In cases where we
450 // still couldn't use a scalar load, using the wider load shouldn't really
453 // If the old size already had to be an extload, there's no harm in continuing
454 // to reduce the width.
455 return (OldSize < 32);
458 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
460 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
463 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
464 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
466 return ((LScalarSize <= CastScalarSize) ||
467 (CastScalarSize >= 32) ||
471 //===---------------------------------------------------------------------===//
473 //===---------------------------------------------------------------------===//
475 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
476 assert(VT.isFloatingPoint());
477 return VT == MVT::f32 || VT == MVT::f64;
480 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
481 assert(VT.isFloatingPoint());
482 return VT == MVT::f32 || VT == MVT::f64;
485 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
486 // Truncate is just accessing a subregister.
487 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
490 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
491 // Truncate is just accessing a subregister.
492 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
493 (Dest->getPrimitiveSizeInBits() % 32 == 0);
496 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
497 const DataLayout *DL = getDataLayout();
498 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
499 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
501 return SrcSize == 32 && DestSize == 64;
504 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
505 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
506 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
507 // this will enable reducing 64-bit operations the 32-bit, which is always
509 return Src == MVT::i32 && Dest == MVT::i64;
512 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
513 return isZExtFree(Val.getValueType(), VT2);
516 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
517 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
518 // limited number of native 64-bit operations. Shrinking an operation to fit
519 // in a single 32-bit register should always be helpful. As currently used,
520 // this is much less general than the name suggests, and is only used in
521 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
522 // not profitable, and may actually be harmful.
523 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
526 //===---------------------------------------------------------------------===//
527 // TargetLowering Callbacks
528 //===---------------------------------------------------------------------===//
530 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
531 const SmallVectorImpl<ISD::InputArg> &Ins) const {
533 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
536 SDValue AMDGPUTargetLowering::LowerReturn(
538 CallingConv::ID CallConv,
540 const SmallVectorImpl<ISD::OutputArg> &Outs,
541 const SmallVectorImpl<SDValue> &OutVals,
542 SDLoc DL, SelectionDAG &DAG) const {
543 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
546 //===---------------------------------------------------------------------===//
547 // Target specific lowering
548 //===---------------------------------------------------------------------===//
550 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
551 SmallVectorImpl<SDValue> &InVals) const {
552 SDValue Callee = CLI.Callee;
553 SelectionDAG &DAG = CLI.DAG;
555 const Function &Fn = *DAG.getMachineFunction().getFunction();
557 StringRef FuncName("<unknown>");
559 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
560 FuncName = G->getSymbol();
561 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
562 FuncName = G->getGlobal()->getName();
564 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
565 DAG.getContext()->diagnose(NoCalls);
569 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
570 SelectionDAG &DAG) const {
571 switch (Op.getOpcode()) {
573 Op.getNode()->dump();
574 llvm_unreachable("Custom lowering code for this"
575 "instruction is not implemented yet!");
577 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
578 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
579 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
580 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
581 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
582 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
583 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
584 case ISD::FREM: return LowerFREM(Op, DAG);
585 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
586 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
587 case ISD::FRINT: return LowerFRINT(Op, DAG);
588 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
589 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
590 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
591 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
592 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
593 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
598 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
599 SmallVectorImpl<SDValue> &Results,
600 SelectionDAG &DAG) const {
601 switch (N->getOpcode()) {
602 case ISD::SIGN_EXTEND_INREG:
603 // Different parts of legalization seem to interpret which type of
604 // sign_extend_inreg is the one to check for custom lowering. The extended
605 // from type is what really matters, but some places check for custom
606 // lowering of the result type. This results in trying to use
607 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
608 // nothing here and let the illegal result integer be handled normally.
611 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
615 Results.push_back(SDValue(Node, 0));
616 Results.push_back(SDValue(Node, 1));
617 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
619 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
623 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
624 if (Lowered.getNode())
625 Results.push_back(Lowered);
633 // FIXME: This implements accesses to initialized globals in the constant
634 // address space by copying them to private and accessing that. It does not
635 // properly handle illegal types or vectors. The private vector loads are not
636 // scalarized, and the illegal scalars hit an assertion. This technique will not
637 // work well with large initializers, and this should eventually be
638 // removed. Initialized globals should be placed into a data section that the
639 // runtime will load into a buffer before the kernel is executed. Uses of the
640 // global need to be replaced with a pointer loaded from an implicit kernel
641 // argument into this buffer holding the copy of the data, which will remove the
642 // need for any of this.
643 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
644 const GlobalValue *GV,
645 const SDValue &InitPtr,
647 SelectionDAG &DAG) const {
648 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
650 Type *InitTy = Init->getType();
652 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
653 EVT VT = EVT::getEVT(InitTy);
654 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
655 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
656 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
657 TD->getPrefTypeAlignment(InitTy));
660 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
661 EVT VT = EVT::getEVT(CFP->getType());
662 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
663 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
664 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
665 TD->getPrefTypeAlignment(CFP->getType()));
668 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
669 const StructLayout *SL = TD->getStructLayout(ST);
671 EVT PtrVT = InitPtr.getValueType();
672 SmallVector<SDValue, 8> Chains;
674 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
675 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
676 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
678 Constant *Elt = Init->getAggregateElement(I);
679 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
682 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
685 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
686 EVT PtrVT = InitPtr.getValueType();
688 unsigned NumElements;
689 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
690 NumElements = AT->getNumElements();
691 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
692 NumElements = VT->getNumElements();
694 llvm_unreachable("Unexpected type");
696 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
697 SmallVector<SDValue, 8> Chains;
698 for (unsigned i = 0; i < NumElements; ++i) {
699 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
700 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
702 Constant *Elt = Init->getAggregateElement(i);
703 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
706 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
709 if (isa<UndefValue>(Init)) {
710 EVT VT = EVT::getEVT(InitTy);
711 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
712 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
713 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
714 TD->getPrefTypeAlignment(InitTy));
718 llvm_unreachable("Unhandled constant initializer");
721 static bool hasDefinedInitializer(const GlobalValue *GV) {
722 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
723 if (!GVar || !GVar->hasInitializer())
726 if (isa<UndefValue>(GVar->getInitializer()))
732 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
734 SelectionDAG &DAG) const {
736 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
737 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
738 const GlobalValue *GV = G->getGlobal();
740 switch (G->getAddressSpace()) {
741 case AMDGPUAS::LOCAL_ADDRESS: {
742 // XXX: What does the value of G->getOffset() mean?
743 assert(G->getOffset() == 0 &&
744 "Do not know what to do with an non-zero offset");
746 // TODO: We could emit code to handle the initialization somewhere.
747 if (hasDefinedInitializer(GV))
751 if (MFI->LocalMemoryObjects.count(GV) == 0) {
752 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
753 Offset = MFI->LDSSize;
754 MFI->LocalMemoryObjects[GV] = Offset;
755 // XXX: Account for alignment?
756 MFI->LDSSize += Size;
758 Offset = MFI->LocalMemoryObjects[GV];
761 return DAG.getConstant(Offset, getPointerTy(AMDGPUAS::LOCAL_ADDRESS));
763 case AMDGPUAS::CONSTANT_ADDRESS: {
764 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
765 Type *EltType = GV->getType()->getElementType();
766 unsigned Size = TD->getTypeAllocSize(EltType);
767 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
769 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
770 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
772 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
773 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
775 const GlobalVariable *Var = cast<GlobalVariable>(GV);
776 if (!Var->hasInitializer()) {
777 // This has no use, but bugpoint will hit it.
778 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
781 const Constant *Init = Var->getInitializer();
782 SmallVector<SDNode*, 8> WorkList;
784 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
785 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
786 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
788 WorkList.push_back(*I);
790 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
791 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
792 E = WorkList.end(); I != E; ++I) {
793 SmallVector<SDValue, 8> Ops;
794 Ops.push_back(Chain);
795 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
796 Ops.push_back((*I)->getOperand(i));
798 DAG.UpdateNodeOperands(*I, Ops);
800 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
804 const Function &Fn = *DAG.getMachineFunction().getFunction();
805 DiagnosticInfoUnsupported BadInit(Fn,
806 "initializer for address space");
807 DAG.getContext()->diagnose(BadInit);
811 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
812 SelectionDAG &DAG) const {
813 SmallVector<SDValue, 8> Args;
814 SDValue A = Op.getOperand(0);
815 SDValue B = Op.getOperand(1);
817 DAG.ExtractVectorElements(A, Args);
818 DAG.ExtractVectorElements(B, Args);
820 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
823 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
824 SelectionDAG &DAG) const {
826 SmallVector<SDValue, 8> Args;
827 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
828 EVT VT = Op.getValueType();
829 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
830 VT.getVectorNumElements());
832 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
835 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
836 SelectionDAG &DAG) const {
838 MachineFunction &MF = DAG.getMachineFunction();
839 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
840 getTargetMachine().getSubtargetImpl()->getFrameLowering());
842 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
844 unsigned FrameIndex = FIN->getIndex();
845 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
846 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
850 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
851 SelectionDAG &DAG) const {
852 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
854 EVT VT = Op.getValueType();
856 switch (IntrinsicID) {
858 case AMDGPUIntrinsic::AMDGPU_abs:
859 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
860 return LowerIntrinsicIABS(Op, DAG);
861 case AMDGPUIntrinsic::AMDGPU_lrp:
862 return LowerIntrinsicLRP(Op, DAG);
863 case AMDGPUIntrinsic::AMDGPU_fract:
864 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
865 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
867 case AMDGPUIntrinsic::AMDGPU_clamp:
868 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
869 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
870 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
872 case Intrinsic::AMDGPU_div_scale: {
873 // 3rd parameter required to be a constant.
874 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
876 return DAG.getUNDEF(VT);
878 // Translate to the operands expected by the machine instruction. The
879 // first parameter must be the same as the first instruction.
880 SDValue Numerator = Op.getOperand(1);
881 SDValue Denominator = Op.getOperand(2);
883 // Note this order is opposite of the machine instruction's operations,
884 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
885 // intrinsic has the numerator as the first operand to match a normal
886 // division operation.
888 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
890 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
891 Denominator, Numerator);
894 case Intrinsic::AMDGPU_div_fmas:
895 // FIXME: Dropping bool parameter. Work is needed to support the implicit
897 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
898 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
900 case Intrinsic::AMDGPU_div_fixup:
901 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
902 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
904 case Intrinsic::AMDGPU_trig_preop:
905 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
906 Op.getOperand(1), Op.getOperand(2));
908 case Intrinsic::AMDGPU_rcp:
909 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
911 case Intrinsic::AMDGPU_rsq:
912 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
914 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
915 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
917 case Intrinsic::AMDGPU_rsq_clamped:
918 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
919 Type *Type = VT.getTypeForEVT(*DAG.getContext());
920 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
921 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
923 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
924 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
925 DAG.getConstantFP(Max, VT));
926 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
927 DAG.getConstantFP(Min, VT));
929 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
932 case Intrinsic::AMDGPU_ldexp:
933 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
936 case AMDGPUIntrinsic::AMDGPU_imax:
937 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
939 case AMDGPUIntrinsic::AMDGPU_umax:
940 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
942 case AMDGPUIntrinsic::AMDGPU_imin:
943 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
945 case AMDGPUIntrinsic::AMDGPU_umin:
946 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
949 case AMDGPUIntrinsic::AMDGPU_umul24:
950 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
951 Op.getOperand(1), Op.getOperand(2));
953 case AMDGPUIntrinsic::AMDGPU_imul24:
954 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
955 Op.getOperand(1), Op.getOperand(2));
957 case AMDGPUIntrinsic::AMDGPU_umad24:
958 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
959 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
961 case AMDGPUIntrinsic::AMDGPU_imad24:
962 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
963 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
965 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
966 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
968 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
969 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
971 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
972 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
974 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
975 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
977 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
978 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
983 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
984 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
989 case AMDGPUIntrinsic::AMDGPU_bfi:
990 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
995 case AMDGPUIntrinsic::AMDGPU_bfm:
996 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
1000 case AMDGPUIntrinsic::AMDGPU_brev:
1001 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
1003 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
1004 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
1006 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
1007 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
1008 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
1009 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
1013 ///IABS(a) = SMAX(sub(0, a), a)
1014 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
1015 SelectionDAG &DAG) const {
1017 EVT VT = Op.getValueType();
1018 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1021 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
1024 /// Linear Interpolation
1025 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
1026 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
1027 SelectionDAG &DAG) const {
1029 EVT VT = Op.getValueType();
1030 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
1031 DAG.getConstantFP(1.0f, MVT::f32),
1033 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
1035 return DAG.getNode(ISD::FADD, DL, VT,
1036 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1040 /// \brief Generate Min/Max node
1041 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
1048 DAGCombinerInfo &DCI) const {
1049 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1052 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1055 SelectionDAG &DAG = DCI.DAG;
1056 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1065 case ISD::SETFALSE2:
1075 // We will allow this before legalization since we expand unordered compares
1078 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1079 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1085 // Ordered. Assume ordered for undefined.
1087 // Only do this after legalization to avoid interfering with other combines
1088 // which might occur.
1089 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1090 !DCI.isCalledByLegalizer())
1093 // We need to permute the operands to get the correct NaN behavior. The
1094 // selected operand is the second one based on the failing compare with NaN,
1095 // so permute it based on the compare type the hardware uses.
1097 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1098 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1103 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1104 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1110 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1111 !DCI.isCalledByLegalizer())
1115 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1116 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1118 case ISD::SETCC_INVALID:
1119 llvm_unreachable("Invalid setcc condcode!");
1124 /// \brief Generate Min/Max node
1125 SDValue AMDGPUTargetLowering::CombineIMinMax(SDLoc DL,
1132 SelectionDAG &DAG) const {
1133 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1136 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1140 unsigned Opc = (LHS == True) ? AMDGPUISD::UMIN : AMDGPUISD::UMAX;
1141 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1145 unsigned Opc = (LHS == True) ? AMDGPUISD::SMIN : AMDGPUISD::SMAX;
1146 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1150 unsigned Opc = (LHS == True) ? AMDGPUISD::SMAX : AMDGPUISD::SMIN;
1151 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1155 unsigned Opc = (LHS == True) ? AMDGPUISD::UMAX : AMDGPUISD::UMIN;
1156 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1163 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1164 SelectionDAG &DAG) const {
1165 LoadSDNode *Load = cast<LoadSDNode>(Op);
1166 EVT MemVT = Load->getMemoryVT();
1167 EVT MemEltVT = MemVT.getVectorElementType();
1169 EVT LoadVT = Op.getValueType();
1170 EVT EltVT = LoadVT.getVectorElementType();
1171 EVT PtrVT = Load->getBasePtr().getValueType();
1173 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1174 SmallVector<SDValue, 8> Loads;
1175 SmallVector<SDValue, 8> Chains;
1178 unsigned MemEltSize = MemEltVT.getStoreSize();
1179 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1181 for (unsigned i = 0; i < NumElts; ++i) {
1182 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1183 DAG.getConstant(i * MemEltSize, PtrVT));
1186 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1187 Load->getChain(), Ptr,
1188 SrcValue.getWithOffset(i * MemEltSize),
1189 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1190 Load->isInvariant(), Load->getAlignment());
1191 Loads.push_back(NewLoad.getValue(0));
1192 Chains.push_back(NewLoad.getValue(1));
1196 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1197 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1200 return DAG.getMergeValues(Ops, SL);
1203 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1204 SelectionDAG &DAG) const {
1205 EVT VT = Op.getValueType();
1207 // If this is a 2 element vector, we really want to scalarize and not create
1208 // weird 1 element vectors.
1209 if (VT.getVectorNumElements() == 2)
1210 return ScalarizeVectorLoad(Op, DAG);
1212 LoadSDNode *Load = cast<LoadSDNode>(Op);
1213 SDValue BasePtr = Load->getBasePtr();
1214 EVT PtrVT = BasePtr.getValueType();
1215 EVT MemVT = Load->getMemoryVT();
1217 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1220 EVT LoMemVT, HiMemVT;
1223 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1224 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1225 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1227 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1228 Load->getChain(), BasePtr,
1230 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1231 Load->isInvariant(), Load->getAlignment());
1233 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1234 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1237 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1238 Load->getChain(), HiPtr,
1239 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1240 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1241 Load->isInvariant(), Load->getAlignment());
1244 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1245 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1246 LoLoad.getValue(1), HiLoad.getValue(1))
1249 return DAG.getMergeValues(Ops, SL);
1252 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1253 SelectionDAG &DAG) const {
1254 StoreSDNode *Store = cast<StoreSDNode>(Op);
1255 EVT MemVT = Store->getMemoryVT();
1256 unsigned MemBits = MemVT.getSizeInBits();
1258 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1259 // truncating store into an i32 store.
1260 // XXX: We could also handle optimize other vector bitwidths.
1261 if (!MemVT.isVector() || MemBits > 32) {
1266 SDValue Value = Store->getValue();
1267 EVT VT = Value.getValueType();
1268 EVT ElemVT = VT.getVectorElementType();
1269 SDValue Ptr = Store->getBasePtr();
1270 EVT MemEltVT = MemVT.getVectorElementType();
1271 unsigned MemEltBits = MemEltVT.getSizeInBits();
1272 unsigned MemNumElements = MemVT.getVectorNumElements();
1273 unsigned PackedSize = MemVT.getStoreSizeInBits();
1274 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1276 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1278 SDValue PackedValue;
1279 for (unsigned i = 0; i < MemNumElements; ++i) {
1280 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1281 DAG.getConstant(i, MVT::i32));
1282 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1283 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1285 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1286 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1291 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1295 if (PackedSize < 32) {
1296 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1297 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1298 Store->getMemOperand()->getPointerInfo(),
1300 Store->isNonTemporal(), Store->isVolatile(),
1301 Store->getAlignment());
1304 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1305 Store->getMemOperand()->getPointerInfo(),
1306 Store->isVolatile(), Store->isNonTemporal(),
1307 Store->getAlignment());
1310 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1311 SelectionDAG &DAG) const {
1312 StoreSDNode *Store = cast<StoreSDNode>(Op);
1313 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1314 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1315 EVT PtrVT = Store->getBasePtr().getValueType();
1316 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1319 SmallVector<SDValue, 8> Chains;
1321 unsigned EltSize = MemEltVT.getStoreSize();
1322 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1324 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1325 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1327 DAG.getConstant(i, MVT::i32));
1329 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), PtrVT);
1330 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1332 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1333 SrcValue.getWithOffset(i * EltSize),
1334 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1335 Store->getAlignment());
1336 Chains.push_back(NewStore);
1339 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1342 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1343 SelectionDAG &DAG) const {
1344 StoreSDNode *Store = cast<StoreSDNode>(Op);
1345 SDValue Val = Store->getValue();
1346 EVT VT = Val.getValueType();
1348 // If this is a 2 element vector, we really want to scalarize and not create
1349 // weird 1 element vectors.
1350 if (VT.getVectorNumElements() == 2)
1351 return ScalarizeVectorStore(Op, DAG);
1353 EVT MemVT = Store->getMemoryVT();
1354 SDValue Chain = Store->getChain();
1355 SDValue BasePtr = Store->getBasePtr();
1359 EVT LoMemVT, HiMemVT;
1362 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1363 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1364 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1366 EVT PtrVT = BasePtr.getValueType();
1367 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1368 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1370 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1372 = DAG.getTruncStore(Chain, SL, Lo,
1376 Store->isNonTemporal(),
1377 Store->isVolatile(),
1378 Store->getAlignment());
1380 = DAG.getTruncStore(Chain, SL, Hi,
1382 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1384 Store->isNonTemporal(),
1385 Store->isVolatile(),
1386 Store->getAlignment());
1388 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1392 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1394 LoadSDNode *Load = cast<LoadSDNode>(Op);
1395 ISD::LoadExtType ExtType = Load->getExtensionType();
1396 EVT VT = Op.getValueType();
1397 EVT MemVT = Load->getMemoryVT();
1399 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1400 // We can do the extload to 32-bits, and then need to separately extend to
1403 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1407 Load->getMemOperand());
1410 DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32),
1411 ExtLoad32.getValue(1)
1414 return DAG.getMergeValues(Ops, DL);
1417 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1418 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1419 // FIXME: Copied from PPC
1420 // First, load into 32 bits, then truncate to 1 bit.
1422 SDValue Chain = Load->getChain();
1423 SDValue BasePtr = Load->getBasePtr();
1424 MachineMemOperand *MMO = Load->getMemOperand();
1426 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1427 BasePtr, MVT::i8, MMO);
1430 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1434 return DAG.getMergeValues(Ops, DL);
1437 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1438 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1439 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1443 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1444 DAG.getConstant(2, MVT::i32));
1445 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1446 Load->getChain(), Ptr,
1447 DAG.getTargetConstant(0, MVT::i32),
1449 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1451 DAG.getConstant(0x3, MVT::i32));
1452 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1453 DAG.getConstant(3, MVT::i32));
1455 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1457 EVT MemEltVT = MemVT.getScalarType();
1458 if (ExtType == ISD::SEXTLOAD) {
1459 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1462 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1466 return DAG.getMergeValues(Ops, DL);
1470 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1474 return DAG.getMergeValues(Ops, DL);
1477 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1479 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1480 if (Result.getNode()) {
1484 StoreSDNode *Store = cast<StoreSDNode>(Op);
1485 SDValue Chain = Store->getChain();
1486 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1487 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1488 Store->getValue().getValueType().isVector()) {
1489 return ScalarizeVectorStore(Op, DAG);
1492 EVT MemVT = Store->getMemoryVT();
1493 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1494 MemVT.bitsLT(MVT::i32)) {
1496 if (Store->getMemoryVT() == MVT::i8) {
1498 } else if (Store->getMemoryVT() == MVT::i16) {
1501 SDValue BasePtr = Store->getBasePtr();
1502 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1503 DAG.getConstant(2, MVT::i32));
1504 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1505 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1507 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1508 DAG.getConstant(0x3, MVT::i32));
1510 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1511 DAG.getConstant(3, MVT::i32));
1513 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1516 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1518 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1519 MaskedValue, ShiftAmt);
1521 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1523 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1524 DAG.getConstant(0xffffffff, MVT::i32));
1525 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1527 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1528 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1529 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1534 // This is a shortcut for integer division because we have fast i32<->f32
1535 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1536 // float is enough to accurately represent up to a 24-bit integer.
1537 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1539 EVT VT = Op.getValueType();
1540 SDValue LHS = Op.getOperand(0);
1541 SDValue RHS = Op.getOperand(1);
1542 MVT IntVT = MVT::i32;
1543 MVT FltVT = MVT::f32;
1545 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1546 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1548 if (VT.isVector()) {
1549 unsigned NElts = VT.getVectorNumElements();
1550 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1551 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1554 unsigned BitSize = VT.getScalarType().getSizeInBits();
1556 SDValue jq = DAG.getConstant(1, IntVT);
1559 // char|short jq = ia ^ ib;
1560 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1562 // jq = jq >> (bitsize - 2)
1563 jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
1566 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));
1569 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1572 // int ia = (int)LHS;
1574 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1576 // int ib, (int)RHS;
1578 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1580 // float fa = (float)ia;
1581 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1583 // float fb = (float)ib;
1584 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1586 // float fq = native_divide(fa, fb);
1587 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1588 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1591 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1593 // float fqneg = -fq;
1594 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1596 // float fr = mad(fqneg, fb, fa);
1597 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1598 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1600 // int iq = (int)fq;
1601 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1604 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1607 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1609 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), VT);
1611 // int cv = fr >= fb;
1612 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1614 // jq = (cv ? jq : 0);
1615 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
1617 // dst = trunc/extend to legal type
1618 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1621 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1623 // Rem needs compensation, it's easier to recompute it
1624 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1625 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1631 return DAG.getMergeValues(Res, DL);
1634 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1636 SmallVectorImpl<SDValue> &Results) const {
1637 assert(Op.getValueType() == MVT::i64);
1640 EVT VT = Op.getValueType();
1641 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1643 SDValue one = DAG.getConstant(1, HalfVT);
1644 SDValue zero = DAG.getConstant(0, HalfVT);
1647 SDValue LHS = Op.getOperand(0);
1648 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1649 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1651 SDValue RHS = Op.getOperand(1);
1652 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1653 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1655 // Get Speculative values
1656 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1657 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1659 SDValue REM_Hi = zero;
1660 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1662 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1663 SDValue DIV_Lo = zero;
1665 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1667 for (unsigned i = 0; i < halfBitWidth; ++i) {
1668 SDValue POS = DAG.getConstant(halfBitWidth - i - 1, HalfVT);
1669 // Get Value of high bit
1671 if (halfBitWidth == 32 && Subtarget->hasBFE()) {
1672 HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
1674 HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1675 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1678 SDValue Carry = DAG.getNode(ISD::SRL, DL, HalfVT, REM_Lo,
1679 DAG.getConstant(halfBitWidth - 1, HalfVT));
1680 REM_Hi = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Hi, one);
1681 REM_Hi = DAG.getNode(ISD::OR, DL, HalfVT, REM_Hi, Carry);
1683 REM_Lo = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Lo, one);
1684 REM_Lo = DAG.getNode(ISD::OR, DL, HalfVT, REM_Lo, HBit);
1687 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
1689 SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
1690 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1692 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1696 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1698 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1699 REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
1700 REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
1703 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
1704 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
1705 Results.push_back(DIV);
1706 Results.push_back(REM);
1709 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1710 SelectionDAG &DAG) const {
1712 EVT VT = Op.getValueType();
1714 if (VT == MVT::i64) {
1715 SmallVector<SDValue, 2> Results;
1716 LowerUDIVREM64(Op, DAG, Results);
1717 return DAG.getMergeValues(Results, DL);
1720 SDValue Num = Op.getOperand(0);
1721 SDValue Den = Op.getOperand(1);
1723 if (VT == MVT::i32) {
1724 if (DAG.MaskedValueIsZero(Op.getOperand(0), APInt(32, 0xff << 24)) &&
1725 DAG.MaskedValueIsZero(Op.getOperand(1), APInt(32, 0xff << 24))) {
1726 // TODO: We technically could do this for i64, but shouldn't that just be
1727 // handled by something generally reducing 64-bit division on 32-bit
1728 // values to 32-bit?
1729 return LowerDIVREM24(Op, DAG, false);
1733 // RCP = URECIP(Den) = 2^32 / Den + e
1734 // e is rounding error.
1735 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1737 // RCP_LO = mul(RCP, Den) */
1738 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1740 // RCP_HI = mulhu (RCP, Den) */
1741 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1743 // NEG_RCP_LO = -RCP_LO
1744 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1747 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1748 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1751 // Calculate the rounding error from the URECIP instruction
1752 // E = mulhu(ABS_RCP_LO, RCP)
1753 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1755 // RCP_A_E = RCP + E
1756 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1758 // RCP_S_E = RCP - E
1759 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1761 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1762 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1765 // Quotient = mulhu(Tmp0, Num)
1766 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1768 // Num_S_Remainder = Quotient * Den
1769 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1771 // Remainder = Num - Num_S_Remainder
1772 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1774 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1775 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1776 DAG.getConstant(-1, VT),
1777 DAG.getConstant(0, VT),
1779 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1780 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1782 DAG.getConstant(-1, VT),
1783 DAG.getConstant(0, VT),
1785 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1786 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1789 // Calculate Division result:
1791 // Quotient_A_One = Quotient + 1
1792 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1793 DAG.getConstant(1, VT));
1795 // Quotient_S_One = Quotient - 1
1796 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1797 DAG.getConstant(1, VT));
1799 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1800 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1801 Quotient, Quotient_A_One, ISD::SETEQ);
1803 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1804 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1805 Quotient_S_One, Div, ISD::SETEQ);
1807 // Calculate Rem result:
1809 // Remainder_S_Den = Remainder - Den
1810 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1812 // Remainder_A_Den = Remainder + Den
1813 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1815 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1816 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1817 Remainder, Remainder_S_Den, ISD::SETEQ);
1819 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1820 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1821 Remainder_A_Den, Rem, ISD::SETEQ);
1826 return DAG.getMergeValues(Ops, DL);
1829 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1830 SelectionDAG &DAG) const {
1832 EVT VT = Op.getValueType();
1834 SDValue LHS = Op.getOperand(0);
1835 SDValue RHS = Op.getOperand(1);
1837 if (VT == MVT::i32) {
1838 if (DAG.ComputeNumSignBits(Op.getOperand(0)) > 8 &&
1839 DAG.ComputeNumSignBits(Op.getOperand(1)) > 8) {
1840 // TODO: We technically could do this for i64, but shouldn't that just be
1841 // handled by something generally reducing 64-bit division on 32-bit
1842 // values to 32-bit?
1843 return LowerDIVREM24(Op, DAG, true);
1847 SDValue Zero = DAG.getConstant(0, VT);
1848 SDValue NegOne = DAG.getConstant(-1, VT);
1850 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1851 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1852 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1853 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1855 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1856 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1858 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1859 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1861 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1862 SDValue Rem = Div.getValue(1);
1864 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1865 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1867 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1868 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1874 return DAG.getMergeValues(Res, DL);
1877 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1878 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1880 EVT VT = Op.getValueType();
1881 SDValue X = Op.getOperand(0);
1882 SDValue Y = Op.getOperand(1);
1884 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1885 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1886 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1888 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1891 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1893 SDValue Src = Op.getOperand(0);
1895 // result = trunc(src)
1896 // if (src > 0.0 && src != result)
1899 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1901 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1902 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1904 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1906 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1907 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1908 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1910 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1911 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1914 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1916 SDValue Src = Op.getOperand(0);
1918 assert(Op.getValueType() == MVT::f64);
1920 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1921 const SDValue One = DAG.getConstant(1, MVT::i32);
1923 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1925 // Extract the upper half, since this is where we will find the sign and
1927 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1929 const unsigned FractBits = 52;
1930 const unsigned ExpBits = 11;
1932 // Extract the exponent.
1933 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1935 DAG.getConstant(FractBits - 32, MVT::i32),
1936 DAG.getConstant(ExpBits, MVT::i32));
1937 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1938 DAG.getConstant(1023, MVT::i32));
1940 // Extract the sign bit.
1941 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1942 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1944 // Extend back to to 64-bits.
1945 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1947 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1949 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1950 const SDValue FractMask
1951 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1953 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1954 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1955 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1957 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1959 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1961 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1962 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1964 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1965 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1967 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1970 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1972 SDValue Src = Op.getOperand(0);
1974 assert(Op.getValueType() == MVT::f64);
1976 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1977 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1978 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1980 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1981 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1983 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1985 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1986 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
1988 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1989 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1991 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1994 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1995 // FNEARBYINT and FRINT are the same, except in their handling of FP
1996 // exceptions. Those aren't really meaningful for us, and OpenCL only has
1997 // rint, so just treat them as equivalent.
1998 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2001 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2003 SDValue Src = Op.getOperand(0);
2005 // result = trunc(src);
2006 // if (src < 0.0 && src != result)
2009 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2011 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
2012 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
2014 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
2016 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2017 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2018 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2020 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2021 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2024 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2025 bool Signed) const {
2027 SDValue Src = Op.getOperand(0);
2029 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2031 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2032 DAG.getConstant(0, MVT::i32));
2033 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2034 DAG.getConstant(1, MVT::i32));
2036 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2039 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2041 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2042 DAG.getConstant(32, MVT::i32));
2044 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2047 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2048 SelectionDAG &DAG) const {
2049 SDValue S0 = Op.getOperand(0);
2050 if (S0.getValueType() != MVT::i64)
2053 EVT DestVT = Op.getValueType();
2054 if (DestVT == MVT::f64)
2055 return LowerINT_TO_FP64(Op, DAG, false);
2057 assert(DestVT == MVT::f32);
2061 // f32 uint_to_fp i64
2062 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2063 DAG.getConstant(0, MVT::i32));
2064 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
2065 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2066 DAG.getConstant(1, MVT::i32));
2067 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
2068 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
2069 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
2070 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
2073 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2074 SelectionDAG &DAG) const {
2075 SDValue Src = Op.getOperand(0);
2076 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
2077 return LowerINT_TO_FP64(Op, DAG, true);
2082 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2083 bool Signed) const {
2086 SDValue Src = Op.getOperand(0);
2088 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2091 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), MVT::f64);
2093 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), MVT::f64);
2095 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2097 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2100 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2102 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2103 MVT::i32, FloorMul);
2104 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2106 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
2108 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2111 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2112 SelectionDAG &DAG) const {
2113 SDValue Src = Op.getOperand(0);
2115 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2116 return LowerFP64_TO_INT(Op, DAG, true);
2121 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2122 SelectionDAG &DAG) const {
2123 SDValue Src = Op.getOperand(0);
2125 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2126 return LowerFP64_TO_INT(Op, DAG, false);
2131 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2132 SelectionDAG &DAG) const {
2133 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2134 MVT VT = Op.getSimpleValueType();
2135 MVT ScalarVT = VT.getScalarType();
2140 SDValue Src = Op.getOperand(0);
2143 // TODO: Don't scalarize on Evergreen?
2144 unsigned NElts = VT.getVectorNumElements();
2145 SmallVector<SDValue, 8> Args;
2146 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2148 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2149 for (unsigned I = 0; I < NElts; ++I)
2150 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2152 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2155 //===----------------------------------------------------------------------===//
2156 // Custom DAG optimizations
2157 //===----------------------------------------------------------------------===//
2159 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2160 APInt KnownZero, KnownOne;
2161 EVT VT = Op.getValueType();
2162 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2164 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2167 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2168 EVT VT = Op.getValueType();
2170 // In order for this to be a signed 24-bit value, bit 23, must
2172 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2173 // as unsigned 24-bit values.
2174 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2177 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2179 SelectionDAG &DAG = DCI.DAG;
2180 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2181 EVT VT = Op.getValueType();
2183 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2184 APInt KnownZero, KnownOne;
2185 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2186 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2187 DCI.CommitTargetLoweringOpt(TLO);
2190 template <typename IntTy>
2191 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2192 uint32_t Offset, uint32_t Width) {
2193 if (Width + Offset < 32) {
2194 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2195 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2196 return DAG.getConstant(Result, MVT::i32);
2199 return DAG.getConstant(Src0 >> Offset, MVT::i32);
2202 static bool usesAllNormalStores(SDNode *LoadVal) {
2203 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2204 if (!ISD::isNormalStore(*I))
2211 // If we have a copy of an illegal type, replace it with a load / store of an
2212 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2213 // instructions emitted when handling extloads and truncstores. Ideally we could
2214 // recognize the pack / unpack pattern to eliminate it.
2215 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2216 DAGCombinerInfo &DCI) const {
2217 if (!DCI.isBeforeLegalize())
2220 StoreSDNode *SN = cast<StoreSDNode>(N);
2221 SDValue Value = SN->getValue();
2222 EVT VT = Value.getValueType();
2224 if (isTypeLegal(VT) || SN->isVolatile() ||
2225 !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2228 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2229 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2232 EVT MemVT = LoadVal->getMemoryVT();
2235 SelectionDAG &DAG = DCI.DAG;
2236 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2238 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2240 LoadVal->getChain(),
2241 LoadVal->getBasePtr(),
2242 LoadVal->getOffset(),
2244 LoadVal->getMemOperand());
2246 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2247 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2249 return DAG.getStore(SN->getChain(), SL, NewLoad,
2250 SN->getBasePtr(), SN->getMemOperand());
2253 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2254 DAGCombinerInfo &DCI) const {
2255 EVT VT = N->getValueType(0);
2257 if (VT.isVector() || VT.getSizeInBits() > 32)
2260 SelectionDAG &DAG = DCI.DAG;
2263 SDValue N0 = N->getOperand(0);
2264 SDValue N1 = N->getOperand(1);
2267 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2268 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2269 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2270 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2271 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2272 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2273 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2274 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2279 // We need to use sext even for MUL_U24, because MUL_U24 is used
2280 // for signed multiply of 8 and 16-bit types.
2281 return DAG.getSExtOrTrunc(Mul, DL, VT);
2284 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2285 DAGCombinerInfo &DCI) const {
2286 SelectionDAG &DAG = DCI.DAG;
2289 switch(N->getOpcode()) {
2292 return performMulCombine(N, DCI);
2293 case AMDGPUISD::MUL_I24:
2294 case AMDGPUISD::MUL_U24: {
2295 SDValue N0 = N->getOperand(0);
2296 SDValue N1 = N->getOperand(1);
2297 simplifyI24(N0, DCI);
2298 simplifyI24(N1, DCI);
2302 SDValue Cond = N->getOperand(0);
2303 if (Cond.getOpcode() == ISD::SETCC) {
2305 EVT VT = N->getValueType(0);
2306 SDValue LHS = Cond.getOperand(0);
2307 SDValue RHS = Cond.getOperand(1);
2308 SDValue CC = Cond.getOperand(2);
2310 SDValue True = N->getOperand(1);
2311 SDValue False = N->getOperand(2);
2314 return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
2316 // TODO: Implement min / max Evergreen instructions.
2317 if (VT == MVT::i32 &&
2318 Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
2319 return CombineIMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
2325 case AMDGPUISD::BFE_I32:
2326 case AMDGPUISD::BFE_U32: {
2327 assert(!N->getValueType(0).isVector() &&
2328 "Vector handling of BFE not implemented");
2329 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2333 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2335 return DAG.getConstant(0, MVT::i32);
2337 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2341 SDValue BitsFrom = N->getOperand(0);
2342 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2344 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2346 if (OffsetVal == 0) {
2347 // This is already sign / zero extended, so try to fold away extra BFEs.
2348 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2350 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2351 if (OpSignBits >= SignBits)
2354 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2356 // This is a sign_extend_inreg. Replace it to take advantage of existing
2357 // DAG Combines. If not eliminated, we will match back to BFE during
2360 // TODO: The sext_inreg of extended types ends, although we can could
2361 // handle them in a single BFE.
2362 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2363 DAG.getValueType(SmallVT));
2366 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2369 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2371 return constantFoldBFE<int32_t>(DAG,
2372 CVal->getSExtValue(),
2377 return constantFoldBFE<uint32_t>(DAG,
2378 CVal->getZExtValue(),
2383 if ((OffsetVal + WidthVal) >= 32) {
2384 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
2385 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2386 BitsFrom, ShiftVal);
2389 if (BitsFrom.hasOneUse()) {
2390 APInt Demanded = APInt::getBitsSet(32,
2392 OffsetVal + WidthVal);
2394 APInt KnownZero, KnownOne;
2395 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2396 !DCI.isBeforeLegalizeOps());
2397 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2398 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2399 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2400 KnownZero, KnownOne, TLO)) {
2401 DCI.CommitTargetLoweringOpt(TLO);
2409 return performStoreCombine(N, DCI);
2414 //===----------------------------------------------------------------------===//
2416 //===----------------------------------------------------------------------===//
2418 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2421 const SmallVectorImpl<ISD::InputArg> &Ins,
2422 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2424 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2425 if (Ins[i].ArgVT == Ins[i].VT) {
2426 OrigIns.push_back(Ins[i]);
2431 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2432 // Vector has been split into scalars.
2433 VT = Ins[i].ArgVT.getVectorElementType();
2434 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2435 Ins[i].ArgVT.getVectorElementType() !=
2436 Ins[i].VT.getVectorElementType()) {
2437 // Vector elements have been promoted
2440 // Vector has been spilt into smaller vectors.
2444 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2445 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2446 OrigIns.push_back(Arg);
2450 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2451 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2452 return CFP->isExactlyValue(1.0);
2454 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2455 return C->isAllOnesValue();
2460 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2461 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2462 return CFP->getValueAPF().isZero();
2464 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2465 return C->isNullValue();
2470 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2471 const TargetRegisterClass *RC,
2472 unsigned Reg, EVT VT) const {
2473 MachineFunction &MF = DAG.getMachineFunction();
2474 MachineRegisterInfo &MRI = MF.getRegInfo();
2475 unsigned VirtualRegister;
2476 if (!MRI.isLiveIn(Reg)) {
2477 VirtualRegister = MRI.createVirtualRegister(RC);
2478 MRI.addLiveIn(Reg, VirtualRegister);
2480 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2482 return DAG.getRegister(VirtualRegister, VT);
2485 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2487 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2489 default: return nullptr;
2491 NODE_NAME_CASE(CALL);
2492 NODE_NAME_CASE(UMUL);
2493 NODE_NAME_CASE(RET_FLAG);
2494 NODE_NAME_CASE(BRANCH_COND);
2497 NODE_NAME_CASE(DWORDADDR)
2498 NODE_NAME_CASE(FRACT)
2499 NODE_NAME_CASE(CLAMP)
2501 NODE_NAME_CASE(FMAX_LEGACY)
2502 NODE_NAME_CASE(SMAX)
2503 NODE_NAME_CASE(UMAX)
2504 NODE_NAME_CASE(FMIN_LEGACY)
2505 NODE_NAME_CASE(SMIN)
2506 NODE_NAME_CASE(UMIN)
2507 NODE_NAME_CASE(FMAX3)
2508 NODE_NAME_CASE(SMAX3)
2509 NODE_NAME_CASE(UMAX3)
2510 NODE_NAME_CASE(FMIN3)
2511 NODE_NAME_CASE(SMIN3)
2512 NODE_NAME_CASE(UMIN3)
2513 NODE_NAME_CASE(URECIP)
2514 NODE_NAME_CASE(DIV_SCALE)
2515 NODE_NAME_CASE(DIV_FMAS)
2516 NODE_NAME_CASE(DIV_FIXUP)
2517 NODE_NAME_CASE(TRIG_PREOP)
2520 NODE_NAME_CASE(RSQ_LEGACY)
2521 NODE_NAME_CASE(RSQ_CLAMPED)
2522 NODE_NAME_CASE(LDEXP)
2523 NODE_NAME_CASE(DOT4)
2524 NODE_NAME_CASE(BFE_U32)
2525 NODE_NAME_CASE(BFE_I32)
2528 NODE_NAME_CASE(BREV)
2529 NODE_NAME_CASE(MUL_U24)
2530 NODE_NAME_CASE(MUL_I24)
2531 NODE_NAME_CASE(MAD_U24)
2532 NODE_NAME_CASE(MAD_I24)
2533 NODE_NAME_CASE(EXPORT)
2534 NODE_NAME_CASE(CONST_ADDRESS)
2535 NODE_NAME_CASE(REGISTER_LOAD)
2536 NODE_NAME_CASE(REGISTER_STORE)
2537 NODE_NAME_CASE(LOAD_CONSTANT)
2538 NODE_NAME_CASE(LOAD_INPUT)
2539 NODE_NAME_CASE(SAMPLE)
2540 NODE_NAME_CASE(SAMPLEB)
2541 NODE_NAME_CASE(SAMPLED)
2542 NODE_NAME_CASE(SAMPLEL)
2543 NODE_NAME_CASE(CVT_F32_UBYTE0)
2544 NODE_NAME_CASE(CVT_F32_UBYTE1)
2545 NODE_NAME_CASE(CVT_F32_UBYTE2)
2546 NODE_NAME_CASE(CVT_F32_UBYTE3)
2547 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2548 NODE_NAME_CASE(CONST_DATA_PTR)
2549 NODE_NAME_CASE(STORE_MSKOR)
2550 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2554 static void computeKnownBitsForMinMax(const SDValue Op0,
2558 const SelectionDAG &DAG,
2560 APInt Op0Zero, Op0One;
2561 APInt Op1Zero, Op1One;
2562 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2563 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2565 KnownZero = Op0Zero & Op1Zero;
2566 KnownOne = Op0One & Op1One;
2569 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2573 const SelectionDAG &DAG,
2574 unsigned Depth) const {
2576 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2580 unsigned Opc = Op.getOpcode();
2585 case ISD::INTRINSIC_WO_CHAIN: {
2586 // FIXME: The intrinsic should just use the node.
2587 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2588 case AMDGPUIntrinsic::AMDGPU_imax:
2589 case AMDGPUIntrinsic::AMDGPU_umax:
2590 case AMDGPUIntrinsic::AMDGPU_imin:
2591 case AMDGPUIntrinsic::AMDGPU_umin:
2592 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2593 KnownZero, KnownOne, DAG, Depth);
2601 case AMDGPUISD::SMAX:
2602 case AMDGPUISD::UMAX:
2603 case AMDGPUISD::SMIN:
2604 case AMDGPUISD::UMIN:
2605 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2606 KnownZero, KnownOne, DAG, Depth);
2609 case AMDGPUISD::BFE_I32:
2610 case AMDGPUISD::BFE_U32: {
2611 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2615 unsigned BitWidth = 32;
2616 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2618 if (Opc == AMDGPUISD::BFE_U32)
2619 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2626 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2628 const SelectionDAG &DAG,
2629 unsigned Depth) const {
2630 switch (Op.getOpcode()) {
2631 case AMDGPUISD::BFE_I32: {
2632 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2636 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2637 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2638 if (!Offset || !Offset->isNullValue())
2641 // TODO: Could probably figure something out with non-0 offsets.
2642 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2643 return std::max(SignBits, Op0SignBits);
2646 case AMDGPUISD::BFE_U32: {
2647 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2648 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;