1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPURegisterInfo.h"
20 #include "AMDGPUSubtarget.h"
21 #include "AMDILIntrinsicInfo.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/DataLayout.h"
33 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
34 CCValAssign::LocInfo LocInfo,
35 ISD::ArgFlagsTy ArgFlags, CCState &State) {
36 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
37 ArgFlags.getOrigAlign());
38 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
43 #include "AMDGPUGenCallingConv.inc"
45 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
46 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
48 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
50 // Initialize target lowering borrowed from AMDIL
53 // We need to custom lower some of the intrinsics
54 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
56 // Library functions. These default to Expand, but we have instructions
58 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
59 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
60 setOperationAction(ISD::FPOW, MVT::f32, Legal);
61 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
62 setOperationAction(ISD::FABS, MVT::f32, Legal);
63 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
64 setOperationAction(ISD::FRINT, MVT::f32, Legal);
65 setOperationAction(ISD::FROUND, MVT::f32, Legal);
66 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
68 // The hardware supports ROTR, but not ROTL
69 setOperationAction(ISD::ROTL, MVT::i32, Expand);
71 // Lower floating point store/load to integer store/load to reduce the number
72 // of patterns in tablegen.
73 setOperationAction(ISD::STORE, MVT::f32, Promote);
74 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
76 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
77 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
79 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
80 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
82 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
83 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
85 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
86 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
88 setOperationAction(ISD::STORE, MVT::f64, Promote);
89 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
91 // Custom lowering of vector stores is required for local address space
93 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
94 // XXX: Native v2i32 local address space stores are possible, but not
95 // currently implemented.
96 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
98 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
99 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
100 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
102 // XXX: This can be change to Custom, once ExpandVectorStores can
103 // handle 64-bit stores.
104 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
106 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
107 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
108 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
111 setOperationAction(ISD::LOAD, MVT::f32, Promote);
112 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
114 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
115 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
117 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
118 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
120 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
121 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
123 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
124 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
126 setOperationAction(ISD::LOAD, MVT::f64, Promote);
127 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
129 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
130 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
131 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
132 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
133 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
134 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
135 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
136 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
137 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
138 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
140 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
141 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
142 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
143 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
144 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
145 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
146 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
147 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
148 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
149 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
150 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
151 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
153 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
155 setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
156 setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
158 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
160 setOperationAction(ISD::MUL, MVT::i64, Expand);
162 setOperationAction(ISD::UDIV, MVT::i32, Expand);
163 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
164 setOperationAction(ISD::UREM, MVT::i32, Expand);
165 setOperationAction(ISD::VSELECT, MVT::v2f32, Expand);
166 setOperationAction(ISD::VSELECT, MVT::v4f32, Expand);
168 static const MVT::SimpleValueType IntTypes[] = {
169 MVT::v2i32, MVT::v4i32
171 const size_t NumIntTypes = array_lengthof(IntTypes);
173 for (unsigned int x = 0; x < NumIntTypes; ++x) {
174 MVT::SimpleValueType VT = IntTypes[x];
175 //Expand the following operations for the current type by default
176 setOperationAction(ISD::ADD, VT, Expand);
177 setOperationAction(ISD::AND, VT, Expand);
178 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
179 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
180 setOperationAction(ISD::MUL, VT, Expand);
181 setOperationAction(ISD::OR, VT, Expand);
182 setOperationAction(ISD::SHL, VT, Expand);
183 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
184 setOperationAction(ISD::SRL, VT, Expand);
185 setOperationAction(ISD::SRA, VT, Expand);
186 setOperationAction(ISD::SUB, VT, Expand);
187 setOperationAction(ISD::UDIV, VT, Expand);
188 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
189 setOperationAction(ISD::UREM, VT, Expand);
190 setOperationAction(ISD::SELECT, VT, Expand);
191 setOperationAction(ISD::VSELECT, VT, Expand);
192 setOperationAction(ISD::XOR, VT, Expand);
195 static const MVT::SimpleValueType FloatTypes[] = {
196 MVT::v2f32, MVT::v4f32
198 const size_t NumFloatTypes = array_lengthof(FloatTypes);
200 for (unsigned int x = 0; x < NumFloatTypes; ++x) {
201 MVT::SimpleValueType VT = FloatTypes[x];
202 setOperationAction(ISD::FABS, VT, Expand);
203 setOperationAction(ISD::FADD, VT, Expand);
204 setOperationAction(ISD::FDIV, VT, Expand);
205 setOperationAction(ISD::FPOW, VT, Expand);
206 setOperationAction(ISD::FFLOOR, VT, Expand);
207 setOperationAction(ISD::FTRUNC, VT, Expand);
208 setOperationAction(ISD::FMUL, VT, Expand);
209 setOperationAction(ISD::FRINT, VT, Expand);
210 setOperationAction(ISD::FSQRT, VT, Expand);
211 setOperationAction(ISD::FSUB, VT, Expand);
212 setOperationAction(ISD::SELECT, VT, Expand);
216 //===----------------------------------------------------------------------===//
217 // Target Information
218 //===----------------------------------------------------------------------===//
220 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
224 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
226 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
229 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
230 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
232 return ((LScalarSize <= CastScalarSize) ||
233 (CastScalarSize >= 32) ||
237 //===---------------------------------------------------------------------===//
239 //===---------------------------------------------------------------------===//
241 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
242 assert(VT.isFloatingPoint());
243 return VT == MVT::f32;
246 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
247 assert(VT.isFloatingPoint());
248 return VT == MVT::f32;
251 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
252 // Truncate is just accessing a subregister.
253 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
256 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
257 // Truncate is just accessing a subregister.
258 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
259 (Dest->getPrimitiveSizeInBits() % 32 == 0);
262 //===---------------------------------------------------------------------===//
263 // TargetLowering Callbacks
264 //===---------------------------------------------------------------------===//
266 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
267 const SmallVectorImpl<ISD::InputArg> &Ins) const {
269 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
272 SDValue AMDGPUTargetLowering::LowerReturn(
274 CallingConv::ID CallConv,
276 const SmallVectorImpl<ISD::OutputArg> &Outs,
277 const SmallVectorImpl<SDValue> &OutVals,
278 SDLoc DL, SelectionDAG &DAG) const {
279 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
282 //===---------------------------------------------------------------------===//
283 // Target specific lowering
284 //===---------------------------------------------------------------------===//
286 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
288 switch (Op.getOpcode()) {
290 Op.getNode()->dump();
291 llvm_unreachable("Custom lowering code for this"
292 "instruction is not implemented yet!");
294 // AMDIL DAG lowering
295 case ISD::SDIV: return LowerSDIV(Op, DAG);
296 case ISD::SREM: return LowerSREM(Op, DAG);
297 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
298 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
299 // AMDGPU DAG lowering
300 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
301 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
302 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
303 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
304 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
305 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
310 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
311 const GlobalValue *GV,
312 const SDValue &InitPtr,
314 SelectionDAG &DAG) const {
315 const DataLayout *TD = getTargetMachine().getDataLayout();
317 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
318 EVT VT = EVT::getEVT(CI->getType());
319 PointerType *PtrTy = PointerType::get(CI->getType(), 0);
320 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
321 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
322 TD->getPrefTypeAlignment(CI->getType()));
323 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
324 EVT VT = EVT::getEVT(CFP->getType());
325 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
326 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
327 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
328 TD->getPrefTypeAlignment(CFP->getType()));
329 } else if (Init->getType()->isAggregateType()) {
330 EVT PtrVT = InitPtr.getValueType();
331 unsigned NumElements = Init->getType()->getArrayNumElements();
332 SmallVector<SDValue, 8> Chains;
333 for (unsigned i = 0; i < NumElements; ++i) {
334 SDValue Offset = DAG.getConstant(i * TD->getTypeAllocSize(
335 Init->getType()->getArrayElementType()), PtrVT);
336 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
337 Chains.push_back(LowerConstantInitializer(Init->getAggregateElement(i),
338 GV, Ptr, Chain, DAG));
340 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &Chains[0],
344 llvm_unreachable("Unhandled constant initializer");
348 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
350 SelectionDAG &DAG) const {
352 const DataLayout *TD = getTargetMachine().getDataLayout();
353 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
354 const GlobalValue *GV = G->getGlobal();
356 switch (G->getAddressSpace()) {
357 default: llvm_unreachable("Global Address lowering not implemented for this "
359 case AMDGPUAS::LOCAL_ADDRESS: {
360 // XXX: What does the value of G->getOffset() mean?
361 assert(G->getOffset() == 0 &&
362 "Do not know what to do with an non-zero offset");
365 if (MFI->LocalMemoryObjects.count(GV) == 0) {
366 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
367 Offset = MFI->LDSSize;
368 MFI->LocalMemoryObjects[GV] = Offset;
369 // XXX: Account for alignment?
370 MFI->LDSSize += Size;
372 Offset = MFI->LocalMemoryObjects[GV];
375 return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
377 case AMDGPUAS::CONSTANT_ADDRESS: {
378 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
379 Type *EltType = GV->getType()->getElementType();
380 unsigned Size = TD->getTypeAllocSize(EltType);
381 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
383 const GlobalVariable *Var = dyn_cast<GlobalVariable>(GV);
384 const Constant *Init = Var->getInitializer();
385 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
386 SDValue InitPtr = DAG.getFrameIndex(FI,
387 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
388 SmallVector<SDNode*, 8> WorkList;
390 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
391 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
392 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
394 WorkList.push_back(*I);
396 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
397 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
398 E = WorkList.end(); I != E; ++I) {
399 SmallVector<SDValue, 8> Ops;
400 Ops.push_back(Chain);
401 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
402 Ops.push_back((*I)->getOperand(i));
404 DAG.UpdateNodeOperands(*I, &Ops[0], Ops.size());
406 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op),
407 getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
412 void AMDGPUTargetLowering::ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
413 SmallVectorImpl<SDValue> &Args,
415 unsigned Count) const {
416 EVT VT = Op.getValueType();
417 for (unsigned i = Start, e = Start + Count; i != e; ++i) {
418 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
419 VT.getVectorElementType(),
420 Op, DAG.getConstant(i, MVT::i32)));
424 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
425 SelectionDAG &DAG) const {
426 SmallVector<SDValue, 8> Args;
427 SDValue A = Op.getOperand(0);
428 SDValue B = Op.getOperand(1);
430 ExtractVectorElements(A, DAG, Args, 0,
431 A.getValueType().getVectorNumElements());
432 ExtractVectorElements(B, DAG, Args, 0,
433 B.getValueType().getVectorNumElements());
435 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
436 &Args[0], Args.size());
439 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
440 SelectionDAG &DAG) const {
442 SmallVector<SDValue, 8> Args;
443 EVT VT = Op.getValueType();
444 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
445 ExtractVectorElements(Op.getOperand(0), DAG, Args, Start,
446 VT.getVectorNumElements());
448 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
449 &Args[0], Args.size());
452 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
453 SelectionDAG &DAG) const {
455 MachineFunction &MF = DAG.getMachineFunction();
456 const AMDGPUFrameLowering *TFL =
457 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
459 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op);
462 unsigned FrameIndex = FIN->getIndex();
463 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
464 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
468 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
469 SelectionDAG &DAG) const {
470 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
472 EVT VT = Op.getValueType();
474 switch (IntrinsicID) {
476 case AMDGPUIntrinsic::AMDIL_abs:
477 return LowerIntrinsicIABS(Op, DAG);
478 case AMDGPUIntrinsic::AMDIL_exp:
479 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
480 case AMDGPUIntrinsic::AMDGPU_lrp:
481 return LowerIntrinsicLRP(Op, DAG);
482 case AMDGPUIntrinsic::AMDIL_fraction:
483 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
484 case AMDGPUIntrinsic::AMDIL_max:
485 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
487 case AMDGPUIntrinsic::AMDGPU_imax:
488 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
490 case AMDGPUIntrinsic::AMDGPU_umax:
491 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
493 case AMDGPUIntrinsic::AMDIL_min:
494 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
496 case AMDGPUIntrinsic::AMDGPU_imin:
497 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
499 case AMDGPUIntrinsic::AMDGPU_umin:
500 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
502 case AMDGPUIntrinsic::AMDIL_round_nearest:
503 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
507 ///IABS(a) = SMAX(sub(0, a), a)
508 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
509 SelectionDAG &DAG) const {
512 EVT VT = Op.getValueType();
513 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
516 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
519 /// Linear Interpolation
520 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
521 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
522 SelectionDAG &DAG) const {
524 EVT VT = Op.getValueType();
525 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
526 DAG.getConstantFP(1.0f, MVT::f32),
528 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
530 return DAG.getNode(ISD::FADD, DL, VT,
531 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
535 /// \brief Generate Min/Max node
536 SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
537 SelectionDAG &DAG) const {
539 EVT VT = Op.getValueType();
541 SDValue LHS = Op.getOperand(0);
542 SDValue RHS = Op.getOperand(1);
543 SDValue True = Op.getOperand(2);
544 SDValue False = Op.getOperand(3);
545 SDValue CC = Op.getOperand(4);
547 if (VT != MVT::f32 ||
548 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
552 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
566 llvm_unreachable("Operation should already be optimised!");
574 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
576 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
585 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
587 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
589 case ISD::SETCC_INVALID:
590 llvm_unreachable("Invalid setcc condcode!");
595 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
596 SelectionDAG &DAG) const {
597 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
598 EVT MemEltVT = Load->getMemoryVT().getVectorElementType();
599 EVT EltVT = Op.getValueType().getVectorElementType();
600 EVT PtrVT = Load->getBasePtr().getValueType();
601 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
602 SmallVector<SDValue, 8> Loads;
605 for (unsigned i = 0, e = NumElts; i != e; ++i) {
606 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
607 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), PtrVT));
608 Loads.push_back(DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
609 Load->getChain(), Ptr,
610 MachinePointerInfo(Load->getMemOperand()->getValue()),
611 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
612 Load->getAlignment()));
614 return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(),
615 Loads.data(), Loads.size());
618 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
619 SelectionDAG &DAG) const {
620 StoreSDNode *Store = dyn_cast<StoreSDNode>(Op);
621 EVT MemVT = Store->getMemoryVT();
622 unsigned MemBits = MemVT.getSizeInBits();
624 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
625 // truncating store into an i32 store.
626 // XXX: We could also handle optimize other vector bitwidths.
627 if (!MemVT.isVector() || MemBits > 32) {
632 const SDValue &Value = Store->getValue();
633 EVT VT = Value.getValueType();
634 const SDValue &Ptr = Store->getBasePtr();
635 EVT MemEltVT = MemVT.getVectorElementType();
636 unsigned MemEltBits = MemEltVT.getSizeInBits();
637 unsigned MemNumElements = MemVT.getVectorNumElements();
638 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits());
639 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, PackedVT);
642 for (unsigned i = 0; i < MemNumElements; ++i) {
643 EVT ElemVT = VT.getVectorElementType();
644 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
645 DAG.getConstant(i, MVT::i32));
646 Elt = DAG.getZExtOrTrunc(Elt, DL, PackedVT);
647 Elt = DAG.getNode(ISD::AND, DL, PackedVT, Elt, Mask);
648 SDValue Shift = DAG.getConstant(MemEltBits * i, PackedVT);
649 Elt = DAG.getNode(ISD::SHL, DL, PackedVT, Elt, Shift);
653 PackedValue = DAG.getNode(ISD::OR, DL, PackedVT, PackedValue, Elt);
656 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
657 MachinePointerInfo(Store->getMemOperand()->getValue()),
658 Store->isVolatile(), Store->isNonTemporal(),
659 Store->getAlignment());
662 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
663 SelectionDAG &DAG) const {
664 StoreSDNode *Store = cast<StoreSDNode>(Op);
665 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
666 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
667 EVT PtrVT = Store->getBasePtr().getValueType();
668 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
671 SmallVector<SDValue, 8> Chains;
673 for (unsigned i = 0, e = NumElts; i != e; ++i) {
674 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
675 Store->getValue(), DAG.getConstant(i, MVT::i32));
676 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT,
678 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
680 Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
681 MachinePointerInfo(Store->getMemOperand()->getValue()),
682 MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
683 Store->getAlignment()));
685 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, &Chains[0], NumElts);
688 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
690 LoadSDNode *Load = cast<LoadSDNode>(Op);
691 ISD::LoadExtType ExtType = Load->getExtensionType();
692 EVT VT = Op.getValueType();
693 EVT MemVT = Load->getMemoryVT();
695 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
696 // We can do the extload to 32-bits, and then need to separately extend to
699 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
703 Load->getMemOperand());
704 return DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32);
707 // Lower loads constant address space global variable loads
708 if (Load->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
709 isa<GlobalVariable>(GetUnderlyingObject(Load->getPointerInfo().V))) {
711 SDValue Ptr = DAG.getZExtOrTrunc(Load->getBasePtr(), DL,
712 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
713 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
714 DAG.getConstant(2, MVT::i32));
715 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
716 Load->getChain(), Ptr,
717 DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2));
720 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
721 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
725 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
726 DAG.getConstant(2, MVT::i32));
727 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
728 Load->getChain(), Ptr,
729 DAG.getTargetConstant(0, MVT::i32),
731 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
733 DAG.getConstant(0x3, MVT::i32));
734 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
735 DAG.getConstant(3, MVT::i32));
737 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
739 EVT MemEltVT = MemVT.getScalarType();
740 if (ExtType == ISD::SEXTLOAD) {
741 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
742 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
745 return DAG.getZeroExtendInReg(Ret, DL, MemEltVT);
748 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
750 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
751 if (Result.getNode()) {
755 StoreSDNode *Store = cast<StoreSDNode>(Op);
756 SDValue Chain = Store->getChain();
757 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
758 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
759 Store->getValue().getValueType().isVector()) {
760 return SplitVectorStore(Op, DAG);
763 EVT MemVT = Store->getMemoryVT();
764 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
765 MemVT.bitsLT(MVT::i32)) {
767 if (Store->getMemoryVT() == MVT::i8) {
769 } else if (Store->getMemoryVT() == MVT::i16) {
772 SDValue BasePtr = Store->getBasePtr();
773 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
774 DAG.getConstant(2, MVT::i32));
775 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
776 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
778 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
779 DAG.getConstant(0x3, MVT::i32));
781 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
782 DAG.getConstant(3, MVT::i32));
784 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
787 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
789 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
790 MaskedValue, ShiftAmt);
792 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
794 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
795 DAG.getConstant(0xffffffff, MVT::i32));
796 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
798 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
799 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
800 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
805 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
806 SelectionDAG &DAG) const {
808 EVT VT = Op.getValueType();
810 SDValue Num = Op.getOperand(0);
811 SDValue Den = Op.getOperand(1);
813 SmallVector<SDValue, 8> Results;
815 // RCP = URECIP(Den) = 2^32 / Den + e
816 // e is rounding error.
817 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
819 // RCP_LO = umulo(RCP, Den) */
820 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
822 // RCP_HI = mulhu (RCP, Den) */
823 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
825 // NEG_RCP_LO = -RCP_LO
826 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
829 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
830 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
833 // Calculate the rounding error from the URECIP instruction
834 // E = mulhu(ABS_RCP_LO, RCP)
835 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
838 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
841 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
843 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
844 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
847 // Quotient = mulhu(Tmp0, Num)
848 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
850 // Num_S_Remainder = Quotient * Den
851 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
853 // Remainder = Num - Num_S_Remainder
854 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
856 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
857 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
858 DAG.getConstant(-1, VT),
859 DAG.getConstant(0, VT),
861 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
862 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
864 DAG.getConstant(-1, VT),
865 DAG.getConstant(0, VT),
867 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
868 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
871 // Calculate Division result:
873 // Quotient_A_One = Quotient + 1
874 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
875 DAG.getConstant(1, VT));
877 // Quotient_S_One = Quotient - 1
878 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
879 DAG.getConstant(1, VT));
881 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
882 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
883 Quotient, Quotient_A_One, ISD::SETEQ);
885 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
886 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
887 Quotient_S_One, Div, ISD::SETEQ);
889 // Calculate Rem result:
891 // Remainder_S_Den = Remainder - Den
892 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
894 // Remainder_A_Den = Remainder + Den
895 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
897 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
898 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
899 Remainder, Remainder_S_Den, ISD::SETEQ);
901 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
902 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
903 Remainder_A_Den, Rem, ISD::SETEQ);
907 return DAG.getMergeValues(Ops, 2, DL);
910 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
911 SelectionDAG &DAG) const {
912 SDValue S0 = Op.getOperand(0);
914 if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64)
917 // f32 uint_to_fp i64
918 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
919 DAG.getConstant(0, MVT::i32));
920 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
921 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
922 DAG.getConstant(1, MVT::i32));
923 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
924 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
925 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
926 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
930 //===----------------------------------------------------------------------===//
932 //===----------------------------------------------------------------------===//
934 void AMDGPUTargetLowering::getOriginalFunctionArgs(
937 const SmallVectorImpl<ISD::InputArg> &Ins,
938 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
940 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
941 if (Ins[i].ArgVT == Ins[i].VT) {
942 OrigIns.push_back(Ins[i]);
947 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
948 // Vector has been split into scalars.
949 VT = Ins[i].ArgVT.getVectorElementType();
950 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
951 Ins[i].ArgVT.getVectorElementType() !=
952 Ins[i].VT.getVectorElementType()) {
953 // Vector elements have been promoted
956 // Vector has been spilt into smaller vectors.
960 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
961 Ins[i].OrigArgIndex, Ins[i].PartOffset);
962 OrigIns.push_back(Arg);
966 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
967 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
968 return CFP->isExactlyValue(1.0);
970 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
971 return C->isAllOnesValue();
976 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
977 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
978 return CFP->getValueAPF().isZero();
980 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
981 return C->isNullValue();
986 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
987 const TargetRegisterClass *RC,
988 unsigned Reg, EVT VT) const {
989 MachineFunction &MF = DAG.getMachineFunction();
990 MachineRegisterInfo &MRI = MF.getRegInfo();
991 unsigned VirtualRegister;
992 if (!MRI.isLiveIn(Reg)) {
993 VirtualRegister = MRI.createVirtualRegister(RC);
994 MRI.addLiveIn(Reg, VirtualRegister);
996 VirtualRegister = MRI.getLiveInVirtReg(Reg);
998 return DAG.getRegister(VirtualRegister, VT);
1001 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
1003 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
1007 NODE_NAME_CASE(CALL);
1008 NODE_NAME_CASE(UMUL);
1009 NODE_NAME_CASE(DIV_INF);
1010 NODE_NAME_CASE(RET_FLAG);
1011 NODE_NAME_CASE(BRANCH_COND);
1014 NODE_NAME_CASE(DWORDADDR)
1015 NODE_NAME_CASE(FRACT)
1016 NODE_NAME_CASE(FMAX)
1017 NODE_NAME_CASE(SMAX)
1018 NODE_NAME_CASE(UMAX)
1019 NODE_NAME_CASE(FMIN)
1020 NODE_NAME_CASE(SMIN)
1021 NODE_NAME_CASE(UMIN)
1022 NODE_NAME_CASE(URECIP)
1023 NODE_NAME_CASE(DOT4)
1024 NODE_NAME_CASE(EXPORT)
1025 NODE_NAME_CASE(CONST_ADDRESS)
1026 NODE_NAME_CASE(REGISTER_LOAD)
1027 NODE_NAME_CASE(REGISTER_STORE)
1028 NODE_NAME_CASE(LOAD_CONSTANT)
1029 NODE_NAME_CASE(LOAD_INPUT)
1030 NODE_NAME_CASE(SAMPLE)
1031 NODE_NAME_CASE(SAMPLEB)
1032 NODE_NAME_CASE(SAMPLED)
1033 NODE_NAME_CASE(SAMPLEL)
1034 NODE_NAME_CASE(STORE_MSKOR)
1035 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)