1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
108 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
110 setOperationAction(ISD::Constant, MVT::i32, Legal);
111 setOperationAction(ISD::Constant, MVT::i64, Legal);
112 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
113 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
115 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
116 setOperationAction(ISD::BRIND, MVT::Other, Expand);
118 // We need to custom lower some of the intrinsics
119 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
121 // Library functions. These default to Expand, but we have instructions
123 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
124 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
125 setOperationAction(ISD::FPOW, MVT::f32, Legal);
126 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
127 setOperationAction(ISD::FABS, MVT::f32, Legal);
128 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
129 setOperationAction(ISD::FRINT, MVT::f32, Legal);
130 setOperationAction(ISD::FROUND, MVT::f32, Legal);
131 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
133 setOperationAction(ISD::FREM, MVT::f32, Custom);
134 setOperationAction(ISD::FREM, MVT::f64, Custom);
136 // Lower floating point store/load to integer store/load to reduce the number
137 // of patterns in tablegen.
138 setOperationAction(ISD::STORE, MVT::f32, Promote);
139 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
141 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
142 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
144 setOperationAction(ISD::STORE, MVT::i64, Promote);
145 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
147 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
148 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
150 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
153 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
154 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
156 setOperationAction(ISD::STORE, MVT::f64, Promote);
157 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
159 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
160 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
162 // Custom lowering of vector stores is required for local address space
164 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
165 // XXX: Native v2i32 local address space stores are possible, but not
166 // currently implemented.
167 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
169 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
170 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
171 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
173 // XXX: This can be change to Custom, once ExpandVectorStores can
174 // handle 64-bit stores.
175 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
177 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
178 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
179 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
180 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
181 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
184 setOperationAction(ISD::LOAD, MVT::f32, Promote);
185 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
187 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
190 setOperationAction(ISD::LOAD, MVT::i64, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
193 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
196 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
199 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
200 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
202 setOperationAction(ISD::LOAD, MVT::f64, Promote);
203 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
205 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
206 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
210 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
211 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
216 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
217 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
219 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
220 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
221 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
222 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
223 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
224 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
225 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
226 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
227 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
228 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
229 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
230 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
232 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
234 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
235 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
236 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
237 setOperationAction(ISD::FRINT, MVT::f64, Custom);
238 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
241 if (!Subtarget->hasBFI()) {
242 // fcopysign can be done in a single instruction with BFI.
243 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
244 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
247 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
249 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
250 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
251 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
253 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
254 for (MVT VT : ScalarIntVTs) {
255 setOperationAction(ISD::SREM, VT, Expand);
256 setOperationAction(ISD::SDIV, VT, Expand);
258 // GPU does not have divrem function for signed or unsigned.
259 setOperationAction(ISD::SDIVREM, VT, Custom);
260 setOperationAction(ISD::UDIVREM, VT, Custom);
262 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
263 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
264 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
266 setOperationAction(ISD::BSWAP, VT, Expand);
267 setOperationAction(ISD::CTTZ, VT, Expand);
268 setOperationAction(ISD::CTLZ, VT, Expand);
271 if (!Subtarget->hasBCNT(32))
272 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
274 if (!Subtarget->hasBCNT(64))
275 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
277 // The hardware supports 32-bit ROTR, but not ROTL.
278 setOperationAction(ISD::ROTL, MVT::i32, Expand);
279 setOperationAction(ISD::ROTL, MVT::i64, Expand);
280 setOperationAction(ISD::ROTR, MVT::i64, Expand);
282 setOperationAction(ISD::MUL, MVT::i64, Expand);
283 setOperationAction(ISD::MULHU, MVT::i64, Expand);
284 setOperationAction(ISD::MULHS, MVT::i64, Expand);
285 setOperationAction(ISD::UDIV, MVT::i32, Expand);
286 setOperationAction(ISD::UREM, MVT::i32, Expand);
287 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
288 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
289 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
290 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
291 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
293 if (!Subtarget->hasFFBH())
294 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
296 if (!Subtarget->hasFFBL())
297 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
299 static const MVT::SimpleValueType VectorIntTypes[] = {
300 MVT::v2i32, MVT::v4i32
303 for (MVT VT : VectorIntTypes) {
304 // Expand the following operations for the current type by default.
305 setOperationAction(ISD::ADD, VT, Expand);
306 setOperationAction(ISD::AND, VT, Expand);
307 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
308 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
309 setOperationAction(ISD::MUL, VT, Expand);
310 setOperationAction(ISD::OR, VT, Expand);
311 setOperationAction(ISD::SHL, VT, Expand);
312 setOperationAction(ISD::SRA, VT, Expand);
313 setOperationAction(ISD::SRL, VT, Expand);
314 setOperationAction(ISD::ROTL, VT, Expand);
315 setOperationAction(ISD::ROTR, VT, Expand);
316 setOperationAction(ISD::SUB, VT, Expand);
317 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
318 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
319 setOperationAction(ISD::SDIV, VT, Expand);
320 setOperationAction(ISD::UDIV, VT, Expand);
321 setOperationAction(ISD::SREM, VT, Expand);
322 setOperationAction(ISD::UREM, VT, Expand);
323 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
324 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
325 setOperationAction(ISD::SDIVREM, VT, Custom);
326 setOperationAction(ISD::UDIVREM, VT, Custom);
327 setOperationAction(ISD::ADDC, VT, Expand);
328 setOperationAction(ISD::SUBC, VT, Expand);
329 setOperationAction(ISD::ADDE, VT, Expand);
330 setOperationAction(ISD::SUBE, VT, Expand);
331 setOperationAction(ISD::SELECT, VT, Expand);
332 setOperationAction(ISD::VSELECT, VT, Expand);
333 setOperationAction(ISD::SELECT_CC, VT, Expand);
334 setOperationAction(ISD::XOR, VT, Expand);
335 setOperationAction(ISD::BSWAP, VT, Expand);
336 setOperationAction(ISD::CTPOP, VT, Expand);
337 setOperationAction(ISD::CTTZ, VT, Expand);
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
339 setOperationAction(ISD::CTLZ, VT, Expand);
340 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
341 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
344 static const MVT::SimpleValueType FloatVectorTypes[] = {
345 MVT::v2f32, MVT::v4f32
348 for (MVT VT : FloatVectorTypes) {
349 setOperationAction(ISD::FABS, VT, Expand);
350 setOperationAction(ISD::FMINNUM, VT, Expand);
351 setOperationAction(ISD::FMAXNUM, VT, Expand);
352 setOperationAction(ISD::FADD, VT, Expand);
353 setOperationAction(ISD::FCEIL, VT, Expand);
354 setOperationAction(ISD::FCOS, VT, Expand);
355 setOperationAction(ISD::FDIV, VT, Expand);
356 setOperationAction(ISD::FEXP2, VT, Expand);
357 setOperationAction(ISD::FLOG2, VT, Expand);
358 setOperationAction(ISD::FREM, VT, Expand);
359 setOperationAction(ISD::FPOW, VT, Expand);
360 setOperationAction(ISD::FFLOOR, VT, Expand);
361 setOperationAction(ISD::FTRUNC, VT, Expand);
362 setOperationAction(ISD::FMUL, VT, Expand);
363 setOperationAction(ISD::FMA, VT, Expand);
364 setOperationAction(ISD::FRINT, VT, Expand);
365 setOperationAction(ISD::FNEARBYINT, VT, Expand);
366 setOperationAction(ISD::FSQRT, VT, Expand);
367 setOperationAction(ISD::FSIN, VT, Expand);
368 setOperationAction(ISD::FSUB, VT, Expand);
369 setOperationAction(ISD::FNEG, VT, Expand);
370 setOperationAction(ISD::SELECT, VT, Expand);
371 setOperationAction(ISD::VSELECT, VT, Expand);
372 setOperationAction(ISD::SELECT_CC, VT, Expand);
373 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
374 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
377 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
378 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
380 setTargetDAGCombine(ISD::MUL);
381 setTargetDAGCombine(ISD::SELECT);
382 setTargetDAGCombine(ISD::SELECT_CC);
383 setTargetDAGCombine(ISD::STORE);
385 setSchedulingPreference(Sched::RegPressure);
386 setJumpIsExpensive(true);
388 // SI at least has hardware support for floating point exceptions, but no way
389 // of using or handling them is implemented. They are also optional in OpenCL
391 setHasFloatingPointExceptions(false);
393 setSelectIsExpensive(false);
394 PredictableSelectIsExpensive = false;
396 // There are no integer divide instructions, and these expand to a pretty
397 // large sequence of instructions.
398 setIntDivIsCheap(false);
399 setPow2SDivIsCheap(false);
401 // FIXME: Need to really handle these.
402 MaxStoresPerMemcpy = 4096;
403 MaxStoresPerMemmove = 4096;
404 MaxStoresPerMemset = 4096;
407 //===----------------------------------------------------------------------===//
408 // Target Information
409 //===----------------------------------------------------------------------===//
411 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
415 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
419 // The backend supports 32 and 64 bit floating point immediates.
420 // FIXME: Why are we reporting vectors of FP immediates as legal?
421 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
422 EVT ScalarVT = VT.getScalarType();
423 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
426 // We don't want to shrink f64 / f32 constants.
427 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
428 EVT ScalarVT = VT.getScalarType();
429 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
432 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
434 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
437 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
438 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
440 return ((LScalarSize <= CastScalarSize) ||
441 (CastScalarSize >= 32) ||
445 //===---------------------------------------------------------------------===//
447 //===---------------------------------------------------------------------===//
449 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
450 assert(VT.isFloatingPoint());
451 return VT == MVT::f32 || VT == MVT::f64;
454 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
455 assert(VT.isFloatingPoint());
456 return VT == MVT::f32 || VT == MVT::f64;
459 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
460 // Truncate is just accessing a subregister.
461 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
464 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
465 // Truncate is just accessing a subregister.
466 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
467 (Dest->getPrimitiveSizeInBits() % 32 == 0);
470 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
471 const DataLayout *DL = getDataLayout();
472 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
473 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
475 return SrcSize == 32 && DestSize == 64;
478 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
479 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
480 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
481 // this will enable reducing 64-bit operations the 32-bit, which is always
483 return Src == MVT::i32 && Dest == MVT::i64;
486 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
487 return isZExtFree(Val.getValueType(), VT2);
490 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
491 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
492 // limited number of native 64-bit operations. Shrinking an operation to fit
493 // in a single 32-bit register should always be helpful. As currently used,
494 // this is much less general than the name suggests, and is only used in
495 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
496 // not profitable, and may actually be harmful.
497 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
500 //===---------------------------------------------------------------------===//
501 // TargetLowering Callbacks
502 //===---------------------------------------------------------------------===//
504 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
505 const SmallVectorImpl<ISD::InputArg> &Ins) const {
507 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
510 SDValue AMDGPUTargetLowering::LowerReturn(
512 CallingConv::ID CallConv,
514 const SmallVectorImpl<ISD::OutputArg> &Outs,
515 const SmallVectorImpl<SDValue> &OutVals,
516 SDLoc DL, SelectionDAG &DAG) const {
517 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
520 //===---------------------------------------------------------------------===//
521 // Target specific lowering
522 //===---------------------------------------------------------------------===//
524 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
525 SmallVectorImpl<SDValue> &InVals) const {
526 SDValue Callee = CLI.Callee;
527 SelectionDAG &DAG = CLI.DAG;
529 const Function &Fn = *DAG.getMachineFunction().getFunction();
531 StringRef FuncName("<unknown>");
533 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
534 FuncName = G->getSymbol();
535 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
536 FuncName = G->getGlobal()->getName();
538 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
539 DAG.getContext()->diagnose(NoCalls);
543 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
544 SelectionDAG &DAG) const {
545 switch (Op.getOpcode()) {
547 Op.getNode()->dump();
548 llvm_unreachable("Custom lowering code for this"
549 "instruction is not implemented yet!");
551 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
552 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
553 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
554 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
555 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
556 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
557 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
558 case ISD::FREM: return LowerFREM(Op, DAG);
559 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
560 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
561 case ISD::FRINT: return LowerFRINT(Op, DAG);
562 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
563 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
564 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
565 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
566 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
567 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
572 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
573 SmallVectorImpl<SDValue> &Results,
574 SelectionDAG &DAG) const {
575 switch (N->getOpcode()) {
576 case ISD::SIGN_EXTEND_INREG:
577 // Different parts of legalization seem to interpret which type of
578 // sign_extend_inreg is the one to check for custom lowering. The extended
579 // from type is what really matters, but some places check for custom
580 // lowering of the result type. This results in trying to use
581 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
582 // nothing here and let the illegal result integer be handled normally.
585 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
589 Results.push_back(SDValue(Node, 0));
590 Results.push_back(SDValue(Node, 1));
591 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
593 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
597 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
598 if (Lowered.getNode())
599 Results.push_back(Lowered);
607 // FIXME: This implements accesses to initialized globals in the constant
608 // address space by copying them to private and accessing that. It does not
609 // properly handle illegal types or vectors. The private vector loads are not
610 // scalarized, and the illegal scalars hit an assertion. This technique will not
611 // work well with large initializers, and this should eventually be
612 // removed. Initialized globals should be placed into a data section that the
613 // runtime will load into a buffer before the kernel is executed. Uses of the
614 // global need to be replaced with a pointer loaded from an implicit kernel
615 // argument into this buffer holding the copy of the data, which will remove the
616 // need for any of this.
617 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
618 const GlobalValue *GV,
619 const SDValue &InitPtr,
621 SelectionDAG &DAG) const {
622 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
624 Type *InitTy = Init->getType();
626 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
627 EVT VT = EVT::getEVT(InitTy);
628 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
629 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
630 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
631 TD->getPrefTypeAlignment(InitTy));
634 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
635 EVT VT = EVT::getEVT(CFP->getType());
636 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
637 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
638 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
639 TD->getPrefTypeAlignment(CFP->getType()));
642 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
643 const StructLayout *SL = TD->getStructLayout(ST);
645 EVT PtrVT = InitPtr.getValueType();
646 SmallVector<SDValue, 8> Chains;
648 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
649 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
650 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
652 Constant *Elt = Init->getAggregateElement(I);
653 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
656 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
659 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
660 EVT PtrVT = InitPtr.getValueType();
662 unsigned NumElements;
663 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
664 NumElements = AT->getNumElements();
665 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
666 NumElements = VT->getNumElements();
668 llvm_unreachable("Unexpected type");
670 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
671 SmallVector<SDValue, 8> Chains;
672 for (unsigned i = 0; i < NumElements; ++i) {
673 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
674 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
676 Constant *Elt = Init->getAggregateElement(i);
677 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
680 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
683 if (isa<UndefValue>(Init)) {
684 EVT VT = EVT::getEVT(InitTy);
685 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
686 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
687 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
688 TD->getPrefTypeAlignment(InitTy));
692 llvm_unreachable("Unhandled constant initializer");
695 static bool hasDefinedInitializer(const GlobalValue *GV) {
696 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
697 if (!GVar || !GVar->hasInitializer())
700 if (isa<UndefValue>(GVar->getInitializer()))
706 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
708 SelectionDAG &DAG) const {
710 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
711 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
712 const GlobalValue *GV = G->getGlobal();
714 switch (G->getAddressSpace()) {
715 case AMDGPUAS::LOCAL_ADDRESS: {
716 // XXX: What does the value of G->getOffset() mean?
717 assert(G->getOffset() == 0 &&
718 "Do not know what to do with an non-zero offset");
720 // TODO: We could emit code to handle the initialization somewhere.
721 if (hasDefinedInitializer(GV))
725 if (MFI->LocalMemoryObjects.count(GV) == 0) {
726 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
727 Offset = MFI->LDSSize;
728 MFI->LocalMemoryObjects[GV] = Offset;
729 // XXX: Account for alignment?
730 MFI->LDSSize += Size;
732 Offset = MFI->LocalMemoryObjects[GV];
735 return DAG.getConstant(Offset, getPointerTy(AMDGPUAS::LOCAL_ADDRESS));
737 case AMDGPUAS::CONSTANT_ADDRESS: {
738 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
739 Type *EltType = GV->getType()->getElementType();
740 unsigned Size = TD->getTypeAllocSize(EltType);
741 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
743 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
744 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
746 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
747 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
749 const GlobalVariable *Var = cast<GlobalVariable>(GV);
750 if (!Var->hasInitializer()) {
751 // This has no use, but bugpoint will hit it.
752 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
755 const Constant *Init = Var->getInitializer();
756 SmallVector<SDNode*, 8> WorkList;
758 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
759 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
760 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
762 WorkList.push_back(*I);
764 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
765 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
766 E = WorkList.end(); I != E; ++I) {
767 SmallVector<SDValue, 8> Ops;
768 Ops.push_back(Chain);
769 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
770 Ops.push_back((*I)->getOperand(i));
772 DAG.UpdateNodeOperands(*I, Ops);
774 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
778 const Function &Fn = *DAG.getMachineFunction().getFunction();
779 DiagnosticInfoUnsupported BadInit(Fn,
780 "initializer for address space");
781 DAG.getContext()->diagnose(BadInit);
785 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
786 SelectionDAG &DAG) const {
787 SmallVector<SDValue, 8> Args;
788 SDValue A = Op.getOperand(0);
789 SDValue B = Op.getOperand(1);
791 DAG.ExtractVectorElements(A, Args);
792 DAG.ExtractVectorElements(B, Args);
794 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
797 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
798 SelectionDAG &DAG) const {
800 SmallVector<SDValue, 8> Args;
801 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
802 EVT VT = Op.getValueType();
803 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
804 VT.getVectorNumElements());
806 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
809 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
810 SelectionDAG &DAG) const {
812 MachineFunction &MF = DAG.getMachineFunction();
813 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
814 getTargetMachine().getSubtargetImpl()->getFrameLowering());
816 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
818 unsigned FrameIndex = FIN->getIndex();
819 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
820 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
824 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
825 SelectionDAG &DAG) const {
826 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
828 EVT VT = Op.getValueType();
830 switch (IntrinsicID) {
832 case AMDGPUIntrinsic::AMDGPU_abs:
833 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
834 return LowerIntrinsicIABS(Op, DAG);
835 case AMDGPUIntrinsic::AMDGPU_lrp:
836 return LowerIntrinsicLRP(Op, DAG);
837 case AMDGPUIntrinsic::AMDGPU_fract:
838 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
839 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
841 case AMDGPUIntrinsic::AMDGPU_clamp:
842 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
843 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
844 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
846 case Intrinsic::AMDGPU_div_scale: {
847 // 3rd parameter required to be a constant.
848 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
850 return DAG.getUNDEF(VT);
852 // Translate to the operands expected by the machine instruction. The
853 // first parameter must be the same as the first instruction.
854 SDValue Numerator = Op.getOperand(1);
855 SDValue Denominator = Op.getOperand(2);
857 // Note this order is opposite of the machine instruction's operations,
858 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
859 // intrinsic has the numerator as the first operand to match a normal
860 // division operation.
862 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
864 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
865 Denominator, Numerator);
868 case Intrinsic::AMDGPU_div_fmas:
869 // FIXME: Dropping bool parameter. Work is needed to support the implicit
871 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
872 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
874 case Intrinsic::AMDGPU_div_fixup:
875 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
876 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
878 case Intrinsic::AMDGPU_trig_preop:
879 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
880 Op.getOperand(1), Op.getOperand(2));
882 case Intrinsic::AMDGPU_rcp:
883 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
885 case Intrinsic::AMDGPU_rsq:
886 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
888 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
889 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
891 case Intrinsic::AMDGPU_rsq_clamped:
892 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
894 case Intrinsic::AMDGPU_ldexp:
895 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
898 case AMDGPUIntrinsic::AMDGPU_imax:
899 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
901 case AMDGPUIntrinsic::AMDGPU_umax:
902 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
904 case AMDGPUIntrinsic::AMDGPU_imin:
905 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
907 case AMDGPUIntrinsic::AMDGPU_umin:
908 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
911 case AMDGPUIntrinsic::AMDGPU_umul24:
912 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
913 Op.getOperand(1), Op.getOperand(2));
915 case AMDGPUIntrinsic::AMDGPU_imul24:
916 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
917 Op.getOperand(1), Op.getOperand(2));
919 case AMDGPUIntrinsic::AMDGPU_umad24:
920 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
921 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
923 case AMDGPUIntrinsic::AMDGPU_imad24:
924 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
925 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
927 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
928 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
930 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
931 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
933 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
934 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
936 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
937 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
939 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
940 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
945 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
946 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
951 case AMDGPUIntrinsic::AMDGPU_bfi:
952 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
957 case AMDGPUIntrinsic::AMDGPU_bfm:
958 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
962 case AMDGPUIntrinsic::AMDGPU_brev:
963 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
965 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
966 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
968 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
969 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
970 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
971 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
975 ///IABS(a) = SMAX(sub(0, a), a)
976 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
977 SelectionDAG &DAG) const {
979 EVT VT = Op.getValueType();
980 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
983 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
986 /// Linear Interpolation
987 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
988 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
989 SelectionDAG &DAG) const {
991 EVT VT = Op.getValueType();
992 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
993 DAG.getConstantFP(1.0f, MVT::f32),
995 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
997 return DAG.getNode(ISD::FADD, DL, VT,
998 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1002 /// \brief Generate Min/Max node
1003 SDValue AMDGPUTargetLowering::CombineFMinMax(SDLoc DL,
1010 SelectionDAG &DAG) const {
1011 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1014 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1023 case ISD::SETFALSE2:
1036 = (LHS == True) ? AMDGPUISD::FMIN_LEGACY : AMDGPUISD::FMAX_LEGACY;
1037 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1046 = (LHS == True) ? AMDGPUISD::FMAX_LEGACY : AMDGPUISD::FMIN_LEGACY;
1047 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1049 case ISD::SETCC_INVALID:
1050 llvm_unreachable("Invalid setcc condcode!");
1055 /// \brief Generate Min/Max node
1056 SDValue AMDGPUTargetLowering::CombineIMinMax(SDLoc DL,
1063 SelectionDAG &DAG) const {
1064 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1067 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1071 unsigned Opc = (LHS == True) ? AMDGPUISD::UMIN : AMDGPUISD::UMAX;
1072 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1076 unsigned Opc = (LHS == True) ? AMDGPUISD::SMIN : AMDGPUISD::SMAX;
1077 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1081 unsigned Opc = (LHS == True) ? AMDGPUISD::SMAX : AMDGPUISD::SMIN;
1082 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1086 unsigned Opc = (LHS == True) ? AMDGPUISD::UMAX : AMDGPUISD::UMIN;
1087 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1094 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1095 SelectionDAG &DAG) const {
1096 LoadSDNode *Load = cast<LoadSDNode>(Op);
1097 EVT MemVT = Load->getMemoryVT();
1098 EVT MemEltVT = MemVT.getVectorElementType();
1100 EVT LoadVT = Op.getValueType();
1101 EVT EltVT = LoadVT.getVectorElementType();
1102 EVT PtrVT = Load->getBasePtr().getValueType();
1104 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1105 SmallVector<SDValue, 8> Loads;
1106 SmallVector<SDValue, 8> Chains;
1109 unsigned MemEltSize = MemEltVT.getStoreSize();
1110 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1112 for (unsigned i = 0; i < NumElts; ++i) {
1113 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1114 DAG.getConstant(i * MemEltSize, PtrVT));
1117 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1118 Load->getChain(), Ptr,
1119 SrcValue.getWithOffset(i * MemEltSize),
1120 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1121 Load->isInvariant(), Load->getAlignment());
1122 Loads.push_back(NewLoad.getValue(0));
1123 Chains.push_back(NewLoad.getValue(1));
1127 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1128 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1131 return DAG.getMergeValues(Ops, SL);
1134 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1135 SelectionDAG &DAG) const {
1136 EVT VT = Op.getValueType();
1138 // If this is a 2 element vector, we really want to scalarize and not create
1139 // weird 1 element vectors.
1140 if (VT.getVectorNumElements() == 2)
1141 return ScalarizeVectorLoad(Op, DAG);
1143 LoadSDNode *Load = cast<LoadSDNode>(Op);
1144 SDValue BasePtr = Load->getBasePtr();
1145 EVT PtrVT = BasePtr.getValueType();
1146 EVT MemVT = Load->getMemoryVT();
1148 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1151 EVT LoMemVT, HiMemVT;
1154 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1155 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1156 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1158 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1159 Load->getChain(), BasePtr,
1161 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1162 Load->isInvariant(), Load->getAlignment());
1164 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1165 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1168 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1169 Load->getChain(), HiPtr,
1170 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1171 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1172 Load->isInvariant(), Load->getAlignment());
1175 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1176 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1177 LoLoad.getValue(1), HiLoad.getValue(1))
1180 return DAG.getMergeValues(Ops, SL);
1183 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1184 SelectionDAG &DAG) const {
1185 StoreSDNode *Store = cast<StoreSDNode>(Op);
1186 EVT MemVT = Store->getMemoryVT();
1187 unsigned MemBits = MemVT.getSizeInBits();
1189 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1190 // truncating store into an i32 store.
1191 // XXX: We could also handle optimize other vector bitwidths.
1192 if (!MemVT.isVector() || MemBits > 32) {
1197 SDValue Value = Store->getValue();
1198 EVT VT = Value.getValueType();
1199 EVT ElemVT = VT.getVectorElementType();
1200 SDValue Ptr = Store->getBasePtr();
1201 EVT MemEltVT = MemVT.getVectorElementType();
1202 unsigned MemEltBits = MemEltVT.getSizeInBits();
1203 unsigned MemNumElements = MemVT.getVectorNumElements();
1204 unsigned PackedSize = MemVT.getStoreSizeInBits();
1205 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1207 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1209 SDValue PackedValue;
1210 for (unsigned i = 0; i < MemNumElements; ++i) {
1211 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1212 DAG.getConstant(i, MVT::i32));
1213 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1214 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1216 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1217 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1222 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1226 if (PackedSize < 32) {
1227 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1228 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1229 Store->getMemOperand()->getPointerInfo(),
1231 Store->isNonTemporal(), Store->isVolatile(),
1232 Store->getAlignment());
1235 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1236 Store->getMemOperand()->getPointerInfo(),
1237 Store->isVolatile(), Store->isNonTemporal(),
1238 Store->getAlignment());
1241 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1242 SelectionDAG &DAG) const {
1243 StoreSDNode *Store = cast<StoreSDNode>(Op);
1244 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1245 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1246 EVT PtrVT = Store->getBasePtr().getValueType();
1247 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1250 SmallVector<SDValue, 8> Chains;
1252 unsigned EltSize = MemEltVT.getStoreSize();
1253 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1255 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1256 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1258 DAG.getConstant(i, MVT::i32));
1260 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), PtrVT);
1261 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1263 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1264 SrcValue.getWithOffset(i * EltSize),
1265 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1266 Store->getAlignment());
1267 Chains.push_back(NewStore);
1270 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1273 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1274 SelectionDAG &DAG) const {
1275 StoreSDNode *Store = cast<StoreSDNode>(Op);
1276 SDValue Val = Store->getValue();
1277 EVT VT = Val.getValueType();
1279 // If this is a 2 element vector, we really want to scalarize and not create
1280 // weird 1 element vectors.
1281 if (VT.getVectorNumElements() == 2)
1282 return ScalarizeVectorStore(Op, DAG);
1284 EVT MemVT = Store->getMemoryVT();
1285 SDValue Chain = Store->getChain();
1286 SDValue BasePtr = Store->getBasePtr();
1290 EVT LoMemVT, HiMemVT;
1293 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1294 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1295 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1297 EVT PtrVT = BasePtr.getValueType();
1298 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1299 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1301 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1303 = DAG.getTruncStore(Chain, SL, Lo,
1307 Store->isNonTemporal(),
1308 Store->isVolatile(),
1309 Store->getAlignment());
1311 = DAG.getTruncStore(Chain, SL, Hi,
1313 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1315 Store->isNonTemporal(),
1316 Store->isVolatile(),
1317 Store->getAlignment());
1319 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1323 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1325 LoadSDNode *Load = cast<LoadSDNode>(Op);
1326 ISD::LoadExtType ExtType = Load->getExtensionType();
1327 EVT VT = Op.getValueType();
1328 EVT MemVT = Load->getMemoryVT();
1330 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1331 // We can do the extload to 32-bits, and then need to separately extend to
1334 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1338 Load->getMemOperand());
1341 DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32),
1342 ExtLoad32.getValue(1)
1345 return DAG.getMergeValues(Ops, DL);
1348 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1349 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1350 // FIXME: Copied from PPC
1351 // First, load into 32 bits, then truncate to 1 bit.
1353 SDValue Chain = Load->getChain();
1354 SDValue BasePtr = Load->getBasePtr();
1355 MachineMemOperand *MMO = Load->getMemOperand();
1357 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1358 BasePtr, MVT::i8, MMO);
1361 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1365 return DAG.getMergeValues(Ops, DL);
1368 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1369 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1370 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1374 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1375 DAG.getConstant(2, MVT::i32));
1376 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1377 Load->getChain(), Ptr,
1378 DAG.getTargetConstant(0, MVT::i32),
1380 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1382 DAG.getConstant(0x3, MVT::i32));
1383 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1384 DAG.getConstant(3, MVT::i32));
1386 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1388 EVT MemEltVT = MemVT.getScalarType();
1389 if (ExtType == ISD::SEXTLOAD) {
1390 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1393 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1397 return DAG.getMergeValues(Ops, DL);
1401 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1405 return DAG.getMergeValues(Ops, DL);
1408 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1410 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1411 if (Result.getNode()) {
1415 StoreSDNode *Store = cast<StoreSDNode>(Op);
1416 SDValue Chain = Store->getChain();
1417 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1418 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1419 Store->getValue().getValueType().isVector()) {
1420 return ScalarizeVectorStore(Op, DAG);
1423 EVT MemVT = Store->getMemoryVT();
1424 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1425 MemVT.bitsLT(MVT::i32)) {
1427 if (Store->getMemoryVT() == MVT::i8) {
1429 } else if (Store->getMemoryVT() == MVT::i16) {
1432 SDValue BasePtr = Store->getBasePtr();
1433 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1434 DAG.getConstant(2, MVT::i32));
1435 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1436 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1438 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1439 DAG.getConstant(0x3, MVT::i32));
1441 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1442 DAG.getConstant(3, MVT::i32));
1444 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1447 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1449 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1450 MaskedValue, ShiftAmt);
1452 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1454 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1455 DAG.getConstant(0xffffffff, MVT::i32));
1456 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1458 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1459 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1460 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1465 // This is a shortcut for integer division because we have fast i32<->f32
1466 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1467 // float is enough to accurately represent up to a 24-bit integer.
1468 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1470 EVT VT = Op.getValueType();
1471 SDValue LHS = Op.getOperand(0);
1472 SDValue RHS = Op.getOperand(1);
1473 MVT IntVT = MVT::i32;
1474 MVT FltVT = MVT::f32;
1476 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1477 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1479 if (VT.isVector()) {
1480 unsigned NElts = VT.getVectorNumElements();
1481 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1482 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1485 unsigned BitSize = VT.getScalarType().getSizeInBits();
1487 SDValue jq = DAG.getConstant(1, IntVT);
1490 // char|short jq = ia ^ ib;
1491 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1493 // jq = jq >> (bitsize - 2)
1494 jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
1497 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));
1500 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1503 // int ia = (int)LHS;
1505 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1507 // int ib, (int)RHS;
1509 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1511 // float fa = (float)ia;
1512 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1514 // float fb = (float)ib;
1515 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1517 // float fq = native_divide(fa, fb);
1518 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1519 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1522 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1524 // float fqneg = -fq;
1525 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1527 // float fr = mad(fqneg, fb, fa);
1528 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1529 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1531 // int iq = (int)fq;
1532 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1535 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1538 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1540 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), VT);
1542 // int cv = fr >= fb;
1543 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1545 // jq = (cv ? jq : 0);
1546 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
1548 // dst = trunc/extend to legal type
1549 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1552 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1554 // Rem needs compensation, it's easier to recompute it
1555 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1556 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1562 return DAG.getMergeValues(Res, DL);
1565 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1566 SelectionDAG &DAG) const {
1568 EVT VT = Op.getValueType();
1570 SDValue Num = Op.getOperand(0);
1571 SDValue Den = Op.getOperand(1);
1573 if (VT == MVT::i32) {
1574 if (DAG.MaskedValueIsZero(Op.getOperand(0), APInt(32, 0xff << 24)) &&
1575 DAG.MaskedValueIsZero(Op.getOperand(1), APInt(32, 0xff << 24))) {
1576 // TODO: We technically could do this for i64, but shouldn't that just be
1577 // handled by something generally reducing 64-bit division on 32-bit
1578 // values to 32-bit?
1579 return LowerDIVREM24(Op, DAG, false);
1583 // RCP = URECIP(Den) = 2^32 / Den + e
1584 // e is rounding error.
1585 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1587 // RCP_LO = mul(RCP, Den) */
1588 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1590 // RCP_HI = mulhu (RCP, Den) */
1591 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1593 // NEG_RCP_LO = -RCP_LO
1594 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1597 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1598 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1601 // Calculate the rounding error from the URECIP instruction
1602 // E = mulhu(ABS_RCP_LO, RCP)
1603 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1605 // RCP_A_E = RCP + E
1606 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1608 // RCP_S_E = RCP - E
1609 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1611 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1612 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1615 // Quotient = mulhu(Tmp0, Num)
1616 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1618 // Num_S_Remainder = Quotient * Den
1619 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1621 // Remainder = Num - Num_S_Remainder
1622 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1624 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1625 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1626 DAG.getConstant(-1, VT),
1627 DAG.getConstant(0, VT),
1629 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1630 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1632 DAG.getConstant(-1, VT),
1633 DAG.getConstant(0, VT),
1635 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1636 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1639 // Calculate Division result:
1641 // Quotient_A_One = Quotient + 1
1642 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1643 DAG.getConstant(1, VT));
1645 // Quotient_S_One = Quotient - 1
1646 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1647 DAG.getConstant(1, VT));
1649 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1650 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1651 Quotient, Quotient_A_One, ISD::SETEQ);
1653 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1654 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1655 Quotient_S_One, Div, ISD::SETEQ);
1657 // Calculate Rem result:
1659 // Remainder_S_Den = Remainder - Den
1660 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1662 // Remainder_A_Den = Remainder + Den
1663 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1665 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1666 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1667 Remainder, Remainder_S_Den, ISD::SETEQ);
1669 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1670 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1671 Remainder_A_Den, Rem, ISD::SETEQ);
1676 return DAG.getMergeValues(Ops, DL);
1679 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1680 SelectionDAG &DAG) const {
1682 EVT VT = Op.getValueType();
1684 SDValue LHS = Op.getOperand(0);
1685 SDValue RHS = Op.getOperand(1);
1687 if (VT == MVT::i32) {
1688 if (DAG.ComputeNumSignBits(Op.getOperand(0)) > 8 &&
1689 DAG.ComputeNumSignBits(Op.getOperand(1)) > 8) {
1690 // TODO: We technically could do this for i64, but shouldn't that just be
1691 // handled by something generally reducing 64-bit division on 32-bit
1692 // values to 32-bit?
1693 return LowerDIVREM24(Op, DAG, true);
1697 SDValue Zero = DAG.getConstant(0, VT);
1698 SDValue NegOne = DAG.getConstant(-1, VT);
1700 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1701 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1702 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1703 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1705 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1706 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1708 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1709 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1711 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1712 SDValue Rem = Div.getValue(1);
1714 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1715 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1717 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1718 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1724 return DAG.getMergeValues(Res, DL);
1727 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1728 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1730 EVT VT = Op.getValueType();
1731 SDValue X = Op.getOperand(0);
1732 SDValue Y = Op.getOperand(1);
1734 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1735 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1736 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1738 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1741 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1743 SDValue Src = Op.getOperand(0);
1745 // result = trunc(src)
1746 // if (src > 0.0 && src != result)
1749 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1751 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1752 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1754 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1756 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1757 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1758 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1760 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1761 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1764 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1766 SDValue Src = Op.getOperand(0);
1768 assert(Op.getValueType() == MVT::f64);
1770 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1771 const SDValue One = DAG.getConstant(1, MVT::i32);
1773 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1775 // Extract the upper half, since this is where we will find the sign and
1777 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1779 const unsigned FractBits = 52;
1780 const unsigned ExpBits = 11;
1782 // Extract the exponent.
1783 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1785 DAG.getConstant(FractBits - 32, MVT::i32),
1786 DAG.getConstant(ExpBits, MVT::i32));
1787 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1788 DAG.getConstant(1023, MVT::i32));
1790 // Extract the sign bit.
1791 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1792 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1794 // Extend back to to 64-bits.
1795 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1797 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1799 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1800 const SDValue FractMask
1801 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1803 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1804 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1805 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1807 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1809 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1811 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1812 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1814 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1815 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1817 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1820 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1822 SDValue Src = Op.getOperand(0);
1824 assert(Op.getValueType() == MVT::f64);
1826 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1827 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1828 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1830 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1831 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1833 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1835 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1836 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
1838 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1839 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1841 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1844 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1845 // FNEARBYINT and FRINT are the same, except in their handling of FP
1846 // exceptions. Those aren't really meaningful for us, and OpenCL only has
1847 // rint, so just treat them as equivalent.
1848 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1851 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1853 SDValue Src = Op.getOperand(0);
1855 // result = trunc(src);
1856 // if (src < 0.0 && src != result)
1859 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1861 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1862 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
1864 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1866 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
1867 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1868 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1870 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
1871 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1874 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
1875 bool Signed) const {
1877 SDValue Src = Op.getOperand(0);
1879 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1881 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
1882 DAG.getConstant(0, MVT::i32));
1883 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
1884 DAG.getConstant(1, MVT::i32));
1886 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
1889 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
1891 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
1892 DAG.getConstant(32, MVT::i32));
1894 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
1897 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1898 SelectionDAG &DAG) const {
1899 SDValue S0 = Op.getOperand(0);
1900 if (S0.getValueType() != MVT::i64)
1903 EVT DestVT = Op.getValueType();
1904 if (DestVT == MVT::f64)
1905 return LowerINT_TO_FP64(Op, DAG, false);
1907 assert(DestVT == MVT::f32);
1911 // f32 uint_to_fp i64
1912 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1913 DAG.getConstant(0, MVT::i32));
1914 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1915 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1916 DAG.getConstant(1, MVT::i32));
1917 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1918 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1919 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1920 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1923 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
1924 SelectionDAG &DAG) const {
1925 SDValue Src = Op.getOperand(0);
1926 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
1927 return LowerINT_TO_FP64(Op, DAG, true);
1932 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
1933 bool Signed) const {
1936 SDValue Src = Op.getOperand(0);
1938 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1941 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), MVT::f64);
1943 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), MVT::f64);
1945 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
1947 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
1950 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
1952 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
1953 MVT::i32, FloorMul);
1954 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
1956 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
1958 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
1961 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
1962 SelectionDAG &DAG) const {
1963 SDValue Src = Op.getOperand(0);
1965 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
1966 return LowerFP64_TO_INT(Op, DAG, true);
1971 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
1972 SelectionDAG &DAG) const {
1973 SDValue Src = Op.getOperand(0);
1975 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
1976 return LowerFP64_TO_INT(Op, DAG, false);
1981 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1982 SelectionDAG &DAG) const {
1983 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1984 MVT VT = Op.getSimpleValueType();
1985 MVT ScalarVT = VT.getScalarType();
1990 SDValue Src = Op.getOperand(0);
1993 // TODO: Don't scalarize on Evergreen?
1994 unsigned NElts = VT.getVectorNumElements();
1995 SmallVector<SDValue, 8> Args;
1996 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1998 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1999 for (unsigned I = 0; I < NElts; ++I)
2000 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2002 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2005 //===----------------------------------------------------------------------===//
2006 // Custom DAG optimizations
2007 //===----------------------------------------------------------------------===//
2009 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2010 APInt KnownZero, KnownOne;
2011 EVT VT = Op.getValueType();
2012 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2014 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2017 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2018 EVT VT = Op.getValueType();
2020 // In order for this to be a signed 24-bit value, bit 23, must
2022 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2023 // as unsigned 24-bit values.
2024 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2027 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2029 SelectionDAG &DAG = DCI.DAG;
2030 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2031 EVT VT = Op.getValueType();
2033 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2034 APInt KnownZero, KnownOne;
2035 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2036 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2037 DCI.CommitTargetLoweringOpt(TLO);
2040 template <typename IntTy>
2041 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2042 uint32_t Offset, uint32_t Width) {
2043 if (Width + Offset < 32) {
2044 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2045 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2046 return DAG.getConstant(Result, MVT::i32);
2049 return DAG.getConstant(Src0 >> Offset, MVT::i32);
2052 static bool usesAllNormalStores(SDNode *LoadVal) {
2053 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2054 if (!ISD::isNormalStore(*I))
2061 // If we have a copy of an illegal type, replace it with a load / store of an
2062 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2063 // instructions emitted when handling extloads and truncstores. Ideally we could
2064 // recognize the pack / unpack pattern to eliminate it.
2065 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2066 DAGCombinerInfo &DCI) const {
2067 if (!DCI.isBeforeLegalize())
2070 StoreSDNode *SN = cast<StoreSDNode>(N);
2071 SDValue Value = SN->getValue();
2072 EVT VT = Value.getValueType();
2074 if (isTypeLegal(VT) || SN->isVolatile() || !ISD::isNormalLoad(Value.getNode()))
2077 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2078 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2081 EVT MemVT = LoadVal->getMemoryVT();
2084 SelectionDAG &DAG = DCI.DAG;
2085 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2087 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2089 LoadVal->getChain(),
2090 LoadVal->getBasePtr(),
2091 LoadVal->getOffset(),
2093 LoadVal->getMemOperand());
2095 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2096 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2098 return DAG.getStore(SN->getChain(), SL, NewLoad,
2099 SN->getBasePtr(), SN->getMemOperand());
2102 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2103 DAGCombinerInfo &DCI) const {
2104 EVT VT = N->getValueType(0);
2106 if (VT.isVector() || VT.getSizeInBits() > 32)
2109 SelectionDAG &DAG = DCI.DAG;
2112 SDValue N0 = N->getOperand(0);
2113 SDValue N1 = N->getOperand(1);
2116 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2117 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2118 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2119 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2120 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2121 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2122 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2123 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2128 // We need to use sext even for MUL_U24, because MUL_U24 is used
2129 // for signed multiply of 8 and 16-bit types.
2130 return DAG.getSExtOrTrunc(Mul, DL, VT);
2133 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2134 DAGCombinerInfo &DCI) const {
2135 SelectionDAG &DAG = DCI.DAG;
2138 switch(N->getOpcode()) {
2141 return performMulCombine(N, DCI);
2142 case AMDGPUISD::MUL_I24:
2143 case AMDGPUISD::MUL_U24: {
2144 SDValue N0 = N->getOperand(0);
2145 SDValue N1 = N->getOperand(1);
2146 simplifyI24(N0, DCI);
2147 simplifyI24(N1, DCI);
2150 case ISD::SELECT_CC: {
2152 EVT VT = N->getValueType(0);
2154 if (VT == MVT::f32 ||
2156 Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)) {
2157 SDValue LHS = N->getOperand(0);
2158 SDValue RHS = N->getOperand(1);
2159 SDValue True = N->getOperand(2);
2160 SDValue False = N->getOperand(3);
2161 SDValue CC = N->getOperand(4);
2163 return CombineFMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
2169 SDValue Cond = N->getOperand(0);
2170 if (Cond.getOpcode() == ISD::SETCC) {
2172 EVT VT = N->getValueType(0);
2173 SDValue LHS = Cond.getOperand(0);
2174 SDValue RHS = Cond.getOperand(1);
2175 SDValue CC = Cond.getOperand(2);
2177 SDValue True = N->getOperand(1);
2178 SDValue False = N->getOperand(2);
2180 if (VT == MVT::f32 ||
2182 Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS)) {
2183 return CombineFMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
2186 // TODO: Implement min / max Evergreen instructions.
2187 if (VT == MVT::i32 &&
2188 Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
2189 return CombineIMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
2195 case AMDGPUISD::BFE_I32:
2196 case AMDGPUISD::BFE_U32: {
2197 assert(!N->getValueType(0).isVector() &&
2198 "Vector handling of BFE not implemented");
2199 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2203 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2205 return DAG.getConstant(0, MVT::i32);
2207 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2211 SDValue BitsFrom = N->getOperand(0);
2212 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2214 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2216 if (OffsetVal == 0) {
2217 // This is already sign / zero extended, so try to fold away extra BFEs.
2218 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2220 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2221 if (OpSignBits >= SignBits)
2224 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2226 // This is a sign_extend_inreg. Replace it to take advantage of existing
2227 // DAG Combines. If not eliminated, we will match back to BFE during
2230 // TODO: The sext_inreg of extended types ends, although we can could
2231 // handle them in a single BFE.
2232 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2233 DAG.getValueType(SmallVT));
2236 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2239 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2241 return constantFoldBFE<int32_t>(DAG,
2242 CVal->getSExtValue(),
2247 return constantFoldBFE<uint32_t>(DAG,
2248 CVal->getZExtValue(),
2253 if ((OffsetVal + WidthVal) >= 32) {
2254 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
2255 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2256 BitsFrom, ShiftVal);
2259 if (BitsFrom.hasOneUse()) {
2260 APInt Demanded = APInt::getBitsSet(32,
2262 OffsetVal + WidthVal);
2264 APInt KnownZero, KnownOne;
2265 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2266 !DCI.isBeforeLegalizeOps());
2267 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2268 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2269 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2270 KnownZero, KnownOne, TLO)) {
2271 DCI.CommitTargetLoweringOpt(TLO);
2279 return performStoreCombine(N, DCI);
2284 //===----------------------------------------------------------------------===//
2286 //===----------------------------------------------------------------------===//
2288 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2291 const SmallVectorImpl<ISD::InputArg> &Ins,
2292 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2294 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2295 if (Ins[i].ArgVT == Ins[i].VT) {
2296 OrigIns.push_back(Ins[i]);
2301 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2302 // Vector has been split into scalars.
2303 VT = Ins[i].ArgVT.getVectorElementType();
2304 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2305 Ins[i].ArgVT.getVectorElementType() !=
2306 Ins[i].VT.getVectorElementType()) {
2307 // Vector elements have been promoted
2310 // Vector has been spilt into smaller vectors.
2314 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2315 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2316 OrigIns.push_back(Arg);
2320 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2321 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2322 return CFP->isExactlyValue(1.0);
2324 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2325 return C->isAllOnesValue();
2330 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2331 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2332 return CFP->getValueAPF().isZero();
2334 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2335 return C->isNullValue();
2340 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2341 const TargetRegisterClass *RC,
2342 unsigned Reg, EVT VT) const {
2343 MachineFunction &MF = DAG.getMachineFunction();
2344 MachineRegisterInfo &MRI = MF.getRegInfo();
2345 unsigned VirtualRegister;
2346 if (!MRI.isLiveIn(Reg)) {
2347 VirtualRegister = MRI.createVirtualRegister(RC);
2348 MRI.addLiveIn(Reg, VirtualRegister);
2350 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2352 return DAG.getRegister(VirtualRegister, VT);
2355 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2357 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2359 default: return nullptr;
2361 NODE_NAME_CASE(CALL);
2362 NODE_NAME_CASE(UMUL);
2363 NODE_NAME_CASE(RET_FLAG);
2364 NODE_NAME_CASE(BRANCH_COND);
2367 NODE_NAME_CASE(DWORDADDR)
2368 NODE_NAME_CASE(FRACT)
2369 NODE_NAME_CASE(CLAMP)
2371 NODE_NAME_CASE(FMAX_LEGACY)
2372 NODE_NAME_CASE(SMAX)
2373 NODE_NAME_CASE(UMAX)
2374 NODE_NAME_CASE(FMIN_LEGACY)
2375 NODE_NAME_CASE(SMIN)
2376 NODE_NAME_CASE(UMIN)
2377 NODE_NAME_CASE(FMAX3)
2378 NODE_NAME_CASE(SMAX3)
2379 NODE_NAME_CASE(UMAX3)
2380 NODE_NAME_CASE(FMIN3)
2381 NODE_NAME_CASE(SMIN3)
2382 NODE_NAME_CASE(UMIN3)
2383 NODE_NAME_CASE(URECIP)
2384 NODE_NAME_CASE(DIV_SCALE)
2385 NODE_NAME_CASE(DIV_FMAS)
2386 NODE_NAME_CASE(DIV_FIXUP)
2387 NODE_NAME_CASE(TRIG_PREOP)
2390 NODE_NAME_CASE(RSQ_LEGACY)
2391 NODE_NAME_CASE(RSQ_CLAMPED)
2392 NODE_NAME_CASE(LDEXP)
2393 NODE_NAME_CASE(DOT4)
2394 NODE_NAME_CASE(BFE_U32)
2395 NODE_NAME_CASE(BFE_I32)
2398 NODE_NAME_CASE(BREV)
2399 NODE_NAME_CASE(MUL_U24)
2400 NODE_NAME_CASE(MUL_I24)
2401 NODE_NAME_CASE(MAD_U24)
2402 NODE_NAME_CASE(MAD_I24)
2403 NODE_NAME_CASE(EXPORT)
2404 NODE_NAME_CASE(CONST_ADDRESS)
2405 NODE_NAME_CASE(REGISTER_LOAD)
2406 NODE_NAME_CASE(REGISTER_STORE)
2407 NODE_NAME_CASE(LOAD_CONSTANT)
2408 NODE_NAME_CASE(LOAD_INPUT)
2409 NODE_NAME_CASE(SAMPLE)
2410 NODE_NAME_CASE(SAMPLEB)
2411 NODE_NAME_CASE(SAMPLED)
2412 NODE_NAME_CASE(SAMPLEL)
2413 NODE_NAME_CASE(CVT_F32_UBYTE0)
2414 NODE_NAME_CASE(CVT_F32_UBYTE1)
2415 NODE_NAME_CASE(CVT_F32_UBYTE2)
2416 NODE_NAME_CASE(CVT_F32_UBYTE3)
2417 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2418 NODE_NAME_CASE(CONST_DATA_PTR)
2419 NODE_NAME_CASE(STORE_MSKOR)
2420 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2424 static void computeKnownBitsForMinMax(const SDValue Op0,
2428 const SelectionDAG &DAG,
2430 APInt Op0Zero, Op0One;
2431 APInt Op1Zero, Op1One;
2432 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2433 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2435 KnownZero = Op0Zero & Op1Zero;
2436 KnownOne = Op0One & Op1One;
2439 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2443 const SelectionDAG &DAG,
2444 unsigned Depth) const {
2446 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2450 unsigned Opc = Op.getOpcode();
2455 case ISD::INTRINSIC_WO_CHAIN: {
2456 // FIXME: The intrinsic should just use the node.
2457 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2458 case AMDGPUIntrinsic::AMDGPU_imax:
2459 case AMDGPUIntrinsic::AMDGPU_umax:
2460 case AMDGPUIntrinsic::AMDGPU_imin:
2461 case AMDGPUIntrinsic::AMDGPU_umin:
2462 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2463 KnownZero, KnownOne, DAG, Depth);
2471 case AMDGPUISD::SMAX:
2472 case AMDGPUISD::UMAX:
2473 case AMDGPUISD::SMIN:
2474 case AMDGPUISD::UMIN:
2475 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2476 KnownZero, KnownOne, DAG, Depth);
2479 case AMDGPUISD::BFE_I32:
2480 case AMDGPUISD::BFE_U32: {
2481 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2485 unsigned BitWidth = 32;
2486 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2488 if (Opc == AMDGPUISD::BFE_U32)
2489 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2496 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2498 const SelectionDAG &DAG,
2499 unsigned Depth) const {
2500 switch (Op.getOpcode()) {
2501 case AMDGPUISD::BFE_I32: {
2502 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2506 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2507 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2508 if (!Offset || !Offset->isNullValue())
2511 // TODO: Could probably figure something out with non-0 offsets.
2512 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2513 return std::max(SignBits, Op0SignBits);
2516 case AMDGPUISD::BFE_U32: {
2517 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2518 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;