1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
108 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
110 setOperationAction(ISD::Constant, MVT::i32, Legal);
111 setOperationAction(ISD::Constant, MVT::i64, Legal);
112 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
113 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
115 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
116 setOperationAction(ISD::BRIND, MVT::Other, Expand);
118 // We need to custom lower some of the intrinsics
119 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
121 // Library functions. These default to Expand, but we have instructions
123 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
124 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
125 setOperationAction(ISD::FPOW, MVT::f32, Legal);
126 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
127 setOperationAction(ISD::FABS, MVT::f32, Legal);
128 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
129 setOperationAction(ISD::FRINT, MVT::f32, Legal);
130 setOperationAction(ISD::FROUND, MVT::f32, Legal);
131 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
133 setOperationAction(ISD::FREM, MVT::f32, Custom);
134 setOperationAction(ISD::FREM, MVT::f64, Custom);
136 // Lower floating point store/load to integer store/load to reduce the number
137 // of patterns in tablegen.
138 setOperationAction(ISD::STORE, MVT::f32, Promote);
139 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
141 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
142 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
144 setOperationAction(ISD::STORE, MVT::i64, Promote);
145 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
147 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
148 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
150 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
153 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
154 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
156 setOperationAction(ISD::STORE, MVT::f64, Promote);
157 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
159 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
160 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
162 // Custom lowering of vector stores is required for local address space
164 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
165 // XXX: Native v2i32 local address space stores are possible, but not
166 // currently implemented.
167 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
169 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
170 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
171 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
173 // XXX: This can be change to Custom, once ExpandVectorStores can
174 // handle 64-bit stores.
175 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
177 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
178 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
179 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
180 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
181 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
184 setOperationAction(ISD::LOAD, MVT::f32, Promote);
185 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
187 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
190 setOperationAction(ISD::LOAD, MVT::i64, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
193 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
196 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
199 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
200 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
202 setOperationAction(ISD::LOAD, MVT::f64, Promote);
203 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
205 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
206 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
210 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
211 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
216 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
217 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
219 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
220 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
221 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
222 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
223 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
224 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
225 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
226 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
227 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
228 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
229 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
230 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
232 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
234 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
235 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
236 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
237 setOperationAction(ISD::FRINT, MVT::f64, Custom);
238 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
241 if (!Subtarget->hasBFI()) {
242 // fcopysign can be done in a single instruction with BFI.
243 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
244 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
247 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
249 setLoadExtAction(ISD::EXTLOAD, MVT::f16, Expand);
250 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
251 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
253 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
254 for (MVT VT : ScalarIntVTs) {
255 setOperationAction(ISD::SREM, VT, Expand);
256 setOperationAction(ISD::SDIV, VT, Expand);
258 // GPU does not have divrem function for signed or unsigned.
259 setOperationAction(ISD::SDIVREM, VT, Custom);
260 setOperationAction(ISD::UDIVREM, VT, Custom);
262 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
263 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
264 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
266 setOperationAction(ISD::BSWAP, VT, Expand);
267 setOperationAction(ISD::CTTZ, VT, Expand);
268 setOperationAction(ISD::CTLZ, VT, Expand);
271 if (!Subtarget->hasBCNT(32))
272 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
274 if (!Subtarget->hasBCNT(64))
275 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
277 // The hardware supports 32-bit ROTR, but not ROTL.
278 setOperationAction(ISD::ROTL, MVT::i32, Expand);
279 setOperationAction(ISD::ROTL, MVT::i64, Expand);
280 setOperationAction(ISD::ROTR, MVT::i64, Expand);
282 setOperationAction(ISD::MUL, MVT::i64, Expand);
283 setOperationAction(ISD::MULHU, MVT::i64, Expand);
284 setOperationAction(ISD::MULHS, MVT::i64, Expand);
285 setOperationAction(ISD::UDIV, MVT::i32, Expand);
286 setOperationAction(ISD::UREM, MVT::i32, Expand);
287 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
288 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
289 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
290 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
291 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
293 if (!Subtarget->hasFFBH())
294 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
296 if (!Subtarget->hasFFBL())
297 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
299 static const MVT::SimpleValueType VectorIntTypes[] = {
300 MVT::v2i32, MVT::v4i32
303 for (MVT VT : VectorIntTypes) {
304 // Expand the following operations for the current type by default.
305 setOperationAction(ISD::ADD, VT, Expand);
306 setOperationAction(ISD::AND, VT, Expand);
307 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
308 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
309 setOperationAction(ISD::MUL, VT, Expand);
310 setOperationAction(ISD::OR, VT, Expand);
311 setOperationAction(ISD::SHL, VT, Expand);
312 setOperationAction(ISD::SRA, VT, Expand);
313 setOperationAction(ISD::SRL, VT, Expand);
314 setOperationAction(ISD::ROTL, VT, Expand);
315 setOperationAction(ISD::ROTR, VT, Expand);
316 setOperationAction(ISD::SUB, VT, Expand);
317 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
318 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
319 setOperationAction(ISD::SDIV, VT, Expand);
320 setOperationAction(ISD::UDIV, VT, Expand);
321 setOperationAction(ISD::SREM, VT, Expand);
322 setOperationAction(ISD::UREM, VT, Expand);
323 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
324 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
325 setOperationAction(ISD::SDIVREM, VT, Custom);
326 setOperationAction(ISD::UDIVREM, VT, Custom);
327 setOperationAction(ISD::ADDC, VT, Expand);
328 setOperationAction(ISD::SUBC, VT, Expand);
329 setOperationAction(ISD::ADDE, VT, Expand);
330 setOperationAction(ISD::SUBE, VT, Expand);
331 setOperationAction(ISD::SELECT, VT, Expand);
332 setOperationAction(ISD::VSELECT, VT, Expand);
333 setOperationAction(ISD::SELECT_CC, VT, Expand);
334 setOperationAction(ISD::XOR, VT, Expand);
335 setOperationAction(ISD::BSWAP, VT, Expand);
336 setOperationAction(ISD::CTPOP, VT, Expand);
337 setOperationAction(ISD::CTTZ, VT, Expand);
338 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
339 setOperationAction(ISD::CTLZ, VT, Expand);
340 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
341 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
344 static const MVT::SimpleValueType FloatVectorTypes[] = {
345 MVT::v2f32, MVT::v4f32
348 for (MVT VT : FloatVectorTypes) {
349 setOperationAction(ISD::FABS, VT, Expand);
350 setOperationAction(ISD::FMINNUM, VT, Expand);
351 setOperationAction(ISD::FMAXNUM, VT, Expand);
352 setOperationAction(ISD::FADD, VT, Expand);
353 setOperationAction(ISD::FCEIL, VT, Expand);
354 setOperationAction(ISD::FCOS, VT, Expand);
355 setOperationAction(ISD::FDIV, VT, Expand);
356 setOperationAction(ISD::FEXP2, VT, Expand);
357 setOperationAction(ISD::FLOG2, VT, Expand);
358 setOperationAction(ISD::FREM, VT, Expand);
359 setOperationAction(ISD::FPOW, VT, Expand);
360 setOperationAction(ISD::FFLOOR, VT, Expand);
361 setOperationAction(ISD::FTRUNC, VT, Expand);
362 setOperationAction(ISD::FMUL, VT, Expand);
363 setOperationAction(ISD::FMA, VT, Expand);
364 setOperationAction(ISD::FRINT, VT, Expand);
365 setOperationAction(ISD::FNEARBYINT, VT, Expand);
366 setOperationAction(ISD::FSQRT, VT, Expand);
367 setOperationAction(ISD::FSIN, VT, Expand);
368 setOperationAction(ISD::FSUB, VT, Expand);
369 setOperationAction(ISD::FNEG, VT, Expand);
370 setOperationAction(ISD::SELECT, VT, Expand);
371 setOperationAction(ISD::VSELECT, VT, Expand);
372 setOperationAction(ISD::SELECT_CC, VT, Expand);
373 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
374 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
377 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
378 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
380 setTargetDAGCombine(ISD::MUL);
381 setTargetDAGCombine(ISD::SELECT);
382 setTargetDAGCombine(ISD::SELECT_CC);
383 setTargetDAGCombine(ISD::STORE);
385 setSchedulingPreference(Sched::RegPressure);
386 setJumpIsExpensive(true);
388 // SI at least has hardware support for floating point exceptions, but no way
389 // of using or handling them is implemented. They are also optional in OpenCL
391 setHasFloatingPointExceptions(false);
393 setSelectIsExpensive(false);
394 PredictableSelectIsExpensive = false;
396 // There are no integer divide instructions, and these expand to a pretty
397 // large sequence of instructions.
398 setIntDivIsCheap(false);
399 setPow2SDivIsCheap(false);
401 // FIXME: Need to really handle these.
402 MaxStoresPerMemcpy = 4096;
403 MaxStoresPerMemmove = 4096;
404 MaxStoresPerMemset = 4096;
407 //===----------------------------------------------------------------------===//
408 // Target Information
409 //===----------------------------------------------------------------------===//
411 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
415 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
419 // The backend supports 32 and 64 bit floating point immediates.
420 // FIXME: Why are we reporting vectors of FP immediates as legal?
421 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
422 EVT ScalarVT = VT.getScalarType();
423 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
426 // We don't want to shrink f64 / f32 constants.
427 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
428 EVT ScalarVT = VT.getScalarType();
429 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
432 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
434 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
437 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
438 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
440 return ((LScalarSize <= CastScalarSize) ||
441 (CastScalarSize >= 32) ||
445 //===---------------------------------------------------------------------===//
447 //===---------------------------------------------------------------------===//
449 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
450 assert(VT.isFloatingPoint());
451 return VT == MVT::f32 || VT == MVT::f64;
454 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
455 assert(VT.isFloatingPoint());
456 return VT == MVT::f32 || VT == MVT::f64;
459 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
460 // Truncate is just accessing a subregister.
461 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
464 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
465 // Truncate is just accessing a subregister.
466 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
467 (Dest->getPrimitiveSizeInBits() % 32 == 0);
470 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
471 const DataLayout *DL = getDataLayout();
472 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
473 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
475 return SrcSize == 32 && DestSize == 64;
478 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
479 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
480 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
481 // this will enable reducing 64-bit operations the 32-bit, which is always
483 return Src == MVT::i32 && Dest == MVT::i64;
486 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
487 return isZExtFree(Val.getValueType(), VT2);
490 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
491 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
492 // limited number of native 64-bit operations. Shrinking an operation to fit
493 // in a single 32-bit register should always be helpful. As currently used,
494 // this is much less general than the name suggests, and is only used in
495 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
496 // not profitable, and may actually be harmful.
497 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
500 //===---------------------------------------------------------------------===//
501 // TargetLowering Callbacks
502 //===---------------------------------------------------------------------===//
504 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
505 const SmallVectorImpl<ISD::InputArg> &Ins) const {
507 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
510 SDValue AMDGPUTargetLowering::LowerReturn(
512 CallingConv::ID CallConv,
514 const SmallVectorImpl<ISD::OutputArg> &Outs,
515 const SmallVectorImpl<SDValue> &OutVals,
516 SDLoc DL, SelectionDAG &DAG) const {
517 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
520 //===---------------------------------------------------------------------===//
521 // Target specific lowering
522 //===---------------------------------------------------------------------===//
524 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
525 SmallVectorImpl<SDValue> &InVals) const {
526 SDValue Callee = CLI.Callee;
527 SelectionDAG &DAG = CLI.DAG;
529 const Function &Fn = *DAG.getMachineFunction().getFunction();
531 StringRef FuncName("<unknown>");
533 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
534 FuncName = G->getSymbol();
535 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
536 FuncName = G->getGlobal()->getName();
538 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
539 DAG.getContext()->diagnose(NoCalls);
543 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
544 SelectionDAG &DAG) const {
545 switch (Op.getOpcode()) {
547 Op.getNode()->dump();
548 llvm_unreachable("Custom lowering code for this"
549 "instruction is not implemented yet!");
551 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
552 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
553 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
554 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
555 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
556 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
557 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
558 case ISD::FREM: return LowerFREM(Op, DAG);
559 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
560 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
561 case ISD::FRINT: return LowerFRINT(Op, DAG);
562 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
563 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
564 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
565 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
566 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
567 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
572 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
573 SmallVectorImpl<SDValue> &Results,
574 SelectionDAG &DAG) const {
575 switch (N->getOpcode()) {
576 case ISD::SIGN_EXTEND_INREG:
577 // Different parts of legalization seem to interpret which type of
578 // sign_extend_inreg is the one to check for custom lowering. The extended
579 // from type is what really matters, but some places check for custom
580 // lowering of the result type. This results in trying to use
581 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
582 // nothing here and let the illegal result integer be handled normally.
585 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
589 Results.push_back(SDValue(Node, 0));
590 Results.push_back(SDValue(Node, 1));
591 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
593 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
597 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
598 if (Lowered.getNode())
599 Results.push_back(Lowered);
607 // FIXME: This implements accesses to initialized globals in the constant
608 // address space by copying them to private and accessing that. It does not
609 // properly handle illegal types or vectors. The private vector loads are not
610 // scalarized, and the illegal scalars hit an assertion. This technique will not
611 // work well with large initializers, and this should eventually be
612 // removed. Initialized globals should be placed into a data section that the
613 // runtime will load into a buffer before the kernel is executed. Uses of the
614 // global need to be replaced with a pointer loaded from an implicit kernel
615 // argument into this buffer holding the copy of the data, which will remove the
616 // need for any of this.
617 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
618 const GlobalValue *GV,
619 const SDValue &InitPtr,
621 SelectionDAG &DAG) const {
622 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
624 Type *InitTy = Init->getType();
626 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
627 EVT VT = EVT::getEVT(InitTy);
628 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
629 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
630 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
631 TD->getPrefTypeAlignment(InitTy));
634 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
635 EVT VT = EVT::getEVT(CFP->getType());
636 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
637 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
638 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
639 TD->getPrefTypeAlignment(CFP->getType()));
642 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
643 const StructLayout *SL = TD->getStructLayout(ST);
645 EVT PtrVT = InitPtr.getValueType();
646 SmallVector<SDValue, 8> Chains;
648 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
649 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
650 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
652 Constant *Elt = Init->getAggregateElement(I);
653 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
656 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
659 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
660 EVT PtrVT = InitPtr.getValueType();
662 unsigned NumElements;
663 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
664 NumElements = AT->getNumElements();
665 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
666 NumElements = VT->getNumElements();
668 llvm_unreachable("Unexpected type");
670 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
671 SmallVector<SDValue, 8> Chains;
672 for (unsigned i = 0; i < NumElements; ++i) {
673 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
674 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
676 Constant *Elt = Init->getAggregateElement(i);
677 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
680 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
683 if (isa<UndefValue>(Init)) {
684 EVT VT = EVT::getEVT(InitTy);
685 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
686 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
687 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
688 TD->getPrefTypeAlignment(InitTy));
692 llvm_unreachable("Unhandled constant initializer");
695 static bool hasDefinedInitializer(const GlobalValue *GV) {
696 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
697 if (!GVar || !GVar->hasInitializer())
700 if (isa<UndefValue>(GVar->getInitializer()))
706 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
708 SelectionDAG &DAG) const {
710 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
711 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
712 const GlobalValue *GV = G->getGlobal();
714 switch (G->getAddressSpace()) {
715 case AMDGPUAS::LOCAL_ADDRESS: {
716 // XXX: What does the value of G->getOffset() mean?
717 assert(G->getOffset() == 0 &&
718 "Do not know what to do with an non-zero offset");
720 // TODO: We could emit code to handle the initialization somewhere.
721 if (hasDefinedInitializer(GV))
725 if (MFI->LocalMemoryObjects.count(GV) == 0) {
726 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
727 Offset = MFI->LDSSize;
728 MFI->LocalMemoryObjects[GV] = Offset;
729 // XXX: Account for alignment?
730 MFI->LDSSize += Size;
732 Offset = MFI->LocalMemoryObjects[GV];
735 return DAG.getConstant(Offset, getPointerTy(AMDGPUAS::LOCAL_ADDRESS));
737 case AMDGPUAS::CONSTANT_ADDRESS: {
738 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
739 Type *EltType = GV->getType()->getElementType();
740 unsigned Size = TD->getTypeAllocSize(EltType);
741 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
743 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
744 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
746 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
747 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
749 const GlobalVariable *Var = cast<GlobalVariable>(GV);
750 if (!Var->hasInitializer()) {
751 // This has no use, but bugpoint will hit it.
752 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
755 const Constant *Init = Var->getInitializer();
756 SmallVector<SDNode*, 8> WorkList;
758 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
759 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
760 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
762 WorkList.push_back(*I);
764 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
765 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
766 E = WorkList.end(); I != E; ++I) {
767 SmallVector<SDValue, 8> Ops;
768 Ops.push_back(Chain);
769 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
770 Ops.push_back((*I)->getOperand(i));
772 DAG.UpdateNodeOperands(*I, Ops);
774 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
778 const Function &Fn = *DAG.getMachineFunction().getFunction();
779 DiagnosticInfoUnsupported BadInit(Fn,
780 "initializer for address space");
781 DAG.getContext()->diagnose(BadInit);
785 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
786 SelectionDAG &DAG) const {
787 SmallVector<SDValue, 8> Args;
788 SDValue A = Op.getOperand(0);
789 SDValue B = Op.getOperand(1);
791 DAG.ExtractVectorElements(A, Args);
792 DAG.ExtractVectorElements(B, Args);
794 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
797 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
798 SelectionDAG &DAG) const {
800 SmallVector<SDValue, 8> Args;
801 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
802 EVT VT = Op.getValueType();
803 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
804 VT.getVectorNumElements());
806 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
809 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
810 SelectionDAG &DAG) const {
812 MachineFunction &MF = DAG.getMachineFunction();
813 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
814 getTargetMachine().getSubtargetImpl()->getFrameLowering());
816 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
818 unsigned FrameIndex = FIN->getIndex();
819 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
820 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
824 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
825 SelectionDAG &DAG) const {
826 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
828 EVT VT = Op.getValueType();
830 switch (IntrinsicID) {
832 case AMDGPUIntrinsic::AMDGPU_abs:
833 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
834 return LowerIntrinsicIABS(Op, DAG);
835 case AMDGPUIntrinsic::AMDGPU_lrp:
836 return LowerIntrinsicLRP(Op, DAG);
837 case AMDGPUIntrinsic::AMDGPU_fract:
838 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
839 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
841 case AMDGPUIntrinsic::AMDGPU_clamp:
842 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
843 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
844 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
846 case Intrinsic::AMDGPU_div_scale: {
847 // 3rd parameter required to be a constant.
848 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
850 return DAG.getUNDEF(VT);
852 // Translate to the operands expected by the machine instruction. The
853 // first parameter must be the same as the first instruction.
854 SDValue Numerator = Op.getOperand(1);
855 SDValue Denominator = Op.getOperand(2);
857 // Note this order is opposite of the machine instruction's operations,
858 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
859 // intrinsic has the numerator as the first operand to match a normal
860 // division operation.
862 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
864 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
865 Denominator, Numerator);
868 case Intrinsic::AMDGPU_div_fmas:
869 // FIXME: Dropping bool parameter. Work is needed to support the implicit
871 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
872 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
874 case Intrinsic::AMDGPU_div_fixup:
875 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
876 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
878 case Intrinsic::AMDGPU_trig_preop:
879 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
880 Op.getOperand(1), Op.getOperand(2));
882 case Intrinsic::AMDGPU_rcp:
883 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
885 case Intrinsic::AMDGPU_rsq:
886 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
888 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
889 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
891 case Intrinsic::AMDGPU_rsq_clamped:
892 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
894 case Intrinsic::AMDGPU_ldexp:
895 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
898 case AMDGPUIntrinsic::AMDGPU_imax:
899 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
901 case AMDGPUIntrinsic::AMDGPU_umax:
902 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
904 case AMDGPUIntrinsic::AMDGPU_imin:
905 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
907 case AMDGPUIntrinsic::AMDGPU_umin:
908 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
911 case AMDGPUIntrinsic::AMDGPU_umul24:
912 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
913 Op.getOperand(1), Op.getOperand(2));
915 case AMDGPUIntrinsic::AMDGPU_imul24:
916 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
917 Op.getOperand(1), Op.getOperand(2));
919 case AMDGPUIntrinsic::AMDGPU_umad24:
920 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
921 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
923 case AMDGPUIntrinsic::AMDGPU_imad24:
924 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
925 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
927 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
928 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
930 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
931 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
933 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
934 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
936 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
937 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
939 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
940 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
945 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
946 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
951 case AMDGPUIntrinsic::AMDGPU_bfi:
952 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
957 case AMDGPUIntrinsic::AMDGPU_bfm:
958 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
962 case AMDGPUIntrinsic::AMDGPU_brev:
963 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
965 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
966 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
968 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
969 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
970 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
971 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
975 ///IABS(a) = SMAX(sub(0, a), a)
976 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
977 SelectionDAG &DAG) const {
979 EVT VT = Op.getValueType();
980 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
983 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
986 /// Linear Interpolation
987 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
988 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
989 SelectionDAG &DAG) const {
991 EVT VT = Op.getValueType();
992 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
993 DAG.getConstantFP(1.0f, MVT::f32),
995 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
997 return DAG.getNode(ISD::FADD, DL, VT,
998 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1002 /// \brief Generate Min/Max node
1003 SDValue AMDGPUTargetLowering::CombineMinMax(SDLoc DL,
1010 SelectionDAG &DAG) const {
1011 if (VT != MVT::f32 &&
1013 Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS))
1016 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1019 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1028 case ISD::SETFALSE2:
1041 = (LHS == True) ? AMDGPUISD::FMIN_LEGACY : AMDGPUISD::FMAX_LEGACY;
1042 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1051 = (LHS == True) ? AMDGPUISD::FMAX_LEGACY : AMDGPUISD::FMIN_LEGACY;
1052 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1054 case ISD::SETCC_INVALID:
1055 llvm_unreachable("Invalid setcc condcode!");
1060 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1061 SelectionDAG &DAG) const {
1062 LoadSDNode *Load = cast<LoadSDNode>(Op);
1063 EVT MemVT = Load->getMemoryVT();
1064 EVT MemEltVT = MemVT.getVectorElementType();
1066 EVT LoadVT = Op.getValueType();
1067 EVT EltVT = LoadVT.getVectorElementType();
1068 EVT PtrVT = Load->getBasePtr().getValueType();
1070 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1071 SmallVector<SDValue, 8> Loads;
1072 SmallVector<SDValue, 8> Chains;
1075 unsigned MemEltSize = MemEltVT.getStoreSize();
1076 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1078 for (unsigned i = 0; i < NumElts; ++i) {
1079 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1080 DAG.getConstant(i * MemEltSize, PtrVT));
1083 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1084 Load->getChain(), Ptr,
1085 SrcValue.getWithOffset(i * MemEltSize),
1086 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1087 Load->isInvariant(), Load->getAlignment());
1088 Loads.push_back(NewLoad.getValue(0));
1089 Chains.push_back(NewLoad.getValue(1));
1093 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1094 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1097 return DAG.getMergeValues(Ops, SL);
1100 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1101 SelectionDAG &DAG) const {
1102 EVT VT = Op.getValueType();
1104 // If this is a 2 element vector, we really want to scalarize and not create
1105 // weird 1 element vectors.
1106 if (VT.getVectorNumElements() == 2)
1107 return ScalarizeVectorLoad(Op, DAG);
1109 LoadSDNode *Load = cast<LoadSDNode>(Op);
1110 SDValue BasePtr = Load->getBasePtr();
1111 EVT PtrVT = BasePtr.getValueType();
1112 EVT MemVT = Load->getMemoryVT();
1114 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1117 EVT LoMemVT, HiMemVT;
1120 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1121 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1122 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1124 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1125 Load->getChain(), BasePtr,
1127 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1128 Load->isInvariant(), Load->getAlignment());
1130 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1131 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1134 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1135 Load->getChain(), HiPtr,
1136 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1137 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1138 Load->isInvariant(), Load->getAlignment());
1141 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1142 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1143 LoLoad.getValue(1), HiLoad.getValue(1))
1146 return DAG.getMergeValues(Ops, SL);
1149 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1150 SelectionDAG &DAG) const {
1151 StoreSDNode *Store = cast<StoreSDNode>(Op);
1152 EVT MemVT = Store->getMemoryVT();
1153 unsigned MemBits = MemVT.getSizeInBits();
1155 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1156 // truncating store into an i32 store.
1157 // XXX: We could also handle optimize other vector bitwidths.
1158 if (!MemVT.isVector() || MemBits > 32) {
1163 SDValue Value = Store->getValue();
1164 EVT VT = Value.getValueType();
1165 EVT ElemVT = VT.getVectorElementType();
1166 SDValue Ptr = Store->getBasePtr();
1167 EVT MemEltVT = MemVT.getVectorElementType();
1168 unsigned MemEltBits = MemEltVT.getSizeInBits();
1169 unsigned MemNumElements = MemVT.getVectorNumElements();
1170 unsigned PackedSize = MemVT.getStoreSizeInBits();
1171 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1173 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1175 SDValue PackedValue;
1176 for (unsigned i = 0; i < MemNumElements; ++i) {
1177 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1178 DAG.getConstant(i, MVT::i32));
1179 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1180 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1182 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1183 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1188 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1192 if (PackedSize < 32) {
1193 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1194 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1195 Store->getMemOperand()->getPointerInfo(),
1197 Store->isNonTemporal(), Store->isVolatile(),
1198 Store->getAlignment());
1201 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1202 Store->getMemOperand()->getPointerInfo(),
1203 Store->isVolatile(), Store->isNonTemporal(),
1204 Store->getAlignment());
1207 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1208 SelectionDAG &DAG) const {
1209 StoreSDNode *Store = cast<StoreSDNode>(Op);
1210 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1211 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1212 EVT PtrVT = Store->getBasePtr().getValueType();
1213 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1216 SmallVector<SDValue, 8> Chains;
1218 unsigned EltSize = MemEltVT.getStoreSize();
1219 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1221 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1222 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1224 DAG.getConstant(i, MVT::i32));
1226 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), PtrVT);
1227 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1229 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1230 SrcValue.getWithOffset(i * EltSize),
1231 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1232 Store->getAlignment());
1233 Chains.push_back(NewStore);
1236 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1239 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1240 SelectionDAG &DAG) const {
1241 StoreSDNode *Store = cast<StoreSDNode>(Op);
1242 SDValue Val = Store->getValue();
1243 EVT VT = Val.getValueType();
1245 // If this is a 2 element vector, we really want to scalarize and not create
1246 // weird 1 element vectors.
1247 if (VT.getVectorNumElements() == 2)
1248 return ScalarizeVectorStore(Op, DAG);
1250 EVT MemVT = Store->getMemoryVT();
1251 SDValue Chain = Store->getChain();
1252 SDValue BasePtr = Store->getBasePtr();
1256 EVT LoMemVT, HiMemVT;
1259 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1260 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1261 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1263 EVT PtrVT = BasePtr.getValueType();
1264 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1265 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1267 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1269 = DAG.getTruncStore(Chain, SL, Lo,
1273 Store->isNonTemporal(),
1274 Store->isVolatile(),
1275 Store->getAlignment());
1277 = DAG.getTruncStore(Chain, SL, Hi,
1279 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1281 Store->isNonTemporal(),
1282 Store->isVolatile(),
1283 Store->getAlignment());
1285 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1289 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1291 LoadSDNode *Load = cast<LoadSDNode>(Op);
1292 ISD::LoadExtType ExtType = Load->getExtensionType();
1293 EVT VT = Op.getValueType();
1294 EVT MemVT = Load->getMemoryVT();
1296 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1297 // We can do the extload to 32-bits, and then need to separately extend to
1300 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1304 Load->getMemOperand());
1307 DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32),
1308 ExtLoad32.getValue(1)
1311 return DAG.getMergeValues(Ops, DL);
1314 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1315 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1316 // FIXME: Copied from PPC
1317 // First, load into 32 bits, then truncate to 1 bit.
1319 SDValue Chain = Load->getChain();
1320 SDValue BasePtr = Load->getBasePtr();
1321 MachineMemOperand *MMO = Load->getMemOperand();
1323 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1324 BasePtr, MVT::i8, MMO);
1327 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1331 return DAG.getMergeValues(Ops, DL);
1334 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1335 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1336 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1340 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1341 DAG.getConstant(2, MVT::i32));
1342 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1343 Load->getChain(), Ptr,
1344 DAG.getTargetConstant(0, MVT::i32),
1346 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1348 DAG.getConstant(0x3, MVT::i32));
1349 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1350 DAG.getConstant(3, MVT::i32));
1352 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1354 EVT MemEltVT = MemVT.getScalarType();
1355 if (ExtType == ISD::SEXTLOAD) {
1356 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1359 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1363 return DAG.getMergeValues(Ops, DL);
1367 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1371 return DAG.getMergeValues(Ops, DL);
1374 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1376 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1377 if (Result.getNode()) {
1381 StoreSDNode *Store = cast<StoreSDNode>(Op);
1382 SDValue Chain = Store->getChain();
1383 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1384 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1385 Store->getValue().getValueType().isVector()) {
1386 return ScalarizeVectorStore(Op, DAG);
1389 EVT MemVT = Store->getMemoryVT();
1390 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1391 MemVT.bitsLT(MVT::i32)) {
1393 if (Store->getMemoryVT() == MVT::i8) {
1395 } else if (Store->getMemoryVT() == MVT::i16) {
1398 SDValue BasePtr = Store->getBasePtr();
1399 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1400 DAG.getConstant(2, MVT::i32));
1401 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1402 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1404 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1405 DAG.getConstant(0x3, MVT::i32));
1407 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1408 DAG.getConstant(3, MVT::i32));
1410 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1413 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1415 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1416 MaskedValue, ShiftAmt);
1418 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1420 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1421 DAG.getConstant(0xffffffff, MVT::i32));
1422 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1424 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1425 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1426 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1431 // This is a shortcut for integer division because we have fast i32<->f32
1432 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1433 // float is enough to accurately represent up to a 24-bit integer.
1434 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1436 EVT VT = Op.getValueType();
1437 SDValue LHS = Op.getOperand(0);
1438 SDValue RHS = Op.getOperand(1);
1439 MVT IntVT = MVT::i32;
1440 MVT FltVT = MVT::f32;
1442 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1443 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1445 if (VT.isVector()) {
1446 unsigned NElts = VT.getVectorNumElements();
1447 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1448 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1451 unsigned BitSize = VT.getScalarType().getSizeInBits();
1453 SDValue jq = DAG.getConstant(1, IntVT);
1456 // char|short jq = ia ^ ib;
1457 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1459 // jq = jq >> (bitsize - 2)
1460 jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
1463 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));
1466 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1469 // int ia = (int)LHS;
1471 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1473 // int ib, (int)RHS;
1475 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1477 // float fa = (float)ia;
1478 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1480 // float fb = (float)ib;
1481 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1483 // float fq = native_divide(fa, fb);
1484 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1485 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1488 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1490 // float fqneg = -fq;
1491 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1493 // float fr = mad(fqneg, fb, fa);
1494 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1495 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1497 // int iq = (int)fq;
1498 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1501 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1504 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1506 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), VT);
1508 // int cv = fr >= fb;
1509 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1511 // jq = (cv ? jq : 0);
1512 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
1514 // dst = trunc/extend to legal type
1515 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1518 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1520 // Rem needs compensation, it's easier to recompute it
1521 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1522 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1528 return DAG.getMergeValues(Res, DL);
1531 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1532 SelectionDAG &DAG) const {
1534 EVT VT = Op.getValueType();
1536 SDValue Num = Op.getOperand(0);
1537 SDValue Den = Op.getOperand(1);
1539 if (VT == MVT::i32) {
1540 if (DAG.MaskedValueIsZero(Op.getOperand(0), APInt(32, 0xff << 24)) &&
1541 DAG.MaskedValueIsZero(Op.getOperand(1), APInt(32, 0xff << 24))) {
1542 // TODO: We technically could do this for i64, but shouldn't that just be
1543 // handled by something generally reducing 64-bit division on 32-bit
1544 // values to 32-bit?
1545 return LowerDIVREM24(Op, DAG, false);
1549 // RCP = URECIP(Den) = 2^32 / Den + e
1550 // e is rounding error.
1551 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1553 // RCP_LO = mul(RCP, Den) */
1554 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1556 // RCP_HI = mulhu (RCP, Den) */
1557 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1559 // NEG_RCP_LO = -RCP_LO
1560 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1563 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1564 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1567 // Calculate the rounding error from the URECIP instruction
1568 // E = mulhu(ABS_RCP_LO, RCP)
1569 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1571 // RCP_A_E = RCP + E
1572 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1574 // RCP_S_E = RCP - E
1575 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1577 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1578 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1581 // Quotient = mulhu(Tmp0, Num)
1582 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1584 // Num_S_Remainder = Quotient * Den
1585 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1587 // Remainder = Num - Num_S_Remainder
1588 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1590 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1591 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1592 DAG.getConstant(-1, VT),
1593 DAG.getConstant(0, VT),
1595 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1596 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1598 DAG.getConstant(-1, VT),
1599 DAG.getConstant(0, VT),
1601 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1602 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1605 // Calculate Division result:
1607 // Quotient_A_One = Quotient + 1
1608 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1609 DAG.getConstant(1, VT));
1611 // Quotient_S_One = Quotient - 1
1612 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1613 DAG.getConstant(1, VT));
1615 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1616 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1617 Quotient, Quotient_A_One, ISD::SETEQ);
1619 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1620 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1621 Quotient_S_One, Div, ISD::SETEQ);
1623 // Calculate Rem result:
1625 // Remainder_S_Den = Remainder - Den
1626 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1628 // Remainder_A_Den = Remainder + Den
1629 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1631 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1632 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1633 Remainder, Remainder_S_Den, ISD::SETEQ);
1635 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1636 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1637 Remainder_A_Den, Rem, ISD::SETEQ);
1642 return DAG.getMergeValues(Ops, DL);
1645 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1646 SelectionDAG &DAG) const {
1648 EVT VT = Op.getValueType();
1650 SDValue LHS = Op.getOperand(0);
1651 SDValue RHS = Op.getOperand(1);
1653 if (VT == MVT::i32) {
1654 if (DAG.ComputeNumSignBits(Op.getOperand(0)) > 8 &&
1655 DAG.ComputeNumSignBits(Op.getOperand(1)) > 8) {
1656 // TODO: We technically could do this for i64, but shouldn't that just be
1657 // handled by something generally reducing 64-bit division on 32-bit
1658 // values to 32-bit?
1659 return LowerDIVREM24(Op, DAG, true);
1663 SDValue Zero = DAG.getConstant(0, VT);
1664 SDValue NegOne = DAG.getConstant(-1, VT);
1666 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1667 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1668 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1669 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1671 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1672 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1674 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1675 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1677 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1678 SDValue Rem = Div.getValue(1);
1680 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1681 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1683 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1684 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1690 return DAG.getMergeValues(Res, DL);
1693 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1694 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1696 EVT VT = Op.getValueType();
1697 SDValue X = Op.getOperand(0);
1698 SDValue Y = Op.getOperand(1);
1700 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1701 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1702 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1704 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1707 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1709 SDValue Src = Op.getOperand(0);
1711 // result = trunc(src)
1712 // if (src > 0.0 && src != result)
1715 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1717 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1718 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1720 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1722 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1723 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1724 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1726 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1727 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1730 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1732 SDValue Src = Op.getOperand(0);
1734 assert(Op.getValueType() == MVT::f64);
1736 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1737 const SDValue One = DAG.getConstant(1, MVT::i32);
1739 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1741 // Extract the upper half, since this is where we will find the sign and
1743 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1745 const unsigned FractBits = 52;
1746 const unsigned ExpBits = 11;
1748 // Extract the exponent.
1749 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1751 DAG.getConstant(FractBits - 32, MVT::i32),
1752 DAG.getConstant(ExpBits, MVT::i32));
1753 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1754 DAG.getConstant(1023, MVT::i32));
1756 // Extract the sign bit.
1757 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1758 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1760 // Extend back to to 64-bits.
1761 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1763 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1765 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1766 const SDValue FractMask
1767 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1769 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1770 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1771 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1773 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1775 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1777 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1778 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1780 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1781 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1783 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1786 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1788 SDValue Src = Op.getOperand(0);
1790 assert(Op.getValueType() == MVT::f64);
1792 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1793 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1794 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1796 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1797 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1799 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1801 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1802 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
1804 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1805 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1807 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1810 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1811 // FNEARBYINT and FRINT are the same, except in their handling of FP
1812 // exceptions. Those aren't really meaningful for us, and OpenCL only has
1813 // rint, so just treat them as equivalent.
1814 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1817 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1819 SDValue Src = Op.getOperand(0);
1821 // result = trunc(src);
1822 // if (src < 0.0 && src != result)
1825 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1827 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1828 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
1830 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1832 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
1833 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1834 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1836 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
1837 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1840 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
1841 bool Signed) const {
1843 SDValue Src = Op.getOperand(0);
1845 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1847 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
1848 DAG.getConstant(0, MVT::i32));
1849 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
1850 DAG.getConstant(1, MVT::i32));
1852 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
1855 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
1857 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
1858 DAG.getConstant(32, MVT::i32));
1860 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
1863 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1864 SelectionDAG &DAG) const {
1865 SDValue S0 = Op.getOperand(0);
1866 if (S0.getValueType() != MVT::i64)
1869 EVT DestVT = Op.getValueType();
1870 if (DestVT == MVT::f64)
1871 return LowerINT_TO_FP64(Op, DAG, false);
1873 assert(DestVT == MVT::f32);
1877 // f32 uint_to_fp i64
1878 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1879 DAG.getConstant(0, MVT::i32));
1880 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1881 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1882 DAG.getConstant(1, MVT::i32));
1883 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1884 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1885 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1886 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1889 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
1890 SelectionDAG &DAG) const {
1891 SDValue Src = Op.getOperand(0);
1892 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
1893 return LowerINT_TO_FP64(Op, DAG, true);
1898 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
1899 bool Signed) const {
1902 SDValue Src = Op.getOperand(0);
1904 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1907 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), MVT::f64);
1909 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), MVT::f64);
1911 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
1913 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
1916 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
1918 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
1919 MVT::i32, FloorMul);
1920 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
1922 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
1924 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
1927 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
1928 SelectionDAG &DAG) const {
1929 SDValue Src = Op.getOperand(0);
1931 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
1932 return LowerFP64_TO_INT(Op, DAG, true);
1937 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
1938 SelectionDAG &DAG) const {
1939 SDValue Src = Op.getOperand(0);
1941 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
1942 return LowerFP64_TO_INT(Op, DAG, false);
1947 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1948 SelectionDAG &DAG) const {
1949 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1950 MVT VT = Op.getSimpleValueType();
1951 MVT ScalarVT = VT.getScalarType();
1956 SDValue Src = Op.getOperand(0);
1959 // TODO: Don't scalarize on Evergreen?
1960 unsigned NElts = VT.getVectorNumElements();
1961 SmallVector<SDValue, 8> Args;
1962 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1964 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1965 for (unsigned I = 0; I < NElts; ++I)
1966 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1968 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1971 //===----------------------------------------------------------------------===//
1972 // Custom DAG optimizations
1973 //===----------------------------------------------------------------------===//
1975 static bool isU24(SDValue Op, SelectionDAG &DAG) {
1976 APInt KnownZero, KnownOne;
1977 EVT VT = Op.getValueType();
1978 DAG.computeKnownBits(Op, KnownZero, KnownOne);
1980 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1983 static bool isI24(SDValue Op, SelectionDAG &DAG) {
1984 EVT VT = Op.getValueType();
1986 // In order for this to be a signed 24-bit value, bit 23, must
1988 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1989 // as unsigned 24-bit values.
1990 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1993 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
1995 SelectionDAG &DAG = DCI.DAG;
1996 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1997 EVT VT = Op.getValueType();
1999 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2000 APInt KnownZero, KnownOne;
2001 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2002 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2003 DCI.CommitTargetLoweringOpt(TLO);
2006 template <typename IntTy>
2007 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2008 uint32_t Offset, uint32_t Width) {
2009 if (Width + Offset < 32) {
2010 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2011 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2012 return DAG.getConstant(Result, MVT::i32);
2015 return DAG.getConstant(Src0 >> Offset, MVT::i32);
2018 static bool usesAllNormalStores(SDNode *LoadVal) {
2019 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2020 if (!ISD::isNormalStore(*I))
2027 // If we have a copy of an illegal type, replace it with a load / store of an
2028 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2029 // instructions emitted when handling extloads and truncstores. Ideally we could
2030 // recognize the pack / unpack pattern to eliminate it.
2031 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2032 DAGCombinerInfo &DCI) const {
2033 if (!DCI.isBeforeLegalize())
2036 StoreSDNode *SN = cast<StoreSDNode>(N);
2037 SDValue Value = SN->getValue();
2038 EVT VT = Value.getValueType();
2040 if (isTypeLegal(VT) || SN->isVolatile() || !ISD::isNormalLoad(Value.getNode()))
2043 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2044 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2047 EVT MemVT = LoadVal->getMemoryVT();
2050 SelectionDAG &DAG = DCI.DAG;
2051 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2053 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2055 LoadVal->getChain(),
2056 LoadVal->getBasePtr(),
2057 LoadVal->getOffset(),
2059 LoadVal->getMemOperand());
2061 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2062 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2064 return DAG.getStore(SN->getChain(), SL, NewLoad,
2065 SN->getBasePtr(), SN->getMemOperand());
2068 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2069 DAGCombinerInfo &DCI) const {
2070 EVT VT = N->getValueType(0);
2072 if (VT.isVector() || VT.getSizeInBits() > 32)
2075 SelectionDAG &DAG = DCI.DAG;
2078 SDValue N0 = N->getOperand(0);
2079 SDValue N1 = N->getOperand(1);
2082 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2083 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2084 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2085 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2086 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2087 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2088 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2089 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2094 // We need to use sext even for MUL_U24, because MUL_U24 is used
2095 // for signed multiply of 8 and 16-bit types.
2096 return DAG.getSExtOrTrunc(Mul, DL, VT);
2099 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2100 DAGCombinerInfo &DCI) const {
2101 SelectionDAG &DAG = DCI.DAG;
2104 switch(N->getOpcode()) {
2107 return performMulCombine(N, DCI);
2108 case AMDGPUISD::MUL_I24:
2109 case AMDGPUISD::MUL_U24: {
2110 SDValue N0 = N->getOperand(0);
2111 SDValue N1 = N->getOperand(1);
2112 simplifyI24(N0, DCI);
2113 simplifyI24(N1, DCI);
2116 case ISD::SELECT_CC: {
2118 EVT VT = N->getValueType(0);
2120 SDValue LHS = N->getOperand(0);
2121 SDValue RHS = N->getOperand(1);
2122 SDValue True = N->getOperand(2);
2123 SDValue False = N->getOperand(3);
2124 SDValue CC = N->getOperand(4);
2126 return CombineMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
2129 SDValue Cond = N->getOperand(0);
2130 if (Cond.getOpcode() == ISD::SETCC) {
2132 EVT VT = N->getValueType(0);
2134 SDValue LHS = Cond.getOperand(0);
2135 SDValue RHS = Cond.getOperand(1);
2136 SDValue CC = Cond.getOperand(2);
2138 SDValue True = N->getOperand(1);
2139 SDValue False = N->getOperand(2);
2142 return CombineMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
2147 case AMDGPUISD::BFE_I32:
2148 case AMDGPUISD::BFE_U32: {
2149 assert(!N->getValueType(0).isVector() &&
2150 "Vector handling of BFE not implemented");
2151 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2155 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2157 return DAG.getConstant(0, MVT::i32);
2159 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2163 SDValue BitsFrom = N->getOperand(0);
2164 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2166 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2168 if (OffsetVal == 0) {
2169 // This is already sign / zero extended, so try to fold away extra BFEs.
2170 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2172 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2173 if (OpSignBits >= SignBits)
2176 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2178 // This is a sign_extend_inreg. Replace it to take advantage of existing
2179 // DAG Combines. If not eliminated, we will match back to BFE during
2182 // TODO: The sext_inreg of extended types ends, although we can could
2183 // handle them in a single BFE.
2184 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2185 DAG.getValueType(SmallVT));
2188 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2191 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2193 return constantFoldBFE<int32_t>(DAG,
2194 CVal->getSExtValue(),
2199 return constantFoldBFE<uint32_t>(DAG,
2200 CVal->getZExtValue(),
2205 if ((OffsetVal + WidthVal) >= 32) {
2206 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
2207 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2208 BitsFrom, ShiftVal);
2211 if (BitsFrom.hasOneUse()) {
2212 APInt Demanded = APInt::getBitsSet(32,
2214 OffsetVal + WidthVal);
2216 APInt KnownZero, KnownOne;
2217 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2218 !DCI.isBeforeLegalizeOps());
2219 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2220 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2221 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2222 KnownZero, KnownOne, TLO)) {
2223 DCI.CommitTargetLoweringOpt(TLO);
2231 return performStoreCombine(N, DCI);
2236 //===----------------------------------------------------------------------===//
2238 //===----------------------------------------------------------------------===//
2240 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2243 const SmallVectorImpl<ISD::InputArg> &Ins,
2244 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2246 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2247 if (Ins[i].ArgVT == Ins[i].VT) {
2248 OrigIns.push_back(Ins[i]);
2253 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2254 // Vector has been split into scalars.
2255 VT = Ins[i].ArgVT.getVectorElementType();
2256 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2257 Ins[i].ArgVT.getVectorElementType() !=
2258 Ins[i].VT.getVectorElementType()) {
2259 // Vector elements have been promoted
2262 // Vector has been spilt into smaller vectors.
2266 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2267 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2268 OrigIns.push_back(Arg);
2272 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2273 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2274 return CFP->isExactlyValue(1.0);
2276 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2277 return C->isAllOnesValue();
2282 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2283 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2284 return CFP->getValueAPF().isZero();
2286 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2287 return C->isNullValue();
2292 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2293 const TargetRegisterClass *RC,
2294 unsigned Reg, EVT VT) const {
2295 MachineFunction &MF = DAG.getMachineFunction();
2296 MachineRegisterInfo &MRI = MF.getRegInfo();
2297 unsigned VirtualRegister;
2298 if (!MRI.isLiveIn(Reg)) {
2299 VirtualRegister = MRI.createVirtualRegister(RC);
2300 MRI.addLiveIn(Reg, VirtualRegister);
2302 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2304 return DAG.getRegister(VirtualRegister, VT);
2307 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2309 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2311 default: return nullptr;
2313 NODE_NAME_CASE(CALL);
2314 NODE_NAME_CASE(UMUL);
2315 NODE_NAME_CASE(RET_FLAG);
2316 NODE_NAME_CASE(BRANCH_COND);
2319 NODE_NAME_CASE(DWORDADDR)
2320 NODE_NAME_CASE(FRACT)
2321 NODE_NAME_CASE(CLAMP)
2323 NODE_NAME_CASE(FMAX_LEGACY)
2324 NODE_NAME_CASE(SMAX)
2325 NODE_NAME_CASE(UMAX)
2326 NODE_NAME_CASE(FMIN_LEGACY)
2327 NODE_NAME_CASE(SMIN)
2328 NODE_NAME_CASE(UMIN)
2329 NODE_NAME_CASE(URECIP)
2330 NODE_NAME_CASE(DIV_SCALE)
2331 NODE_NAME_CASE(DIV_FMAS)
2332 NODE_NAME_CASE(DIV_FIXUP)
2333 NODE_NAME_CASE(TRIG_PREOP)
2336 NODE_NAME_CASE(RSQ_LEGACY)
2337 NODE_NAME_CASE(RSQ_CLAMPED)
2338 NODE_NAME_CASE(LDEXP)
2339 NODE_NAME_CASE(DOT4)
2340 NODE_NAME_CASE(BFE_U32)
2341 NODE_NAME_CASE(BFE_I32)
2344 NODE_NAME_CASE(BREV)
2345 NODE_NAME_CASE(MUL_U24)
2346 NODE_NAME_CASE(MUL_I24)
2347 NODE_NAME_CASE(MAD_U24)
2348 NODE_NAME_CASE(MAD_I24)
2349 NODE_NAME_CASE(EXPORT)
2350 NODE_NAME_CASE(CONST_ADDRESS)
2351 NODE_NAME_CASE(REGISTER_LOAD)
2352 NODE_NAME_CASE(REGISTER_STORE)
2353 NODE_NAME_CASE(LOAD_CONSTANT)
2354 NODE_NAME_CASE(LOAD_INPUT)
2355 NODE_NAME_CASE(SAMPLE)
2356 NODE_NAME_CASE(SAMPLEB)
2357 NODE_NAME_CASE(SAMPLED)
2358 NODE_NAME_CASE(SAMPLEL)
2359 NODE_NAME_CASE(CVT_F32_UBYTE0)
2360 NODE_NAME_CASE(CVT_F32_UBYTE1)
2361 NODE_NAME_CASE(CVT_F32_UBYTE2)
2362 NODE_NAME_CASE(CVT_F32_UBYTE3)
2363 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2364 NODE_NAME_CASE(CONST_DATA_PTR)
2365 NODE_NAME_CASE(STORE_MSKOR)
2366 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2370 static void computeKnownBitsForMinMax(const SDValue Op0,
2374 const SelectionDAG &DAG,
2376 APInt Op0Zero, Op0One;
2377 APInt Op1Zero, Op1One;
2378 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2379 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2381 KnownZero = Op0Zero & Op1Zero;
2382 KnownOne = Op0One & Op1One;
2385 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2389 const SelectionDAG &DAG,
2390 unsigned Depth) const {
2392 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2396 unsigned Opc = Op.getOpcode();
2401 case ISD::INTRINSIC_WO_CHAIN: {
2402 // FIXME: The intrinsic should just use the node.
2403 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2404 case AMDGPUIntrinsic::AMDGPU_imax:
2405 case AMDGPUIntrinsic::AMDGPU_umax:
2406 case AMDGPUIntrinsic::AMDGPU_imin:
2407 case AMDGPUIntrinsic::AMDGPU_umin:
2408 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2409 KnownZero, KnownOne, DAG, Depth);
2417 case AMDGPUISD::SMAX:
2418 case AMDGPUISD::UMAX:
2419 case AMDGPUISD::SMIN:
2420 case AMDGPUISD::UMIN:
2421 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2422 KnownZero, KnownOne, DAG, Depth);
2425 case AMDGPUISD::BFE_I32:
2426 case AMDGPUISD::BFE_U32: {
2427 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2431 unsigned BitWidth = 32;
2432 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2434 if (Opc == AMDGPUISD::BFE_U32)
2435 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2442 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2444 const SelectionDAG &DAG,
2445 unsigned Depth) const {
2446 switch (Op.getOpcode()) {
2447 case AMDGPUISD::BFE_I32: {
2448 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2452 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2453 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2454 if (!Offset || !Offset->isNullValue())
2457 // TODO: Could probably figure something out with non-0 offsets.
2458 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2459 return std::max(SignBits, Op0SignBits);
2462 case AMDGPUISD::BFE_U32: {
2463 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2464 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;