1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DiagnosticInfo.h"
31 #include "llvm/IR/DiagnosticPrinter.h"
37 /// Diagnostic information for unimplemented or unsupported feature reporting.
38 class DiagnosticInfoUnsupported : public DiagnosticInfo {
40 const Twine &Description;
45 static int getKindID() {
47 KindID = llvm::getNextAvailablePluginDiagnosticKind();
52 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
53 DiagnosticSeverity Severity = DS_Error)
54 : DiagnosticInfo(getKindID(), Severity),
58 const Function &getFunction() const { return Fn; }
59 const Twine &getDescription() const { return Description; }
61 void print(DiagnosticPrinter &DP) const override {
62 DP << "unsupported " << getDescription() << " in " << Fn.getName();
65 static bool classof(const DiagnosticInfo *DI) {
66 return DI->getKind() == getKindID();
70 int DiagnosticInfoUnsupported::KindID = 0;
74 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
75 CCValAssign::LocInfo LocInfo,
76 ISD::ArgFlagsTy ArgFlags, CCState &State) {
77 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
78 ArgFlags.getOrigAlign());
79 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
84 #include "AMDGPUGenCallingConv.inc"
86 // Find a larger type to do a load / store of a vector with.
87 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
88 unsigned StoreSize = VT.getStoreSizeInBits();
90 return EVT::getIntegerVT(Ctx, StoreSize);
92 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
93 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
96 // Type for a vector that will be loaded to.
97 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
98 unsigned StoreSize = VT.getStoreSizeInBits();
100 return EVT::getIntegerVT(Ctx, 32);
102 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
105 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
108 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
110 setOperationAction(ISD::Constant, MVT::i32, Legal);
111 setOperationAction(ISD::Constant, MVT::i64, Legal);
112 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
113 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
115 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
116 setOperationAction(ISD::BRIND, MVT::Other, Expand);
118 // We need to custom lower some of the intrinsics
119 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
121 // Library functions. These default to Expand, but we have instructions
123 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
124 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
125 setOperationAction(ISD::FPOW, MVT::f32, Legal);
126 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
127 setOperationAction(ISD::FABS, MVT::f32, Legal);
128 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
129 setOperationAction(ISD::FRINT, MVT::f32, Legal);
130 setOperationAction(ISD::FROUND, MVT::f32, Legal);
131 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
133 setOperationAction(ISD::FREM, MVT::f32, Custom);
134 setOperationAction(ISD::FREM, MVT::f64, Custom);
136 // Lower floating point store/load to integer store/load to reduce the number
137 // of patterns in tablegen.
138 setOperationAction(ISD::STORE, MVT::f32, Promote);
139 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
141 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
142 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
144 setOperationAction(ISD::STORE, MVT::i64, Promote);
145 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
147 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
148 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
150 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
151 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
153 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
154 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
156 setOperationAction(ISD::STORE, MVT::f64, Promote);
157 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
159 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
160 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
162 // Custom lowering of vector stores is required for local address space
164 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
165 // XXX: Native v2i32 local address space stores are possible, but not
166 // currently implemented.
167 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
169 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
170 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
171 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
173 // XXX: This can be change to Custom, once ExpandVectorStores can
174 // handle 64-bit stores.
175 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
177 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
178 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
179 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
180 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
181 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
184 setOperationAction(ISD::LOAD, MVT::f32, Promote);
185 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
187 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
188 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
190 setOperationAction(ISD::LOAD, MVT::i64, Promote);
191 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
193 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
194 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
196 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
199 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
200 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
202 setOperationAction(ISD::LOAD, MVT::f64, Promote);
203 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
205 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
206 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
208 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
209 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
210 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
211 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
212 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
213 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
214 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
215 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
216 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
217 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
219 for (MVT VT : MVT::integer_vector_valuetypes()) {
220 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i8, Expand);
221 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i8, Expand);
222 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
223 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i8, Expand);
224 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i8, Expand);
225 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
226 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand);
227 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand);
228 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
229 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand);
230 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand);
231 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
234 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
236 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
237 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
238 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
239 setOperationAction(ISD::FRINT, MVT::f64, Custom);
240 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
243 if (!Subtarget->hasBFI()) {
244 // fcopysign can be done in a single instruction with BFI.
245 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
246 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
249 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
251 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
252 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
253 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
254 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
256 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
257 for (MVT VT : ScalarIntVTs) {
258 setOperationAction(ISD::SREM, VT, Expand);
259 setOperationAction(ISD::SDIV, VT, Expand);
261 // GPU does not have divrem function for signed or unsigned.
262 setOperationAction(ISD::SDIVREM, VT, Custom);
263 setOperationAction(ISD::UDIVREM, VT, Custom);
265 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
266 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
267 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
269 setOperationAction(ISD::BSWAP, VT, Expand);
270 setOperationAction(ISD::CTTZ, VT, Expand);
271 setOperationAction(ISD::CTLZ, VT, Expand);
274 if (!Subtarget->hasBCNT(32))
275 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
277 if (!Subtarget->hasBCNT(64))
278 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
280 // The hardware supports 32-bit ROTR, but not ROTL.
281 setOperationAction(ISD::ROTL, MVT::i32, Expand);
282 setOperationAction(ISD::ROTL, MVT::i64, Expand);
283 setOperationAction(ISD::ROTR, MVT::i64, Expand);
285 setOperationAction(ISD::MUL, MVT::i64, Expand);
286 setOperationAction(ISD::MULHU, MVT::i64, Expand);
287 setOperationAction(ISD::MULHS, MVT::i64, Expand);
288 setOperationAction(ISD::UDIV, MVT::i32, Expand);
289 setOperationAction(ISD::UREM, MVT::i32, Expand);
290 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
291 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
292 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
293 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
294 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
296 if (!Subtarget->hasFFBH())
297 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
299 if (!Subtarget->hasFFBL())
300 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
302 static const MVT::SimpleValueType VectorIntTypes[] = {
303 MVT::v2i32, MVT::v4i32
306 for (MVT VT : VectorIntTypes) {
307 // Expand the following operations for the current type by default.
308 setOperationAction(ISD::ADD, VT, Expand);
309 setOperationAction(ISD::AND, VT, Expand);
310 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
311 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
312 setOperationAction(ISD::MUL, VT, Expand);
313 setOperationAction(ISD::OR, VT, Expand);
314 setOperationAction(ISD::SHL, VT, Expand);
315 setOperationAction(ISD::SRA, VT, Expand);
316 setOperationAction(ISD::SRL, VT, Expand);
317 setOperationAction(ISD::ROTL, VT, Expand);
318 setOperationAction(ISD::ROTR, VT, Expand);
319 setOperationAction(ISD::SUB, VT, Expand);
320 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
321 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
322 setOperationAction(ISD::SDIV, VT, Expand);
323 setOperationAction(ISD::UDIV, VT, Expand);
324 setOperationAction(ISD::SREM, VT, Expand);
325 setOperationAction(ISD::UREM, VT, Expand);
326 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
327 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
328 setOperationAction(ISD::SDIVREM, VT, Custom);
329 setOperationAction(ISD::UDIVREM, VT, Custom);
330 setOperationAction(ISD::ADDC, VT, Expand);
331 setOperationAction(ISD::SUBC, VT, Expand);
332 setOperationAction(ISD::ADDE, VT, Expand);
333 setOperationAction(ISD::SUBE, VT, Expand);
334 setOperationAction(ISD::SELECT, VT, Expand);
335 setOperationAction(ISD::VSELECT, VT, Expand);
336 setOperationAction(ISD::SELECT_CC, VT, Expand);
337 setOperationAction(ISD::XOR, VT, Expand);
338 setOperationAction(ISD::BSWAP, VT, Expand);
339 setOperationAction(ISD::CTPOP, VT, Expand);
340 setOperationAction(ISD::CTTZ, VT, Expand);
341 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
342 setOperationAction(ISD::CTLZ, VT, Expand);
343 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
344 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
347 static const MVT::SimpleValueType FloatVectorTypes[] = {
348 MVT::v2f32, MVT::v4f32
351 for (MVT VT : FloatVectorTypes) {
352 setOperationAction(ISD::FABS, VT, Expand);
353 setOperationAction(ISD::FMINNUM, VT, Expand);
354 setOperationAction(ISD::FMAXNUM, VT, Expand);
355 setOperationAction(ISD::FADD, VT, Expand);
356 setOperationAction(ISD::FCEIL, VT, Expand);
357 setOperationAction(ISD::FCOS, VT, Expand);
358 setOperationAction(ISD::FDIV, VT, Expand);
359 setOperationAction(ISD::FEXP2, VT, Expand);
360 setOperationAction(ISD::FLOG2, VT, Expand);
361 setOperationAction(ISD::FREM, VT, Expand);
362 setOperationAction(ISD::FPOW, VT, Expand);
363 setOperationAction(ISD::FFLOOR, VT, Expand);
364 setOperationAction(ISD::FTRUNC, VT, Expand);
365 setOperationAction(ISD::FMUL, VT, Expand);
366 setOperationAction(ISD::FMA, VT, Expand);
367 setOperationAction(ISD::FRINT, VT, Expand);
368 setOperationAction(ISD::FNEARBYINT, VT, Expand);
369 setOperationAction(ISD::FSQRT, VT, Expand);
370 setOperationAction(ISD::FSIN, VT, Expand);
371 setOperationAction(ISD::FSUB, VT, Expand);
372 setOperationAction(ISD::FNEG, VT, Expand);
373 setOperationAction(ISD::SELECT, VT, Expand);
374 setOperationAction(ISD::VSELECT, VT, Expand);
375 setOperationAction(ISD::SELECT_CC, VT, Expand);
376 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
377 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
380 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
381 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
383 setTargetDAGCombine(ISD::MUL);
384 setTargetDAGCombine(ISD::SELECT);
385 setTargetDAGCombine(ISD::SELECT_CC);
386 setTargetDAGCombine(ISD::STORE);
388 setBooleanContents(ZeroOrNegativeOneBooleanContent);
389 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
391 setSchedulingPreference(Sched::RegPressure);
392 setJumpIsExpensive(true);
394 // SI at least has hardware support for floating point exceptions, but no way
395 // of using or handling them is implemented. They are also optional in OpenCL
397 setHasFloatingPointExceptions(false);
399 setSelectIsExpensive(false);
400 PredictableSelectIsExpensive = false;
402 // There are no integer divide instructions, and these expand to a pretty
403 // large sequence of instructions.
404 setIntDivIsCheap(false);
405 setPow2SDivIsCheap(false);
407 // FIXME: Need to really handle these.
408 MaxStoresPerMemcpy = 4096;
409 MaxStoresPerMemmove = 4096;
410 MaxStoresPerMemset = 4096;
413 //===----------------------------------------------------------------------===//
414 // Target Information
415 //===----------------------------------------------------------------------===//
417 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
421 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
425 // The backend supports 32 and 64 bit floating point immediates.
426 // FIXME: Why are we reporting vectors of FP immediates as legal?
427 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
428 EVT ScalarVT = VT.getScalarType();
429 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
432 // We don't want to shrink f64 / f32 constants.
433 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
434 EVT ScalarVT = VT.getScalarType();
435 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
438 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
442 unsigned NewSize = NewVT.getStoreSizeInBits();
444 // If we are reducing to a 32-bit load, this is always better.
448 EVT OldVT = N->getValueType(0);
449 unsigned OldSize = OldVT.getStoreSizeInBits();
451 // Don't produce extloads from sub 32-bit types. SI doesn't have scalar
452 // extloads, so doing one requires using a buffer_load. In cases where we
453 // still couldn't use a scalar load, using the wider load shouldn't really
456 // If the old size already had to be an extload, there's no harm in continuing
457 // to reduce the width.
458 return (OldSize < 32);
461 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
463 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
466 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
467 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
469 return ((LScalarSize <= CastScalarSize) ||
470 (CastScalarSize >= 32) ||
474 // SI+ has instructions for cttz / ctlz for 32-bit values. This is probably also
475 // profitable with the expansion for 64-bit since it's generally good to
477 // FIXME: These should really have the size as a parameter.
478 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
482 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
486 //===---------------------------------------------------------------------===//
488 //===---------------------------------------------------------------------===//
490 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
491 assert(VT.isFloatingPoint());
492 return VT == MVT::f32 || VT == MVT::f64;
495 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
496 assert(VT.isFloatingPoint());
497 return VT == MVT::f32 || VT == MVT::f64;
500 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
501 // Truncate is just accessing a subregister.
502 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
505 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
506 // Truncate is just accessing a subregister.
507 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
508 (Dest->getPrimitiveSizeInBits() % 32 == 0);
511 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
512 const DataLayout *DL = getDataLayout();
513 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
514 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
516 return SrcSize == 32 && DestSize == 64;
519 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
520 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
521 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
522 // this will enable reducing 64-bit operations the 32-bit, which is always
524 return Src == MVT::i32 && Dest == MVT::i64;
527 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
528 return isZExtFree(Val.getValueType(), VT2);
531 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
532 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
533 // limited number of native 64-bit operations. Shrinking an operation to fit
534 // in a single 32-bit register should always be helpful. As currently used,
535 // this is much less general than the name suggests, and is only used in
536 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
537 // not profitable, and may actually be harmful.
538 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
541 //===---------------------------------------------------------------------===//
542 // TargetLowering Callbacks
543 //===---------------------------------------------------------------------===//
545 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
546 const SmallVectorImpl<ISD::InputArg> &Ins) const {
548 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
551 SDValue AMDGPUTargetLowering::LowerReturn(
553 CallingConv::ID CallConv,
555 const SmallVectorImpl<ISD::OutputArg> &Outs,
556 const SmallVectorImpl<SDValue> &OutVals,
557 SDLoc DL, SelectionDAG &DAG) const {
558 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
561 //===---------------------------------------------------------------------===//
562 // Target specific lowering
563 //===---------------------------------------------------------------------===//
565 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
566 SmallVectorImpl<SDValue> &InVals) const {
567 SDValue Callee = CLI.Callee;
568 SelectionDAG &DAG = CLI.DAG;
570 const Function &Fn = *DAG.getMachineFunction().getFunction();
572 StringRef FuncName("<unknown>");
574 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
575 FuncName = G->getSymbol();
576 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
577 FuncName = G->getGlobal()->getName();
579 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
580 DAG.getContext()->diagnose(NoCalls);
584 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
585 SelectionDAG &DAG) const {
586 switch (Op.getOpcode()) {
588 Op.getNode()->dump();
589 llvm_unreachable("Custom lowering code for this"
590 "instruction is not implemented yet!");
592 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
593 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
594 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
595 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
596 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
597 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
598 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
599 case ISD::FREM: return LowerFREM(Op, DAG);
600 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
601 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
602 case ISD::FRINT: return LowerFRINT(Op, DAG);
603 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
604 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
605 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
606 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
607 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
608 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG);
613 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
614 SmallVectorImpl<SDValue> &Results,
615 SelectionDAG &DAG) const {
616 switch (N->getOpcode()) {
617 case ISD::SIGN_EXTEND_INREG:
618 // Different parts of legalization seem to interpret which type of
619 // sign_extend_inreg is the one to check for custom lowering. The extended
620 // from type is what really matters, but some places check for custom
621 // lowering of the result type. This results in trying to use
622 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
623 // nothing here and let the illegal result integer be handled normally.
626 SDNode *Node = LowerLOAD(SDValue(N, 0), DAG).getNode();
630 Results.push_back(SDValue(Node, 0));
631 Results.push_back(SDValue(Node, 1));
632 // XXX: LLVM seems not to replace Chain Value inside CustomWidenLowerNode
634 DAG.ReplaceAllUsesOfValueWith(SDValue(N,1), SDValue(Node, 1));
638 SDValue Lowered = LowerSTORE(SDValue(N, 0), DAG);
639 if (Lowered.getNode())
640 Results.push_back(Lowered);
648 // FIXME: This implements accesses to initialized globals in the constant
649 // address space by copying them to private and accessing that. It does not
650 // properly handle illegal types or vectors. The private vector loads are not
651 // scalarized, and the illegal scalars hit an assertion. This technique will not
652 // work well with large initializers, and this should eventually be
653 // removed. Initialized globals should be placed into a data section that the
654 // runtime will load into a buffer before the kernel is executed. Uses of the
655 // global need to be replaced with a pointer loaded from an implicit kernel
656 // argument into this buffer holding the copy of the data, which will remove the
657 // need for any of this.
658 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
659 const GlobalValue *GV,
660 const SDValue &InitPtr,
662 SelectionDAG &DAG) const {
663 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
665 Type *InitTy = Init->getType();
667 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
668 EVT VT = EVT::getEVT(InitTy);
669 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
670 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
671 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
672 TD->getPrefTypeAlignment(InitTy));
675 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
676 EVT VT = EVT::getEVT(CFP->getType());
677 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
678 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
679 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
680 TD->getPrefTypeAlignment(CFP->getType()));
683 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
684 const StructLayout *SL = TD->getStructLayout(ST);
686 EVT PtrVT = InitPtr.getValueType();
687 SmallVector<SDValue, 8> Chains;
689 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
690 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
691 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
693 Constant *Elt = Init->getAggregateElement(I);
694 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
697 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
700 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
701 EVT PtrVT = InitPtr.getValueType();
703 unsigned NumElements;
704 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
705 NumElements = AT->getNumElements();
706 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
707 NumElements = VT->getNumElements();
709 llvm_unreachable("Unexpected type");
711 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
712 SmallVector<SDValue, 8> Chains;
713 for (unsigned i = 0; i < NumElements; ++i) {
714 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
715 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
717 Constant *Elt = Init->getAggregateElement(i);
718 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
721 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
724 if (isa<UndefValue>(Init)) {
725 EVT VT = EVT::getEVT(InitTy);
726 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
727 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
728 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
729 TD->getPrefTypeAlignment(InitTy));
733 llvm_unreachable("Unhandled constant initializer");
736 static bool hasDefinedInitializer(const GlobalValue *GV) {
737 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
738 if (!GVar || !GVar->hasInitializer())
741 if (isa<UndefValue>(GVar->getInitializer()))
747 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
749 SelectionDAG &DAG) const {
751 const DataLayout *TD = getTargetMachine().getSubtargetImpl()->getDataLayout();
752 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
753 const GlobalValue *GV = G->getGlobal();
755 switch (G->getAddressSpace()) {
756 case AMDGPUAS::LOCAL_ADDRESS: {
757 // XXX: What does the value of G->getOffset() mean?
758 assert(G->getOffset() == 0 &&
759 "Do not know what to do with an non-zero offset");
761 // TODO: We could emit code to handle the initialization somewhere.
762 if (hasDefinedInitializer(GV))
766 if (MFI->LocalMemoryObjects.count(GV) == 0) {
767 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
768 Offset = MFI->LDSSize;
769 MFI->LocalMemoryObjects[GV] = Offset;
770 // XXX: Account for alignment?
771 MFI->LDSSize += Size;
773 Offset = MFI->LocalMemoryObjects[GV];
776 return DAG.getConstant(Offset, getPointerTy(AMDGPUAS::LOCAL_ADDRESS));
778 case AMDGPUAS::CONSTANT_ADDRESS: {
779 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
780 Type *EltType = GV->getType()->getElementType();
781 unsigned Size = TD->getTypeAllocSize(EltType);
782 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
784 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
785 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
787 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
788 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
790 const GlobalVariable *Var = cast<GlobalVariable>(GV);
791 if (!Var->hasInitializer()) {
792 // This has no use, but bugpoint will hit it.
793 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
796 const Constant *Init = Var->getInitializer();
797 SmallVector<SDNode*, 8> WorkList;
799 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
800 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
801 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
803 WorkList.push_back(*I);
805 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
806 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
807 E = WorkList.end(); I != E; ++I) {
808 SmallVector<SDValue, 8> Ops;
809 Ops.push_back(Chain);
810 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
811 Ops.push_back((*I)->getOperand(i));
813 DAG.UpdateNodeOperands(*I, Ops);
815 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
819 const Function &Fn = *DAG.getMachineFunction().getFunction();
820 DiagnosticInfoUnsupported BadInit(Fn,
821 "initializer for address space");
822 DAG.getContext()->diagnose(BadInit);
826 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
827 SelectionDAG &DAG) const {
828 SmallVector<SDValue, 8> Args;
829 SDValue A = Op.getOperand(0);
830 SDValue B = Op.getOperand(1);
832 DAG.ExtractVectorElements(A, Args);
833 DAG.ExtractVectorElements(B, Args);
835 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
838 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
839 SelectionDAG &DAG) const {
841 SmallVector<SDValue, 8> Args;
842 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
843 EVT VT = Op.getValueType();
844 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
845 VT.getVectorNumElements());
847 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
850 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
851 SelectionDAG &DAG) const {
853 MachineFunction &MF = DAG.getMachineFunction();
854 const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>(
855 getTargetMachine().getSubtargetImpl()->getFrameLowering());
857 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
859 unsigned FrameIndex = FIN->getIndex();
860 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
861 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
865 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
866 SelectionDAG &DAG) const {
867 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
869 EVT VT = Op.getValueType();
871 switch (IntrinsicID) {
873 case AMDGPUIntrinsic::AMDGPU_abs:
874 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
875 return LowerIntrinsicIABS(Op, DAG);
876 case AMDGPUIntrinsic::AMDGPU_lrp:
877 return LowerIntrinsicLRP(Op, DAG);
878 case AMDGPUIntrinsic::AMDGPU_fract:
879 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
880 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
882 case AMDGPUIntrinsic::AMDGPU_clamp:
883 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
884 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
885 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
887 case Intrinsic::AMDGPU_div_scale: {
888 // 3rd parameter required to be a constant.
889 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
891 return DAG.getUNDEF(VT);
893 // Translate to the operands expected by the machine instruction. The
894 // first parameter must be the same as the first instruction.
895 SDValue Numerator = Op.getOperand(1);
896 SDValue Denominator = Op.getOperand(2);
898 // Note this order is opposite of the machine instruction's operations,
899 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
900 // intrinsic has the numerator as the first operand to match a normal
901 // division operation.
903 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
905 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
906 Denominator, Numerator);
909 case Intrinsic::AMDGPU_div_fmas:
910 // FIXME: Dropping bool parameter. Work is needed to support the implicit
912 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
913 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
915 case Intrinsic::AMDGPU_div_fixup:
916 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
917 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
919 case Intrinsic::AMDGPU_trig_preop:
920 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
921 Op.getOperand(1), Op.getOperand(2));
923 case Intrinsic::AMDGPU_rcp:
924 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
926 case Intrinsic::AMDGPU_rsq:
927 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
929 case AMDGPUIntrinsic::AMDGPU_legacy_rsq:
930 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
932 case Intrinsic::AMDGPU_rsq_clamped:
933 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
934 Type *Type = VT.getTypeForEVT(*DAG.getContext());
935 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
936 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
938 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
939 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
940 DAG.getConstantFP(Max, VT));
941 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
942 DAG.getConstantFP(Min, VT));
944 return DAG.getNode(AMDGPUISD::RSQ_CLAMPED, DL, VT, Op.getOperand(1));
947 case Intrinsic::AMDGPU_ldexp:
948 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT, Op.getOperand(1),
951 case AMDGPUIntrinsic::AMDGPU_imax:
952 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
954 case AMDGPUIntrinsic::AMDGPU_umax:
955 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
957 case AMDGPUIntrinsic::AMDGPU_imin:
958 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
960 case AMDGPUIntrinsic::AMDGPU_umin:
961 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
964 case AMDGPUIntrinsic::AMDGPU_umul24:
965 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
966 Op.getOperand(1), Op.getOperand(2));
968 case AMDGPUIntrinsic::AMDGPU_imul24:
969 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
970 Op.getOperand(1), Op.getOperand(2));
972 case AMDGPUIntrinsic::AMDGPU_umad24:
973 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
974 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
976 case AMDGPUIntrinsic::AMDGPU_imad24:
977 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
978 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
980 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
981 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
983 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
984 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
986 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
987 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
989 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
990 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
992 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
993 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
998 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
999 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
1004 case AMDGPUIntrinsic::AMDGPU_bfi:
1005 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
1010 case AMDGPUIntrinsic::AMDGPU_bfm:
1011 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
1015 case AMDGPUIntrinsic::AMDGPU_brev:
1016 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
1018 case Intrinsic::AMDGPU_class:
1019 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
1020 Op.getOperand(1), Op.getOperand(2));
1022 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
1023 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
1025 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
1026 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
1027 case AMDGPUIntrinsic::AMDGPU_trunc: // Legacy name.
1028 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
1032 ///IABS(a) = SMAX(sub(0, a), a)
1033 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
1034 SelectionDAG &DAG) const {
1036 EVT VT = Op.getValueType();
1037 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1040 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
1043 /// Linear Interpolation
1044 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
1045 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
1046 SelectionDAG &DAG) const {
1048 EVT VT = Op.getValueType();
1049 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
1050 DAG.getConstantFP(1.0f, MVT::f32),
1052 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
1054 return DAG.getNode(ISD::FADD, DL, VT,
1055 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
1059 /// \brief Generate Min/Max node
1060 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,
1067 DAGCombinerInfo &DCI) const {
1068 if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
1071 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1074 SelectionDAG &DAG = DCI.DAG;
1075 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1084 case ISD::SETFALSE2:
1093 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1094 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1100 // Ordered. Assume ordered for undefined.
1102 // Only do this after legalization to avoid interfering with other combines
1103 // which might occur.
1104 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1105 !DCI.isCalledByLegalizer())
1108 // We need to permute the operands to get the correct NaN behavior. The
1109 // selected operand is the second one based on the failing compare with NaN,
1110 // so permute it based on the compare type the hardware uses.
1112 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1113 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1118 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, RHS, LHS);
1119 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, LHS, RHS);
1125 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG &&
1126 !DCI.isCalledByLegalizer())
1130 return DAG.getNode(AMDGPUISD::FMAX_LEGACY, DL, VT, LHS, RHS);
1131 return DAG.getNode(AMDGPUISD::FMIN_LEGACY, DL, VT, RHS, LHS);
1133 case ISD::SETCC_INVALID:
1134 llvm_unreachable("Invalid setcc condcode!");
1139 /// \brief Generate Min/Max node
1140 SDValue AMDGPUTargetLowering::CombineIMinMax(SDLoc DL,
1147 SelectionDAG &DAG) const {
1148 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
1151 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
1155 unsigned Opc = (LHS == True) ? AMDGPUISD::UMIN : AMDGPUISD::UMAX;
1156 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1160 unsigned Opc = (LHS == True) ? AMDGPUISD::SMIN : AMDGPUISD::SMAX;
1161 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1165 unsigned Opc = (LHS == True) ? AMDGPUISD::SMAX : AMDGPUISD::SMIN;
1166 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1170 unsigned Opc = (LHS == True) ? AMDGPUISD::UMAX : AMDGPUISD::UMIN;
1171 return DAG.getNode(Opc, DL, VT, LHS, RHS);
1178 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,
1179 SelectionDAG &DAG) const {
1180 LoadSDNode *Load = cast<LoadSDNode>(Op);
1181 EVT MemVT = Load->getMemoryVT();
1182 EVT MemEltVT = MemVT.getVectorElementType();
1184 EVT LoadVT = Op.getValueType();
1185 EVT EltVT = LoadVT.getVectorElementType();
1186 EVT PtrVT = Load->getBasePtr().getValueType();
1188 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
1189 SmallVector<SDValue, 8> Loads;
1190 SmallVector<SDValue, 8> Chains;
1193 unsigned MemEltSize = MemEltVT.getStoreSize();
1194 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1196 for (unsigned i = 0; i < NumElts; ++i) {
1197 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
1198 DAG.getConstant(i * MemEltSize, PtrVT));
1201 = DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
1202 Load->getChain(), Ptr,
1203 SrcValue.getWithOffset(i * MemEltSize),
1204 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
1205 Load->isInvariant(), Load->getAlignment());
1206 Loads.push_back(NewLoad.getValue(0));
1207 Chains.push_back(NewLoad.getValue(1));
1211 DAG.getNode(ISD::BUILD_VECTOR, SL, LoadVT, Loads),
1212 DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains)
1215 return DAG.getMergeValues(Ops, SL);
1218 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1219 SelectionDAG &DAG) const {
1220 EVT VT = Op.getValueType();
1222 // If this is a 2 element vector, we really want to scalarize and not create
1223 // weird 1 element vectors.
1224 if (VT.getVectorNumElements() == 2)
1225 return ScalarizeVectorLoad(Op, DAG);
1227 LoadSDNode *Load = cast<LoadSDNode>(Op);
1228 SDValue BasePtr = Load->getBasePtr();
1229 EVT PtrVT = BasePtr.getValueType();
1230 EVT MemVT = Load->getMemoryVT();
1232 MachinePointerInfo SrcValue(Load->getMemOperand()->getValue());
1235 EVT LoMemVT, HiMemVT;
1238 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1239 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1240 std::tie(Lo, Hi) = DAG.SplitVector(Op, SL, LoVT, HiVT);
1242 = DAG.getExtLoad(Load->getExtensionType(), SL, LoVT,
1243 Load->getChain(), BasePtr,
1245 LoMemVT, Load->isVolatile(), Load->isNonTemporal(),
1246 Load->isInvariant(), Load->getAlignment());
1248 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1249 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1252 = DAG.getExtLoad(Load->getExtensionType(), SL, HiVT,
1253 Load->getChain(), HiPtr,
1254 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1255 HiMemVT, Load->isVolatile(), Load->isNonTemporal(),
1256 Load->isInvariant(), Load->getAlignment());
1259 DAG.getNode(ISD::CONCAT_VECTORS, SL, VT, LoLoad, HiLoad),
1260 DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
1261 LoLoad.getValue(1), HiLoad.getValue(1))
1264 return DAG.getMergeValues(Ops, SL);
1267 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1268 SelectionDAG &DAG) const {
1269 StoreSDNode *Store = cast<StoreSDNode>(Op);
1270 EVT MemVT = Store->getMemoryVT();
1271 unsigned MemBits = MemVT.getSizeInBits();
1273 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1274 // truncating store into an i32 store.
1275 // XXX: We could also handle optimize other vector bitwidths.
1276 if (!MemVT.isVector() || MemBits > 32) {
1281 SDValue Value = Store->getValue();
1282 EVT VT = Value.getValueType();
1283 EVT ElemVT = VT.getVectorElementType();
1284 SDValue Ptr = Store->getBasePtr();
1285 EVT MemEltVT = MemVT.getVectorElementType();
1286 unsigned MemEltBits = MemEltVT.getSizeInBits();
1287 unsigned MemNumElements = MemVT.getVectorNumElements();
1288 unsigned PackedSize = MemVT.getStoreSizeInBits();
1289 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1291 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1293 SDValue PackedValue;
1294 for (unsigned i = 0; i < MemNumElements; ++i) {
1295 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1296 DAG.getConstant(i, MVT::i32));
1297 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1298 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1300 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1301 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1306 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1310 if (PackedSize < 32) {
1311 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1312 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1313 Store->getMemOperand()->getPointerInfo(),
1315 Store->isNonTemporal(), Store->isVolatile(),
1316 Store->getAlignment());
1319 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1320 Store->getMemOperand()->getPointerInfo(),
1321 Store->isVolatile(), Store->isNonTemporal(),
1322 Store->getAlignment());
1325 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,
1326 SelectionDAG &DAG) const {
1327 StoreSDNode *Store = cast<StoreSDNode>(Op);
1328 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1329 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1330 EVT PtrVT = Store->getBasePtr().getValueType();
1331 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1334 SmallVector<SDValue, 8> Chains;
1336 unsigned EltSize = MemEltVT.getStoreSize();
1337 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1339 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1340 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1342 DAG.getConstant(i, MVT::i32));
1344 SDValue Offset = DAG.getConstant(i * MemEltVT.getStoreSize(), PtrVT);
1345 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Store->getBasePtr(), Offset);
1347 DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1348 SrcValue.getWithOffset(i * EltSize),
1349 MemEltVT, Store->isNonTemporal(), Store->isVolatile(),
1350 Store->getAlignment());
1351 Chains.push_back(NewStore);
1354 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1357 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1358 SelectionDAG &DAG) const {
1359 StoreSDNode *Store = cast<StoreSDNode>(Op);
1360 SDValue Val = Store->getValue();
1361 EVT VT = Val.getValueType();
1363 // If this is a 2 element vector, we really want to scalarize and not create
1364 // weird 1 element vectors.
1365 if (VT.getVectorNumElements() == 2)
1366 return ScalarizeVectorStore(Op, DAG);
1368 EVT MemVT = Store->getMemoryVT();
1369 SDValue Chain = Store->getChain();
1370 SDValue BasePtr = Store->getBasePtr();
1374 EVT LoMemVT, HiMemVT;
1377 std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(VT);
1378 std::tie(LoMemVT, HiMemVT) = DAG.GetSplitDestVTs(MemVT);
1379 std::tie(Lo, Hi) = DAG.SplitVector(Val, SL, LoVT, HiVT);
1381 EVT PtrVT = BasePtr.getValueType();
1382 SDValue HiPtr = DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
1383 DAG.getConstant(LoMemVT.getStoreSize(), PtrVT));
1385 MachinePointerInfo SrcValue(Store->getMemOperand()->getValue());
1387 = DAG.getTruncStore(Chain, SL, Lo,
1391 Store->isNonTemporal(),
1392 Store->isVolatile(),
1393 Store->getAlignment());
1395 = DAG.getTruncStore(Chain, SL, Hi,
1397 SrcValue.getWithOffset(LoMemVT.getStoreSize()),
1399 Store->isNonTemporal(),
1400 Store->isVolatile(),
1401 Store->getAlignment());
1403 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoStore, HiStore);
1407 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1409 LoadSDNode *Load = cast<LoadSDNode>(Op);
1410 ISD::LoadExtType ExtType = Load->getExtensionType();
1411 EVT VT = Op.getValueType();
1412 EVT MemVT = Load->getMemoryVT();
1414 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1415 // We can do the extload to 32-bits, and then need to separately extend to
1418 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1422 Load->getMemOperand());
1425 DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32),
1426 ExtLoad32.getValue(1)
1429 return DAG.getMergeValues(Ops, DL);
1432 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1433 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1434 // FIXME: Copied from PPC
1435 // First, load into 32 bits, then truncate to 1 bit.
1437 SDValue Chain = Load->getChain();
1438 SDValue BasePtr = Load->getBasePtr();
1439 MachineMemOperand *MMO = Load->getMemOperand();
1441 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1442 BasePtr, MVT::i8, MMO);
1445 DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD),
1449 return DAG.getMergeValues(Ops, DL);
1452 if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS ||
1453 Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1454 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1458 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1459 DAG.getConstant(2, MVT::i32));
1460 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1461 Load->getChain(), Ptr,
1462 DAG.getTargetConstant(0, MVT::i32),
1464 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1466 DAG.getConstant(0x3, MVT::i32));
1467 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1468 DAG.getConstant(3, MVT::i32));
1470 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1472 EVT MemEltVT = MemVT.getScalarType();
1473 if (ExtType == ISD::SEXTLOAD) {
1474 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1477 DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode),
1481 return DAG.getMergeValues(Ops, DL);
1485 DAG.getZeroExtendInReg(Ret, DL, MemEltVT),
1489 return DAG.getMergeValues(Ops, DL);
1492 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1494 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1495 if (Result.getNode()) {
1499 StoreSDNode *Store = cast<StoreSDNode>(Op);
1500 SDValue Chain = Store->getChain();
1501 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1502 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1503 Store->getValue().getValueType().isVector()) {
1504 return ScalarizeVectorStore(Op, DAG);
1507 EVT MemVT = Store->getMemoryVT();
1508 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1509 MemVT.bitsLT(MVT::i32)) {
1511 if (Store->getMemoryVT() == MVT::i8) {
1513 } else if (Store->getMemoryVT() == MVT::i16) {
1516 SDValue BasePtr = Store->getBasePtr();
1517 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1518 DAG.getConstant(2, MVT::i32));
1519 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1520 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1522 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1523 DAG.getConstant(0x3, MVT::i32));
1525 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1526 DAG.getConstant(3, MVT::i32));
1528 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1531 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1533 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1534 MaskedValue, ShiftAmt);
1536 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1538 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1539 DAG.getConstant(0xffffffff, MVT::i32));
1540 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1542 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1543 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1544 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1549 // This is a shortcut for integer division because we have fast i32<->f32
1550 // conversions, and fast f32 reciprocal instructions. The fractional part of a
1551 // float is enough to accurately represent up to a 24-bit integer.
1552 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {
1554 EVT VT = Op.getValueType();
1555 SDValue LHS = Op.getOperand(0);
1556 SDValue RHS = Op.getOperand(1);
1557 MVT IntVT = MVT::i32;
1558 MVT FltVT = MVT::f32;
1560 ISD::NodeType ToFp = sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP;
1561 ISD::NodeType ToInt = sign ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
1563 if (VT.isVector()) {
1564 unsigned NElts = VT.getVectorNumElements();
1565 IntVT = MVT::getVectorVT(MVT::i32, NElts);
1566 FltVT = MVT::getVectorVT(MVT::f32, NElts);
1569 unsigned BitSize = VT.getScalarType().getSizeInBits();
1571 SDValue jq = DAG.getConstant(1, IntVT);
1574 // char|short jq = ia ^ ib;
1575 jq = DAG.getNode(ISD::XOR, DL, VT, LHS, RHS);
1577 // jq = jq >> (bitsize - 2)
1578 jq = DAG.getNode(ISD::SRA, DL, VT, jq, DAG.getConstant(BitSize - 2, VT));
1581 jq = DAG.getNode(ISD::OR, DL, VT, jq, DAG.getConstant(1, VT));
1584 jq = DAG.getSExtOrTrunc(jq, DL, IntVT);
1587 // int ia = (int)LHS;
1589 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT);
1591 // int ib, (int)RHS;
1593 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT);
1595 // float fa = (float)ia;
1596 SDValue fa = DAG.getNode(ToFp, DL, FltVT, ia);
1598 // float fb = (float)ib;
1599 SDValue fb = DAG.getNode(ToFp, DL, FltVT, ib);
1601 // float fq = native_divide(fa, fb);
1602 SDValue fq = DAG.getNode(ISD::FMUL, DL, FltVT,
1603 fa, DAG.getNode(AMDGPUISD::RCP, DL, FltVT, fb));
1606 fq = DAG.getNode(ISD::FTRUNC, DL, FltVT, fq);
1608 // float fqneg = -fq;
1609 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FltVT, fq);
1611 // float fr = mad(fqneg, fb, fa);
1612 SDValue fr = DAG.getNode(ISD::FADD, DL, FltVT,
1613 DAG.getNode(ISD::FMUL, DL, FltVT, fqneg, fb), fa);
1615 // int iq = (int)fq;
1616 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq);
1619 fr = DAG.getNode(ISD::FABS, DL, FltVT, fr);
1622 fb = DAG.getNode(ISD::FABS, DL, FltVT, fb);
1624 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), VT);
1626 // int cv = fr >= fb;
1627 SDValue cv = DAG.getSetCC(DL, SetCCVT, fr, fb, ISD::SETOGE);
1629 // jq = (cv ? jq : 0);
1630 jq = DAG.getNode(ISD::SELECT, DL, VT, cv, jq, DAG.getConstant(0, VT));
1632 // dst = trunc/extend to legal type
1633 iq = sign ? DAG.getSExtOrTrunc(iq, DL, VT) : DAG.getZExtOrTrunc(iq, DL, VT);
1636 SDValue Div = DAG.getNode(ISD::ADD, DL, VT, iq, jq);
1638 // Rem needs compensation, it's easier to recompute it
1639 SDValue Rem = DAG.getNode(ISD::MUL, DL, VT, Div, RHS);
1640 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem);
1646 return DAG.getMergeValues(Res, DL);
1649 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1651 SmallVectorImpl<SDValue> &Results) const {
1652 assert(Op.getValueType() == MVT::i64);
1655 EVT VT = Op.getValueType();
1656 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
1658 SDValue one = DAG.getConstant(1, HalfVT);
1659 SDValue zero = DAG.getConstant(0, HalfVT);
1662 SDValue LHS = Op.getOperand(0);
1663 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
1664 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
1666 SDValue RHS = Op.getOperand(1);
1667 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
1668 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
1670 // Get Speculative values
1671 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
1672 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
1674 SDValue REM_Hi = zero;
1675 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
1677 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
1678 SDValue DIV_Lo = zero;
1680 const unsigned halfBitWidth = HalfVT.getSizeInBits();
1682 for (unsigned i = 0; i < halfBitWidth; ++i) {
1683 SDValue POS = DAG.getConstant(halfBitWidth - i - 1, HalfVT);
1684 // Get Value of high bit
1686 if (halfBitWidth == 32 && Subtarget->hasBFE()) {
1687 HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
1689 HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
1690 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
1693 SDValue Carry = DAG.getNode(ISD::SRL, DL, HalfVT, REM_Lo,
1694 DAG.getConstant(halfBitWidth - 1, HalfVT));
1695 REM_Hi = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Hi, one);
1696 REM_Hi = DAG.getNode(ISD::OR, DL, HalfVT, REM_Hi, Carry);
1698 REM_Lo = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Lo, one);
1699 REM_Lo = DAG.getNode(ISD::OR, DL, HalfVT, REM_Lo, HBit);
1702 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
1704 SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
1705 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETUGE);
1707 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
1711 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
1713 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETUGE);
1714 REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
1715 REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
1718 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
1719 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
1720 Results.push_back(DIV);
1721 Results.push_back(REM);
1724 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1725 SelectionDAG &DAG) const {
1727 EVT VT = Op.getValueType();
1729 if (VT == MVT::i64) {
1730 SmallVector<SDValue, 2> Results;
1731 LowerUDIVREM64(Op, DAG, Results);
1732 return DAG.getMergeValues(Results, DL);
1735 SDValue Num = Op.getOperand(0);
1736 SDValue Den = Op.getOperand(1);
1738 if (VT == MVT::i32) {
1739 if (DAG.MaskedValueIsZero(Op.getOperand(0), APInt(32, 0xff << 24)) &&
1740 DAG.MaskedValueIsZero(Op.getOperand(1), APInt(32, 0xff << 24))) {
1741 // TODO: We technically could do this for i64, but shouldn't that just be
1742 // handled by something generally reducing 64-bit division on 32-bit
1743 // values to 32-bit?
1744 return LowerDIVREM24(Op, DAG, false);
1748 // RCP = URECIP(Den) = 2^32 / Den + e
1749 // e is rounding error.
1750 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1752 // RCP_LO = mul(RCP, Den) */
1753 SDValue RCP_LO = DAG.getNode(ISD::MUL, DL, VT, RCP, Den);
1755 // RCP_HI = mulhu (RCP, Den) */
1756 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1758 // NEG_RCP_LO = -RCP_LO
1759 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1762 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1763 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1766 // Calculate the rounding error from the URECIP instruction
1767 // E = mulhu(ABS_RCP_LO, RCP)
1768 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1770 // RCP_A_E = RCP + E
1771 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1773 // RCP_S_E = RCP - E
1774 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1776 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1777 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1780 // Quotient = mulhu(Tmp0, Num)
1781 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1783 // Num_S_Remainder = Quotient * Den
1784 SDValue Num_S_Remainder = DAG.getNode(ISD::MUL, DL, VT, Quotient, Den);
1786 // Remainder = Num - Num_S_Remainder
1787 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1789 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1790 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1791 DAG.getConstant(-1, VT),
1792 DAG.getConstant(0, VT),
1794 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1795 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1797 DAG.getConstant(-1, VT),
1798 DAG.getConstant(0, VT),
1800 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1801 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1804 // Calculate Division result:
1806 // Quotient_A_One = Quotient + 1
1807 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1808 DAG.getConstant(1, VT));
1810 // Quotient_S_One = Quotient - 1
1811 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1812 DAG.getConstant(1, VT));
1814 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1815 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1816 Quotient, Quotient_A_One, ISD::SETEQ);
1818 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1819 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1820 Quotient_S_One, Div, ISD::SETEQ);
1822 // Calculate Rem result:
1824 // Remainder_S_Den = Remainder - Den
1825 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1827 // Remainder_A_Den = Remainder + Den
1828 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1830 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1831 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1832 Remainder, Remainder_S_Den, ISD::SETEQ);
1834 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1835 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1836 Remainder_A_Den, Rem, ISD::SETEQ);
1841 return DAG.getMergeValues(Ops, DL);
1844 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1845 SelectionDAG &DAG) const {
1847 EVT VT = Op.getValueType();
1849 SDValue LHS = Op.getOperand(0);
1850 SDValue RHS = Op.getOperand(1);
1852 if (VT == MVT::i32) {
1853 if (DAG.ComputeNumSignBits(Op.getOperand(0)) > 8 &&
1854 DAG.ComputeNumSignBits(Op.getOperand(1)) > 8) {
1855 // TODO: We technically could do this for i64, but shouldn't that just be
1856 // handled by something generally reducing 64-bit division on 32-bit
1857 // values to 32-bit?
1858 return LowerDIVREM24(Op, DAG, true);
1862 SDValue Zero = DAG.getConstant(0, VT);
1863 SDValue NegOne = DAG.getConstant(-1, VT);
1865 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1866 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1867 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1868 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1870 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1871 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1873 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1874 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1876 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1877 SDValue Rem = Div.getValue(1);
1879 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1880 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1882 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1883 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1889 return DAG.getMergeValues(Res, DL);
1892 // (frem x, y) -> (fsub x, (fmul (ftrunc (fdiv x, y)), y))
1893 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1895 EVT VT = Op.getValueType();
1896 SDValue X = Op.getOperand(0);
1897 SDValue Y = Op.getOperand(1);
1899 SDValue Div = DAG.getNode(ISD::FDIV, SL, VT, X, Y);
1900 SDValue Floor = DAG.getNode(ISD::FTRUNC, SL, VT, Div);
1901 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Floor, Y);
1903 return DAG.getNode(ISD::FSUB, SL, VT, X, Mul);
1906 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1908 SDValue Src = Op.getOperand(0);
1910 // result = trunc(src)
1911 // if (src > 0.0 && src != result)
1914 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1916 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1917 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1919 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1921 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1922 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1923 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1925 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1926 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1929 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1931 SDValue Src = Op.getOperand(0);
1933 assert(Op.getValueType() == MVT::f64);
1935 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1936 const SDValue One = DAG.getConstant(1, MVT::i32);
1938 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1940 // Extract the upper half, since this is where we will find the sign and
1942 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1944 const unsigned FractBits = 52;
1945 const unsigned ExpBits = 11;
1947 // Extract the exponent.
1948 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_U32, SL, MVT::i32,
1950 DAG.getConstant(FractBits - 32, MVT::i32),
1951 DAG.getConstant(ExpBits, MVT::i32));
1952 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1953 DAG.getConstant(1023, MVT::i32));
1955 // Extract the sign bit.
1956 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1957 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1959 // Extend back to to 64-bits.
1960 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1962 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1964 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1965 const SDValue FractMask
1966 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1968 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1969 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1970 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1972 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1974 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1976 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1977 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1979 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1980 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1982 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1985 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1987 SDValue Src = Op.getOperand(0);
1989 assert(Op.getValueType() == MVT::f64);
1991 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1992 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1993 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1995 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1996 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1998 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
2000 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
2001 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
2003 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
2004 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
2006 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
2009 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
2010 // FNEARBYINT and FRINT are the same, except in their handling of FP
2011 // exceptions. Those aren't really meaningful for us, and OpenCL only has
2012 // rint, so just treat them as equivalent.
2013 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
2016 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
2018 SDValue Src = Op.getOperand(0);
2020 // result = trunc(src);
2021 // if (src < 0.0 && src != result)
2024 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2026 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
2027 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
2029 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
2031 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
2032 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
2033 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
2035 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
2036 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
2039 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2040 bool Signed) const {
2042 SDValue Src = Op.getOperand(0);
2044 SDValue BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
2046 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2047 DAG.getConstant(0, MVT::i32));
2048 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC,
2049 DAG.getConstant(1, MVT::i32));
2051 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
2054 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo);
2056 SDValue LdExp = DAG.getNode(AMDGPUISD::LDEXP, SL, MVT::f64, CvtHi,
2057 DAG.getConstant(32, MVT::i32));
2059 return DAG.getNode(ISD::FADD, SL, MVT::f64, LdExp, CvtLo);
2062 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2063 SelectionDAG &DAG) const {
2064 SDValue S0 = Op.getOperand(0);
2065 if (S0.getValueType() != MVT::i64)
2068 EVT DestVT = Op.getValueType();
2069 if (DestVT == MVT::f64)
2070 return LowerINT_TO_FP64(Op, DAG, false);
2072 assert(DestVT == MVT::f32);
2076 // f32 uint_to_fp i64
2077 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2078 DAG.getConstant(0, MVT::i32));
2079 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
2080 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
2081 DAG.getConstant(1, MVT::i32));
2082 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
2083 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
2084 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
2085 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
2088 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2089 SelectionDAG &DAG) const {
2090 SDValue Src = Op.getOperand(0);
2091 if (Src.getValueType() == MVT::i64 && Op.getValueType() == MVT::f64)
2092 return LowerINT_TO_FP64(Op, DAG, true);
2097 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2098 bool Signed) const {
2101 SDValue Src = Op.getOperand(0);
2103 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
2106 = DAG.getConstantFP(BitsToDouble(UINT64_C(0x3df0000000000000)), MVT::f64);
2108 = DAG.getConstantFP(BitsToDouble(UINT64_C(0xc1f0000000000000)), MVT::f64);
2110 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, Trunc, K0);
2112 SDValue FloorMul = DAG.getNode(ISD::FFLOOR, SL, MVT::f64, Mul);
2115 SDValue Fma = DAG.getNode(ISD::FMA, SL, MVT::f64, FloorMul, K1, Trunc);
2117 SDValue Hi = DAG.getNode(Signed ? ISD::FP_TO_SINT : ISD::FP_TO_UINT, SL,
2118 MVT::i32, FloorMul);
2119 SDValue Lo = DAG.getNode(ISD::FP_TO_UINT, SL, MVT::i32, Fma);
2121 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Lo, Hi);
2123 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Result);
2126 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2127 SelectionDAG &DAG) const {
2128 SDValue Src = Op.getOperand(0);
2130 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2131 return LowerFP64_TO_INT(Op, DAG, true);
2136 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2137 SelectionDAG &DAG) const {
2138 SDValue Src = Op.getOperand(0);
2140 if (Op.getValueType() == MVT::i64 && Src.getValueType() == MVT::f64)
2141 return LowerFP64_TO_INT(Op, DAG, false);
2146 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2147 SelectionDAG &DAG) const {
2148 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
2149 MVT VT = Op.getSimpleValueType();
2150 MVT ScalarVT = VT.getScalarType();
2155 SDValue Src = Op.getOperand(0);
2158 // TODO: Don't scalarize on Evergreen?
2159 unsigned NElts = VT.getVectorNumElements();
2160 SmallVector<SDValue, 8> Args;
2161 DAG.ExtractVectorElements(Src, Args, 0, NElts);
2163 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
2164 for (unsigned I = 0; I < NElts; ++I)
2165 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
2167 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
2170 //===----------------------------------------------------------------------===//
2171 // Custom DAG optimizations
2172 //===----------------------------------------------------------------------===//
2174 static bool isU24(SDValue Op, SelectionDAG &DAG) {
2175 APInt KnownZero, KnownOne;
2176 EVT VT = Op.getValueType();
2177 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2179 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
2182 static bool isI24(SDValue Op, SelectionDAG &DAG) {
2183 EVT VT = Op.getValueType();
2185 // In order for this to be a signed 24-bit value, bit 23, must
2187 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
2188 // as unsigned 24-bit values.
2189 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
2192 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
2194 SelectionDAG &DAG = DCI.DAG;
2195 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2196 EVT VT = Op.getValueType();
2198 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
2199 APInt KnownZero, KnownOne;
2200 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
2201 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
2202 DCI.CommitTargetLoweringOpt(TLO);
2205 template <typename IntTy>
2206 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
2207 uint32_t Offset, uint32_t Width) {
2208 if (Width + Offset < 32) {
2209 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2210 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
2211 return DAG.getConstant(Result, MVT::i32);
2214 return DAG.getConstant(Src0 >> Offset, MVT::i32);
2217 static bool usesAllNormalStores(SDNode *LoadVal) {
2218 for (SDNode::use_iterator I = LoadVal->use_begin(); !I.atEnd(); ++I) {
2219 if (!ISD::isNormalStore(*I))
2226 // If we have a copy of an illegal type, replace it with a load / store of an
2227 // equivalently sized legal type. This avoids intermediate bit pack / unpack
2228 // instructions emitted when handling extloads and truncstores. Ideally we could
2229 // recognize the pack / unpack pattern to eliminate it.
2230 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2231 DAGCombinerInfo &DCI) const {
2232 if (!DCI.isBeforeLegalize())
2235 StoreSDNode *SN = cast<StoreSDNode>(N);
2236 SDValue Value = SN->getValue();
2237 EVT VT = Value.getValueType();
2239 if (isTypeLegal(VT) || SN->isVolatile() ||
2240 !ISD::isNormalLoad(Value.getNode()) || VT.getSizeInBits() < 8)
2243 LoadSDNode *LoadVal = cast<LoadSDNode>(Value);
2244 if (LoadVal->isVolatile() || !usesAllNormalStores(LoadVal))
2247 EVT MemVT = LoadVal->getMemoryVT();
2250 SelectionDAG &DAG = DCI.DAG;
2251 EVT LoadVT = getEquivalentMemType(*DAG.getContext(), MemVT);
2253 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD,
2255 LoadVal->getChain(),
2256 LoadVal->getBasePtr(),
2257 LoadVal->getOffset(),
2259 LoadVal->getMemOperand());
2261 SDValue CastLoad = DAG.getNode(ISD::BITCAST, SL, VT, NewLoad.getValue(0));
2262 DCI.CombineTo(LoadVal, CastLoad, NewLoad.getValue(1), false);
2264 return DAG.getStore(SN->getChain(), SL, NewLoad,
2265 SN->getBasePtr(), SN->getMemOperand());
2268 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2269 DAGCombinerInfo &DCI) const {
2270 EVT VT = N->getValueType(0);
2272 if (VT.isVector() || VT.getSizeInBits() > 32)
2275 SelectionDAG &DAG = DCI.DAG;
2278 SDValue N0 = N->getOperand(0);
2279 SDValue N1 = N->getOperand(1);
2282 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
2283 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
2284 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
2285 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
2286 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
2287 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
2288 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
2289 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
2294 // We need to use sext even for MUL_U24, because MUL_U24 is used
2295 // for signed multiply of 8 and 16-bit types.
2296 return DAG.getSExtOrTrunc(Mul, DL, VT);
2299 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2300 DAGCombinerInfo &DCI) const {
2301 SelectionDAG &DAG = DCI.DAG;
2304 switch(N->getOpcode()) {
2307 return performMulCombine(N, DCI);
2308 case AMDGPUISD::MUL_I24:
2309 case AMDGPUISD::MUL_U24: {
2310 SDValue N0 = N->getOperand(0);
2311 SDValue N1 = N->getOperand(1);
2312 simplifyI24(N0, DCI);
2313 simplifyI24(N1, DCI);
2317 SDValue Cond = N->getOperand(0);
2318 if (Cond.getOpcode() == ISD::SETCC && Cond.hasOneUse()) {
2320 EVT VT = N->getValueType(0);
2321 SDValue LHS = Cond.getOperand(0);
2322 SDValue RHS = Cond.getOperand(1);
2323 SDValue CC = Cond.getOperand(2);
2325 SDValue True = N->getOperand(1);
2326 SDValue False = N->getOperand(2);
2329 return CombineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
2331 // TODO: Implement min / max Evergreen instructions.
2332 if (VT == MVT::i32 &&
2333 Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
2334 return CombineIMinMax(DL, VT, LHS, RHS, True, False, CC, DAG);
2340 case AMDGPUISD::BFE_I32:
2341 case AMDGPUISD::BFE_U32: {
2342 assert(!N->getValueType(0).isVector() &&
2343 "Vector handling of BFE not implemented");
2344 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
2348 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
2350 return DAG.getConstant(0, MVT::i32);
2352 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
2356 SDValue BitsFrom = N->getOperand(0);
2357 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
2359 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
2361 if (OffsetVal == 0) {
2362 // This is already sign / zero extended, so try to fold away extra BFEs.
2363 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
2365 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
2366 if (OpSignBits >= SignBits)
2369 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
2371 // This is a sign_extend_inreg. Replace it to take advantage of existing
2372 // DAG Combines. If not eliminated, we will match back to BFE during
2375 // TODO: The sext_inreg of extended types ends, although we can could
2376 // handle them in a single BFE.
2377 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
2378 DAG.getValueType(SmallVT));
2381 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
2384 if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
2386 return constantFoldBFE<int32_t>(DAG,
2387 CVal->getSExtValue(),
2392 return constantFoldBFE<uint32_t>(DAG,
2393 CVal->getZExtValue(),
2398 if ((OffsetVal + WidthVal) >= 32) {
2399 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
2400 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
2401 BitsFrom, ShiftVal);
2404 if (BitsFrom.hasOneUse()) {
2405 APInt Demanded = APInt::getBitsSet(32,
2407 OffsetVal + WidthVal);
2409 APInt KnownZero, KnownOne;
2410 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2411 !DCI.isBeforeLegalizeOps());
2412 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2413 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
2414 TLI.SimplifyDemandedBits(BitsFrom, Demanded,
2415 KnownZero, KnownOne, TLO)) {
2416 DCI.CommitTargetLoweringOpt(TLO);
2424 return performStoreCombine(N, DCI);
2429 //===----------------------------------------------------------------------===//
2431 //===----------------------------------------------------------------------===//
2433 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2436 const SmallVectorImpl<ISD::InputArg> &Ins,
2437 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
2439 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
2440 if (Ins[i].ArgVT == Ins[i].VT) {
2441 OrigIns.push_back(Ins[i]);
2446 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
2447 // Vector has been split into scalars.
2448 VT = Ins[i].ArgVT.getVectorElementType();
2449 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
2450 Ins[i].ArgVT.getVectorElementType() !=
2451 Ins[i].VT.getVectorElementType()) {
2452 // Vector elements have been promoted
2455 // Vector has been spilt into smaller vectors.
2459 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
2460 Ins[i].OrigArgIndex, Ins[i].PartOffset);
2461 OrigIns.push_back(Arg);
2465 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
2466 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2467 return CFP->isExactlyValue(1.0);
2469 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2470 return C->isAllOnesValue();
2475 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2476 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2477 return CFP->getValueAPF().isZero();
2479 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2480 return C->isNullValue();
2485 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2486 const TargetRegisterClass *RC,
2487 unsigned Reg, EVT VT) const {
2488 MachineFunction &MF = DAG.getMachineFunction();
2489 MachineRegisterInfo &MRI = MF.getRegInfo();
2490 unsigned VirtualRegister;
2491 if (!MRI.isLiveIn(Reg)) {
2492 VirtualRegister = MRI.createVirtualRegister(RC);
2493 MRI.addLiveIn(Reg, VirtualRegister);
2495 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2497 return DAG.getRegister(VirtualRegister, VT);
2500 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2502 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2504 default: return nullptr;
2506 NODE_NAME_CASE(CALL);
2507 NODE_NAME_CASE(UMUL);
2508 NODE_NAME_CASE(RET_FLAG);
2509 NODE_NAME_CASE(BRANCH_COND);
2512 NODE_NAME_CASE(DWORDADDR)
2513 NODE_NAME_CASE(FRACT)
2514 NODE_NAME_CASE(CLAMP)
2516 NODE_NAME_CASE(FMAX_LEGACY)
2517 NODE_NAME_CASE(SMAX)
2518 NODE_NAME_CASE(UMAX)
2519 NODE_NAME_CASE(FMIN_LEGACY)
2520 NODE_NAME_CASE(SMIN)
2521 NODE_NAME_CASE(UMIN)
2522 NODE_NAME_CASE(FMAX3)
2523 NODE_NAME_CASE(SMAX3)
2524 NODE_NAME_CASE(UMAX3)
2525 NODE_NAME_CASE(FMIN3)
2526 NODE_NAME_CASE(SMIN3)
2527 NODE_NAME_CASE(UMIN3)
2528 NODE_NAME_CASE(URECIP)
2529 NODE_NAME_CASE(DIV_SCALE)
2530 NODE_NAME_CASE(DIV_FMAS)
2531 NODE_NAME_CASE(DIV_FIXUP)
2532 NODE_NAME_CASE(TRIG_PREOP)
2535 NODE_NAME_CASE(RSQ_LEGACY)
2536 NODE_NAME_CASE(RSQ_CLAMPED)
2537 NODE_NAME_CASE(LDEXP)
2538 NODE_NAME_CASE(FP_CLASS)
2539 NODE_NAME_CASE(DOT4)
2540 NODE_NAME_CASE(BFE_U32)
2541 NODE_NAME_CASE(BFE_I32)
2544 NODE_NAME_CASE(BREV)
2545 NODE_NAME_CASE(MUL_U24)
2546 NODE_NAME_CASE(MUL_I24)
2547 NODE_NAME_CASE(MAD_U24)
2548 NODE_NAME_CASE(MAD_I24)
2549 NODE_NAME_CASE(EXPORT)
2550 NODE_NAME_CASE(CONST_ADDRESS)
2551 NODE_NAME_CASE(REGISTER_LOAD)
2552 NODE_NAME_CASE(REGISTER_STORE)
2553 NODE_NAME_CASE(LOAD_CONSTANT)
2554 NODE_NAME_CASE(LOAD_INPUT)
2555 NODE_NAME_CASE(SAMPLE)
2556 NODE_NAME_CASE(SAMPLEB)
2557 NODE_NAME_CASE(SAMPLED)
2558 NODE_NAME_CASE(SAMPLEL)
2559 NODE_NAME_CASE(CVT_F32_UBYTE0)
2560 NODE_NAME_CASE(CVT_F32_UBYTE1)
2561 NODE_NAME_CASE(CVT_F32_UBYTE2)
2562 NODE_NAME_CASE(CVT_F32_UBYTE3)
2563 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2564 NODE_NAME_CASE(CONST_DATA_PTR)
2565 NODE_NAME_CASE(STORE_MSKOR)
2566 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2570 static void computeKnownBitsForMinMax(const SDValue Op0,
2574 const SelectionDAG &DAG,
2576 APInt Op0Zero, Op0One;
2577 APInt Op1Zero, Op1One;
2578 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2579 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2581 KnownZero = Op0Zero & Op1Zero;
2582 KnownOne = Op0One & Op1One;
2585 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2589 const SelectionDAG &DAG,
2590 unsigned Depth) const {
2592 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2596 unsigned Opc = Op.getOpcode();
2601 case ISD::INTRINSIC_WO_CHAIN: {
2602 // FIXME: The intrinsic should just use the node.
2603 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2604 case AMDGPUIntrinsic::AMDGPU_imax:
2605 case AMDGPUIntrinsic::AMDGPU_umax:
2606 case AMDGPUIntrinsic::AMDGPU_imin:
2607 case AMDGPUIntrinsic::AMDGPU_umin:
2608 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2609 KnownZero, KnownOne, DAG, Depth);
2617 case AMDGPUISD::SMAX:
2618 case AMDGPUISD::UMAX:
2619 case AMDGPUISD::SMIN:
2620 case AMDGPUISD::UMIN:
2621 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2622 KnownZero, KnownOne, DAG, Depth);
2625 case AMDGPUISD::BFE_I32:
2626 case AMDGPUISD::BFE_U32: {
2627 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2631 unsigned BitWidth = 32;
2632 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2634 if (Opc == AMDGPUISD::BFE_U32)
2635 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2642 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2644 const SelectionDAG &DAG,
2645 unsigned Depth) const {
2646 switch (Op.getOpcode()) {
2647 case AMDGPUISD::BFE_I32: {
2648 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2652 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2653 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2654 if (!Offset || !Offset->isNullValue())
2657 // TODO: Could probably figure something out with non-0 offsets.
2658 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2659 return std::max(SignBits, Op0SignBits);
2662 case AMDGPUISD::BFE_U32: {
2663 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2664 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;