1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPURegisterInfo.h"
20 #include "AMDGPUSubtarget.h"
21 #include "AMDILIntrinsicInfo.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DiagnosticInfo.h"
32 #include "llvm/IR/DiagnosticPrinter.h"
38 /// Diagnostic information for unimplemented or unsupported feature reporting.
39 class DiagnosticInfoUnsupported : public DiagnosticInfo {
41 const Twine &Description;
46 static int getKindID() {
48 KindID = llvm::getNextAvailablePluginDiagnosticKind();
53 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
54 DiagnosticSeverity Severity = DS_Error)
55 : DiagnosticInfo(getKindID(), Severity),
59 const Function &getFunction() const { return Fn; }
60 const Twine &getDescription() const { return Description; }
62 void print(DiagnosticPrinter &DP) const override {
63 DP << "unsupported " << getDescription() << " in " << Fn.getName();
66 static bool classof(const DiagnosticInfo *DI) {
67 return DI->getKind() == getKindID();
71 int DiagnosticInfoUnsupported::KindID = 0;
75 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
76 CCValAssign::LocInfo LocInfo,
77 ISD::ArgFlagsTy ArgFlags, CCState &State) {
78 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
79 ArgFlags.getOrigAlign());
80 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
85 #include "AMDGPUGenCallingConv.inc"
87 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
88 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
90 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
92 // Initialize target lowering borrowed from AMDIL
95 // We need to custom lower some of the intrinsics
96 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
98 // Library functions. These default to Expand, but we have instructions
100 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
101 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
102 setOperationAction(ISD::FPOW, MVT::f32, Legal);
103 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
104 setOperationAction(ISD::FABS, MVT::f32, Legal);
105 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
106 setOperationAction(ISD::FRINT, MVT::f32, Legal);
107 setOperationAction(ISD::FROUND, MVT::f32, Legal);
108 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
110 // The hardware supports ROTR, but not ROTL
111 setOperationAction(ISD::ROTL, MVT::i32, Expand);
113 // Lower floating point store/load to integer store/load to reduce the number
114 // of patterns in tablegen.
115 setOperationAction(ISD::STORE, MVT::f32, Promote);
116 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
118 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
119 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
121 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
122 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
124 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
125 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
127 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
128 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
130 setOperationAction(ISD::STORE, MVT::f64, Promote);
131 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
133 // Custom lowering of vector stores is required for local address space
135 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
136 // XXX: Native v2i32 local address space stores are possible, but not
137 // currently implemented.
138 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
140 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
141 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
142 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
144 // XXX: This can be change to Custom, once ExpandVectorStores can
145 // handle 64-bit stores.
146 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
148 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
149 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
150 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
153 setOperationAction(ISD::LOAD, MVT::f32, Promote);
154 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
156 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
157 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
159 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
160 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
162 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
163 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
165 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
166 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
168 setOperationAction(ISD::LOAD, MVT::f64, Promote);
169 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
171 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
172 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
173 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
174 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
175 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
176 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
177 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
178 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
179 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
180 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
182 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
183 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
184 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
185 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
186 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
187 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
188 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
189 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
190 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
191 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
192 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
193 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
195 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
197 setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
198 setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
200 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
202 setOperationAction(ISD::MUL, MVT::i64, Expand);
204 setOperationAction(ISD::UDIV, MVT::i32, Expand);
205 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
206 setOperationAction(ISD::UREM, MVT::i32, Expand);
207 setOperationAction(ISD::VSELECT, MVT::v2f32, Expand);
208 setOperationAction(ISD::VSELECT, MVT::v4f32, Expand);
210 static const MVT::SimpleValueType IntTypes[] = {
211 MVT::v2i32, MVT::v4i32
213 const size_t NumIntTypes = array_lengthof(IntTypes);
215 for (unsigned int x = 0; x < NumIntTypes; ++x) {
216 MVT::SimpleValueType VT = IntTypes[x];
217 //Expand the following operations for the current type by default
218 setOperationAction(ISD::ADD, VT, Expand);
219 setOperationAction(ISD::AND, VT, Expand);
220 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
221 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
222 setOperationAction(ISD::MUL, VT, Expand);
223 setOperationAction(ISD::OR, VT, Expand);
224 setOperationAction(ISD::SHL, VT, Expand);
225 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
226 setOperationAction(ISD::SRL, VT, Expand);
227 setOperationAction(ISD::SRA, VT, Expand);
228 setOperationAction(ISD::SUB, VT, Expand);
229 setOperationAction(ISD::UDIV, VT, Expand);
230 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
231 setOperationAction(ISD::UREM, VT, Expand);
232 setOperationAction(ISD::SELECT, VT, Expand);
233 setOperationAction(ISD::VSELECT, VT, Expand);
234 setOperationAction(ISD::XOR, VT, Expand);
237 static const MVT::SimpleValueType FloatTypes[] = {
238 MVT::v2f32, MVT::v4f32
240 const size_t NumFloatTypes = array_lengthof(FloatTypes);
242 for (unsigned int x = 0; x < NumFloatTypes; ++x) {
243 MVT::SimpleValueType VT = FloatTypes[x];
244 setOperationAction(ISD::FABS, VT, Expand);
245 setOperationAction(ISD::FADD, VT, Expand);
246 setOperationAction(ISD::FDIV, VT, Expand);
247 setOperationAction(ISD::FPOW, VT, Expand);
248 setOperationAction(ISD::FFLOOR, VT, Expand);
249 setOperationAction(ISD::FTRUNC, VT, Expand);
250 setOperationAction(ISD::FMUL, VT, Expand);
251 setOperationAction(ISD::FRINT, VT, Expand);
252 setOperationAction(ISD::FSQRT, VT, Expand);
253 setOperationAction(ISD::FSUB, VT, Expand);
254 setOperationAction(ISD::SELECT, VT, Expand);
257 setTargetDAGCombine(ISD::MUL);
260 //===----------------------------------------------------------------------===//
261 // Target Information
262 //===----------------------------------------------------------------------===//
264 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
268 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
270 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
273 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
274 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
276 return ((LScalarSize <= CastScalarSize) ||
277 (CastScalarSize >= 32) ||
281 //===---------------------------------------------------------------------===//
283 //===---------------------------------------------------------------------===//
285 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
286 assert(VT.isFloatingPoint());
287 return VT == MVT::f32;
290 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
291 assert(VT.isFloatingPoint());
292 return VT == MVT::f32;
295 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
296 // Truncate is just accessing a subregister.
297 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
300 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
301 // Truncate is just accessing a subregister.
302 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
303 (Dest->getPrimitiveSizeInBits() % 32 == 0);
306 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
307 const DataLayout *DL = getDataLayout();
308 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
309 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
311 return SrcSize == 32 && DestSize == 64;
314 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
315 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
316 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
317 // this will enable reducing 64-bit operations the 32-bit, which is always
319 return Src == MVT::i32 && Dest == MVT::i64;
322 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
323 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
324 // limited number of native 64-bit operations. Shrinking an operation to fit
325 // in a single 32-bit register should always be helpful. As currently used,
326 // this is much less general than the name suggests, and is only used in
327 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
328 // not profitable, and may actually be harmful.
329 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
332 //===---------------------------------------------------------------------===//
333 // TargetLowering Callbacks
334 //===---------------------------------------------------------------------===//
336 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
337 const SmallVectorImpl<ISD::InputArg> &Ins) const {
339 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
342 SDValue AMDGPUTargetLowering::LowerReturn(
344 CallingConv::ID CallConv,
346 const SmallVectorImpl<ISD::OutputArg> &Outs,
347 const SmallVectorImpl<SDValue> &OutVals,
348 SDLoc DL, SelectionDAG &DAG) const {
349 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
352 //===---------------------------------------------------------------------===//
353 // Target specific lowering
354 //===---------------------------------------------------------------------===//
356 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
357 SmallVectorImpl<SDValue> &InVals) const {
358 SDValue Callee = CLI.Callee;
359 SelectionDAG &DAG = CLI.DAG;
361 const Function &Fn = *DAG.getMachineFunction().getFunction();
363 StringRef FuncName("<unknown>");
365 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
366 FuncName = G->getSymbol();
367 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
368 FuncName = G->getGlobal()->getName();
370 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
371 DAG.getContext()->diagnose(NoCalls);
375 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
377 switch (Op.getOpcode()) {
379 Op.getNode()->dump();
380 llvm_unreachable("Custom lowering code for this"
381 "instruction is not implemented yet!");
383 // AMDIL DAG lowering
384 case ISD::SDIV: return LowerSDIV(Op, DAG);
385 case ISD::SREM: return LowerSREM(Op, DAG);
386 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
387 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
388 // AMDGPU DAG lowering
389 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
390 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
391 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
392 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
393 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
394 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
399 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
400 SmallVectorImpl<SDValue> &Results,
401 SelectionDAG &DAG) const {
402 switch (N->getOpcode()) {
403 case ISD::SIGN_EXTEND_INREG:
404 // Different parts of legalization seem to interpret which type of
405 // sign_extend_inreg is the one to check for custom lowering. The extended
406 // from type is what really matters, but some places check for custom
407 // lowering of the result type. This results in trying to use
408 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
409 // nothing here and let the illegal result integer be handled normally.
417 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
418 const GlobalValue *GV,
419 const SDValue &InitPtr,
421 SelectionDAG &DAG) const {
422 const DataLayout *TD = getTargetMachine().getDataLayout();
424 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
425 EVT VT = EVT::getEVT(CI->getType());
426 PointerType *PtrTy = PointerType::get(CI->getType(), 0);
427 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
428 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
429 TD->getPrefTypeAlignment(CI->getType()));
430 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
431 EVT VT = EVT::getEVT(CFP->getType());
432 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
433 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
434 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
435 TD->getPrefTypeAlignment(CFP->getType()));
436 } else if (Init->getType()->isAggregateType()) {
437 EVT PtrVT = InitPtr.getValueType();
438 unsigned NumElements = Init->getType()->getArrayNumElements();
439 SmallVector<SDValue, 8> Chains;
440 for (unsigned i = 0; i < NumElements; ++i) {
441 SDValue Offset = DAG.getConstant(i * TD->getTypeAllocSize(
442 Init->getType()->getArrayElementType()), PtrVT);
443 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
444 Chains.push_back(LowerConstantInitializer(Init->getAggregateElement(i),
445 GV, Ptr, Chain, DAG));
447 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
450 llvm_unreachable("Unhandled constant initializer");
454 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
456 SelectionDAG &DAG) const {
458 const DataLayout *TD = getTargetMachine().getDataLayout();
459 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
460 const GlobalValue *GV = G->getGlobal();
462 switch (G->getAddressSpace()) {
463 default: llvm_unreachable("Global Address lowering not implemented for this "
465 case AMDGPUAS::LOCAL_ADDRESS: {
466 // XXX: What does the value of G->getOffset() mean?
467 assert(G->getOffset() == 0 &&
468 "Do not know what to do with an non-zero offset");
471 if (MFI->LocalMemoryObjects.count(GV) == 0) {
472 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
473 Offset = MFI->LDSSize;
474 MFI->LocalMemoryObjects[GV] = Offset;
475 // XXX: Account for alignment?
476 MFI->LDSSize += Size;
478 Offset = MFI->LocalMemoryObjects[GV];
481 return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
483 case AMDGPUAS::CONSTANT_ADDRESS: {
484 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
485 Type *EltType = GV->getType()->getElementType();
486 unsigned Size = TD->getTypeAllocSize(EltType);
487 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
489 const GlobalVariable *Var = dyn_cast<GlobalVariable>(GV);
490 const Constant *Init = Var->getInitializer();
491 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
492 SDValue InitPtr = DAG.getFrameIndex(FI,
493 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
494 SmallVector<SDNode*, 8> WorkList;
496 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
497 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
498 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
500 WorkList.push_back(*I);
502 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
503 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
504 E = WorkList.end(); I != E; ++I) {
505 SmallVector<SDValue, 8> Ops;
506 Ops.push_back(Chain);
507 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
508 Ops.push_back((*I)->getOperand(i));
510 DAG.UpdateNodeOperands(*I, Ops.data(), Ops.size());
512 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op),
513 getPointerTy(AMDGPUAS::CONSTANT_ADDRESS));
518 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
519 SelectionDAG &DAG) const {
520 SmallVector<SDValue, 8> Args;
521 SDValue A = Op.getOperand(0);
522 SDValue B = Op.getOperand(1);
524 DAG.ExtractVectorElements(A, Args);
525 DAG.ExtractVectorElements(B, Args);
527 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
530 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
531 SelectionDAG &DAG) const {
533 SmallVector<SDValue, 8> Args;
534 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
535 EVT VT = Op.getValueType();
536 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
537 VT.getVectorNumElements());
539 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
542 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
543 SelectionDAG &DAG) const {
545 MachineFunction &MF = DAG.getMachineFunction();
546 const AMDGPUFrameLowering *TFL =
547 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
549 FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op);
552 unsigned FrameIndex = FIN->getIndex();
553 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
554 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
558 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
559 SelectionDAG &DAG) const {
560 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
562 EVT VT = Op.getValueType();
564 switch (IntrinsicID) {
566 case AMDGPUIntrinsic::AMDIL_abs:
567 return LowerIntrinsicIABS(Op, DAG);
568 case AMDGPUIntrinsic::AMDIL_exp:
569 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
570 case AMDGPUIntrinsic::AMDGPU_lrp:
571 return LowerIntrinsicLRP(Op, DAG);
572 case AMDGPUIntrinsic::AMDIL_fraction:
573 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
574 case AMDGPUIntrinsic::AMDIL_max:
575 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
577 case AMDGPUIntrinsic::AMDGPU_imax:
578 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
580 case AMDGPUIntrinsic::AMDGPU_umax:
581 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
583 case AMDGPUIntrinsic::AMDIL_min:
584 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
586 case AMDGPUIntrinsic::AMDGPU_imin:
587 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
589 case AMDGPUIntrinsic::AMDGPU_umin:
590 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
593 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
594 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
599 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
600 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
605 case AMDGPUIntrinsic::AMDGPU_bfi:
606 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
611 case AMDGPUIntrinsic::AMDGPU_bfm:
612 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
616 case AMDGPUIntrinsic::AMDIL_round_nearest:
617 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
621 ///IABS(a) = SMAX(sub(0, a), a)
622 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
623 SelectionDAG &DAG) const {
626 EVT VT = Op.getValueType();
627 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
630 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
633 /// Linear Interpolation
634 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
635 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
636 SelectionDAG &DAG) const {
638 EVT VT = Op.getValueType();
639 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
640 DAG.getConstantFP(1.0f, MVT::f32),
642 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
644 return DAG.getNode(ISD::FADD, DL, VT,
645 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
649 /// \brief Generate Min/Max node
650 SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
651 SelectionDAG &DAG) const {
653 EVT VT = Op.getValueType();
655 SDValue LHS = Op.getOperand(0);
656 SDValue RHS = Op.getOperand(1);
657 SDValue True = Op.getOperand(2);
658 SDValue False = Op.getOperand(3);
659 SDValue CC = Op.getOperand(4);
661 if (VT != MVT::f32 ||
662 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
666 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
680 llvm_unreachable("Operation should already be optimised!");
688 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
690 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
699 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
701 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
703 case ISD::SETCC_INVALID:
704 llvm_unreachable("Invalid setcc condcode!");
709 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
710 SelectionDAG &DAG) const {
711 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
712 EVT MemEltVT = Load->getMemoryVT().getVectorElementType();
713 EVT EltVT = Op.getValueType().getVectorElementType();
714 EVT PtrVT = Load->getBasePtr().getValueType();
715 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
716 SmallVector<SDValue, 8> Loads;
719 for (unsigned i = 0, e = NumElts; i != e; ++i) {
720 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
721 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), PtrVT));
722 Loads.push_back(DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
723 Load->getChain(), Ptr,
724 MachinePointerInfo(Load->getMemOperand()->getValue()),
725 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
726 Load->getAlignment()));
728 return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(), Loads);
731 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
732 SelectionDAG &DAG) const {
733 StoreSDNode *Store = dyn_cast<StoreSDNode>(Op);
734 EVT MemVT = Store->getMemoryVT();
735 unsigned MemBits = MemVT.getSizeInBits();
737 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
738 // truncating store into an i32 store.
739 // XXX: We could also handle optimize other vector bitwidths.
740 if (!MemVT.isVector() || MemBits > 32) {
745 SDValue Value = Store->getValue();
746 EVT VT = Value.getValueType();
747 EVT ElemVT = VT.getVectorElementType();
748 SDValue Ptr = Store->getBasePtr();
749 EVT MemEltVT = MemVT.getVectorElementType();
750 unsigned MemEltBits = MemEltVT.getSizeInBits();
751 unsigned MemNumElements = MemVT.getVectorNumElements();
752 unsigned PackedSize = MemVT.getStoreSizeInBits();
753 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
755 assert(Value.getValueType().getScalarSizeInBits() >= 32);
758 for (unsigned i = 0; i < MemNumElements; ++i) {
759 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
760 DAG.getConstant(i, MVT::i32));
761 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
762 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
764 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
765 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
770 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
774 if (PackedSize < 32) {
775 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
776 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
777 Store->getMemOperand()->getPointerInfo(),
779 Store->isNonTemporal(), Store->isVolatile(),
780 Store->getAlignment());
783 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
784 Store->getMemOperand()->getPointerInfo(),
785 Store->isVolatile(), Store->isNonTemporal(),
786 Store->getAlignment());
789 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
790 SelectionDAG &DAG) const {
791 StoreSDNode *Store = cast<StoreSDNode>(Op);
792 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
793 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
794 EVT PtrVT = Store->getBasePtr().getValueType();
795 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
798 SmallVector<SDValue, 8> Chains;
800 for (unsigned i = 0, e = NumElts; i != e; ++i) {
801 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
802 Store->getValue(), DAG.getConstant(i, MVT::i32));
803 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT,
805 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
807 Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
808 MachinePointerInfo(Store->getMemOperand()->getValue()),
809 MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
810 Store->getAlignment()));
812 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
815 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
817 LoadSDNode *Load = cast<LoadSDNode>(Op);
818 ISD::LoadExtType ExtType = Load->getExtensionType();
819 EVT VT = Op.getValueType();
820 EVT MemVT = Load->getMemoryVT();
822 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
823 // We can do the extload to 32-bits, and then need to separately extend to
826 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
830 Load->getMemOperand());
831 return DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32);
834 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
835 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
836 // FIXME: Copied from PPC
837 // First, load into 32 bits, then truncate to 1 bit.
839 SDValue Chain = Load->getChain();
840 SDValue BasePtr = Load->getBasePtr();
841 MachineMemOperand *MMO = Load->getMemOperand();
843 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
844 BasePtr, MVT::i8, MMO);
845 return DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
848 // Lower loads constant address space global variable loads
849 if (Load->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
851 GetUnderlyingObject(Load->getMemOperand()->getValue()))) {
853 SDValue Ptr = DAG.getZExtOrTrunc(Load->getBasePtr(), DL,
854 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
855 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
856 DAG.getConstant(2, MVT::i32));
857 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
858 Load->getChain(), Ptr,
859 DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2));
862 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
863 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
867 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
868 DAG.getConstant(2, MVT::i32));
869 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
870 Load->getChain(), Ptr,
871 DAG.getTargetConstant(0, MVT::i32),
873 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
875 DAG.getConstant(0x3, MVT::i32));
876 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
877 DAG.getConstant(3, MVT::i32));
879 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
881 EVT MemEltVT = MemVT.getScalarType();
882 if (ExtType == ISD::SEXTLOAD) {
883 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
884 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
887 return DAG.getZeroExtendInReg(Ret, DL, MemEltVT);
890 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
892 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
893 if (Result.getNode()) {
897 StoreSDNode *Store = cast<StoreSDNode>(Op);
898 SDValue Chain = Store->getChain();
899 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
900 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
901 Store->getValue().getValueType().isVector()) {
902 return SplitVectorStore(Op, DAG);
905 EVT MemVT = Store->getMemoryVT();
906 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
907 MemVT.bitsLT(MVT::i32)) {
909 if (Store->getMemoryVT() == MVT::i8) {
911 } else if (Store->getMemoryVT() == MVT::i16) {
914 SDValue BasePtr = Store->getBasePtr();
915 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
916 DAG.getConstant(2, MVT::i32));
917 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
918 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
920 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
921 DAG.getConstant(0x3, MVT::i32));
923 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
924 DAG.getConstant(3, MVT::i32));
926 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
929 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
931 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
932 MaskedValue, ShiftAmt);
934 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
936 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
937 DAG.getConstant(0xffffffff, MVT::i32));
938 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
940 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
941 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
942 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
947 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
948 SelectionDAG &DAG) const {
950 EVT VT = Op.getValueType();
952 SDValue Num = Op.getOperand(0);
953 SDValue Den = Op.getOperand(1);
955 SmallVector<SDValue, 8> Results;
957 // RCP = URECIP(Den) = 2^32 / Den + e
958 // e is rounding error.
959 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
961 // RCP_LO = umulo(RCP, Den) */
962 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
964 // RCP_HI = mulhu (RCP, Den) */
965 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
967 // NEG_RCP_LO = -RCP_LO
968 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
971 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
972 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
975 // Calculate the rounding error from the URECIP instruction
976 // E = mulhu(ABS_RCP_LO, RCP)
977 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
980 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
983 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
985 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
986 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
989 // Quotient = mulhu(Tmp0, Num)
990 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
992 // Num_S_Remainder = Quotient * Den
993 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
995 // Remainder = Num - Num_S_Remainder
996 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
998 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
999 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1000 DAG.getConstant(-1, VT),
1001 DAG.getConstant(0, VT),
1003 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1004 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1006 DAG.getConstant(-1, VT),
1007 DAG.getConstant(0, VT),
1009 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1010 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1013 // Calculate Division result:
1015 // Quotient_A_One = Quotient + 1
1016 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1017 DAG.getConstant(1, VT));
1019 // Quotient_S_One = Quotient - 1
1020 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1021 DAG.getConstant(1, VT));
1023 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1024 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1025 Quotient, Quotient_A_One, ISD::SETEQ);
1027 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1028 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1029 Quotient_S_One, Div, ISD::SETEQ);
1031 // Calculate Rem result:
1033 // Remainder_S_Den = Remainder - Den
1034 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1036 // Remainder_A_Den = Remainder + Den
1037 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1039 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1040 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1041 Remainder, Remainder_S_Den, ISD::SETEQ);
1043 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1044 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1045 Remainder_A_Den, Rem, ISD::SETEQ);
1050 return DAG.getMergeValues(Ops, DL);
1053 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1054 SelectionDAG &DAG) const {
1055 SDValue S0 = Op.getOperand(0);
1057 if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64)
1060 // f32 uint_to_fp i64
1061 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1062 DAG.getConstant(0, MVT::i32));
1063 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1064 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1065 DAG.getConstant(1, MVT::i32));
1066 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1067 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1068 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1069 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1073 SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
1075 SelectionDAG &DAG) const {
1076 MVT VT = Op.getSimpleValueType();
1078 SDValue Shift = DAG.getConstant(BitsDiff, VT);
1079 // Shift left by 'Shift' bits.
1080 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
1081 // Signed shift Right by 'Shift' bits.
1082 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
1085 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1086 SelectionDAG &DAG) const {
1087 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1088 MVT VT = Op.getSimpleValueType();
1089 MVT ScalarVT = VT.getScalarType();
1094 SDValue Src = Op.getOperand(0);
1097 // TODO: Don't scalarize on Evergreen?
1098 unsigned NElts = VT.getVectorNumElements();
1099 SmallVector<SDValue, 8> Args;
1100 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1102 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1103 for (unsigned I = 0; I < NElts; ++I)
1104 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1106 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1109 //===----------------------------------------------------------------------===//
1110 // Custom DAG optimizations
1111 //===----------------------------------------------------------------------===//
1113 static bool isU24(SDValue Op, SelectionDAG &DAG) {
1114 APInt KnownZero, KnownOne;
1115 EVT VT = Op.getValueType();
1116 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne);
1118 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1121 static bool isI24(SDValue Op, SelectionDAG &DAG) {
1122 EVT VT = Op.getValueType();
1124 // In order for this to be a signed 24-bit value, bit 23, must
1126 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1127 // as unsigned 24-bit values.
1128 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1131 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
1133 SelectionDAG &DAG = DCI.DAG;
1134 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1135 EVT VT = Op.getValueType();
1137 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
1138 APInt KnownZero, KnownOne;
1139 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
1140 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
1141 DCI.CommitTargetLoweringOpt(TLO);
1144 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
1145 DAGCombinerInfo &DCI) const {
1146 SelectionDAG &DAG = DCI.DAG;
1149 switch(N->getOpcode()) {
1152 EVT VT = N->getValueType(0);
1153 SDValue N0 = N->getOperand(0);
1154 SDValue N1 = N->getOperand(1);
1157 // FIXME: Add support for 24-bit multiply with 64-bit output on SI.
1158 if (VT.isVector() || VT.getSizeInBits() > 32)
1161 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
1162 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
1163 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
1164 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
1165 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
1166 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
1167 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
1168 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
1173 // We need to use sext even for MUL_U24, because MUL_U24 is used
1174 // for signed multiply of 8 and 16-bit types.
1175 SDValue Reg = DAG.getSExtOrTrunc(Mul, DL, VT);
1179 case AMDGPUISD::MUL_I24:
1180 case AMDGPUISD::MUL_U24: {
1181 SDValue N0 = N->getOperand(0);
1182 SDValue N1 = N->getOperand(1);
1183 simplifyI24(N0, DCI);
1184 simplifyI24(N1, DCI);
1191 //===----------------------------------------------------------------------===//
1193 //===----------------------------------------------------------------------===//
1195 void AMDGPUTargetLowering::getOriginalFunctionArgs(
1198 const SmallVectorImpl<ISD::InputArg> &Ins,
1199 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
1201 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1202 if (Ins[i].ArgVT == Ins[i].VT) {
1203 OrigIns.push_back(Ins[i]);
1208 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
1209 // Vector has been split into scalars.
1210 VT = Ins[i].ArgVT.getVectorElementType();
1211 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
1212 Ins[i].ArgVT.getVectorElementType() !=
1213 Ins[i].VT.getVectorElementType()) {
1214 // Vector elements have been promoted
1217 // Vector has been spilt into smaller vectors.
1221 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
1222 Ins[i].OrigArgIndex, Ins[i].PartOffset);
1223 OrigIns.push_back(Arg);
1227 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
1228 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
1229 return CFP->isExactlyValue(1.0);
1231 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
1232 return C->isAllOnesValue();
1237 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
1238 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
1239 return CFP->getValueAPF().isZero();
1241 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
1242 return C->isNullValue();
1247 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1248 const TargetRegisterClass *RC,
1249 unsigned Reg, EVT VT) const {
1250 MachineFunction &MF = DAG.getMachineFunction();
1251 MachineRegisterInfo &MRI = MF.getRegInfo();
1252 unsigned VirtualRegister;
1253 if (!MRI.isLiveIn(Reg)) {
1254 VirtualRegister = MRI.createVirtualRegister(RC);
1255 MRI.addLiveIn(Reg, VirtualRegister);
1257 VirtualRegister = MRI.getLiveInVirtReg(Reg);
1259 return DAG.getRegister(VirtualRegister, VT);
1262 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
1264 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
1266 default: return nullptr;
1268 NODE_NAME_CASE(CALL);
1269 NODE_NAME_CASE(UMUL);
1270 NODE_NAME_CASE(DIV_INF);
1271 NODE_NAME_CASE(RET_FLAG);
1272 NODE_NAME_CASE(BRANCH_COND);
1275 NODE_NAME_CASE(DWORDADDR)
1276 NODE_NAME_CASE(FRACT)
1277 NODE_NAME_CASE(FMAX)
1278 NODE_NAME_CASE(SMAX)
1279 NODE_NAME_CASE(UMAX)
1280 NODE_NAME_CASE(FMIN)
1281 NODE_NAME_CASE(SMIN)
1282 NODE_NAME_CASE(UMIN)
1283 NODE_NAME_CASE(BFE_U32)
1284 NODE_NAME_CASE(BFE_I32)
1287 NODE_NAME_CASE(MUL_U24)
1288 NODE_NAME_CASE(MUL_I24)
1289 NODE_NAME_CASE(URECIP)
1290 NODE_NAME_CASE(DOT4)
1291 NODE_NAME_CASE(EXPORT)
1292 NODE_NAME_CASE(CONST_ADDRESS)
1293 NODE_NAME_CASE(REGISTER_LOAD)
1294 NODE_NAME_CASE(REGISTER_STORE)
1295 NODE_NAME_CASE(LOAD_CONSTANT)
1296 NODE_NAME_CASE(LOAD_INPUT)
1297 NODE_NAME_CASE(SAMPLE)
1298 NODE_NAME_CASE(SAMPLEB)
1299 NODE_NAME_CASE(SAMPLED)
1300 NODE_NAME_CASE(SAMPLEL)
1301 NODE_NAME_CASE(STORE_MSKOR)
1302 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
1306 static void computeMaskedBitsForMinMax(const SDValue Op0,
1310 const SelectionDAG &DAG,
1312 APInt Op0Zero, Op0One;
1313 APInt Op1Zero, Op1One;
1314 DAG.ComputeMaskedBits(Op0, Op0Zero, Op0One, Depth);
1315 DAG.ComputeMaskedBits(Op1, Op1Zero, Op1One, Depth);
1317 KnownZero = Op0Zero & Op1Zero;
1318 KnownOne = Op0One & Op1One;
1321 void AMDGPUTargetLowering::computeMaskedBitsForTargetNode(
1325 const SelectionDAG &DAG,
1326 unsigned Depth) const {
1328 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
1329 unsigned Opc = Op.getOpcode();
1331 case ISD::INTRINSIC_WO_CHAIN: {
1332 // FIXME: The intrinsic should just use the node.
1333 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
1334 case AMDGPUIntrinsic::AMDGPU_imax:
1335 case AMDGPUIntrinsic::AMDGPU_umax:
1336 case AMDGPUIntrinsic::AMDGPU_imin:
1337 case AMDGPUIntrinsic::AMDGPU_umin:
1338 computeMaskedBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
1339 KnownZero, KnownOne, DAG, Depth);
1347 case AMDGPUISD::SMAX:
1348 case AMDGPUISD::UMAX:
1349 case AMDGPUISD::SMIN:
1350 case AMDGPUISD::UMIN:
1351 computeMaskedBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
1352 KnownZero, KnownOne, DAG, Depth);