1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPURegisterInfo.h"
19 #include "AMDGPUSubtarget.h"
20 #include "AMDILIntrinsicInfo.h"
21 #include "R600MachineFunctionInfo.h"
22 #include "SIMachineFunctionInfo.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/DataLayout.h"
32 #include "AMDGPUGenCallingConv.inc"
34 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
35 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
37 // Initialize target lowering borrowed from AMDIL
40 // We need to custom lower some of the intrinsics
41 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
43 // Library functions. These default to Expand, but we have instructions
45 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
46 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
47 setOperationAction(ISD::FPOW, MVT::f32, Legal);
48 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
49 setOperationAction(ISD::FABS, MVT::f32, Legal);
50 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
51 setOperationAction(ISD::FRINT, MVT::f32, Legal);
53 // The hardware supports ROTR, but not ROTL
54 setOperationAction(ISD::ROTL, MVT::i32, Expand);
56 // Lower floating point store/load to integer store/load to reduce the number
57 // of patterns in tablegen.
58 setOperationAction(ISD::STORE, MVT::f32, Promote);
59 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
61 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
62 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
64 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
65 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
67 setOperationAction(ISD::STORE, MVT::f64, Promote);
68 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
70 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
71 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
72 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
73 // XXX: This can be change to Custom, once ExpandVectorStores can
74 // handle 64-bit stores.
75 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
77 setOperationAction(ISD::LOAD, MVT::f32, Promote);
78 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
80 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
81 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
83 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
84 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
86 setOperationAction(ISD::LOAD, MVT::f64, Promote);
87 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
89 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
90 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
91 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
92 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
94 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
95 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
96 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
97 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
98 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
99 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
100 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
101 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
102 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
103 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
104 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
105 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
107 setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
108 setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
110 setOperationAction(ISD::MUL, MVT::i64, Expand);
112 setOperationAction(ISD::UDIV, MVT::i32, Expand);
113 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
114 setOperationAction(ISD::UREM, MVT::i32, Expand);
115 setOperationAction(ISD::VSELECT, MVT::v2f32, Expand);
116 setOperationAction(ISD::VSELECT, MVT::v4f32, Expand);
118 static const MVT::SimpleValueType IntTypes[] = {
119 MVT::v2i32, MVT::v4i32
121 const size_t NumIntTypes = array_lengthof(IntTypes);
123 for (unsigned int x = 0; x < NumIntTypes; ++x) {
124 MVT::SimpleValueType VT = IntTypes[x];
125 //Expand the following operations for the current type by default
126 setOperationAction(ISD::ADD, VT, Expand);
127 setOperationAction(ISD::AND, VT, Expand);
128 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
129 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
130 setOperationAction(ISD::MUL, VT, Expand);
131 setOperationAction(ISD::OR, VT, Expand);
132 setOperationAction(ISD::SHL, VT, Expand);
133 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
134 setOperationAction(ISD::SRL, VT, Expand);
135 setOperationAction(ISD::SRA, VT, Expand);
136 setOperationAction(ISD::SUB, VT, Expand);
137 setOperationAction(ISD::UDIV, VT, Expand);
138 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
139 setOperationAction(ISD::UREM, VT, Expand);
140 setOperationAction(ISD::VSELECT, VT, Expand);
141 setOperationAction(ISD::XOR, VT, Expand);
144 static const MVT::SimpleValueType FloatTypes[] = {
145 MVT::v2f32, MVT::v4f32
147 const size_t NumFloatTypes = array_lengthof(FloatTypes);
149 for (unsigned int x = 0; x < NumFloatTypes; ++x) {
150 MVT::SimpleValueType VT = FloatTypes[x];
151 setOperationAction(ISD::FADD, VT, Expand);
152 setOperationAction(ISD::FDIV, VT, Expand);
153 setOperationAction(ISD::FFLOOR, VT, Expand);
154 setOperationAction(ISD::FMUL, VT, Expand);
155 setOperationAction(ISD::FRINT, VT, Expand);
156 setOperationAction(ISD::FSUB, VT, Expand);
160 //===----------------------------------------------------------------------===//
161 // Target Information
162 //===----------------------------------------------------------------------===//
164 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
169 //===---------------------------------------------------------------------===//
171 //===---------------------------------------------------------------------===//
173 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
174 assert(VT.isFloatingPoint());
175 return VT == MVT::f32;
178 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
179 assert(VT.isFloatingPoint());
180 return VT == MVT::f32;
183 //===---------------------------------------------------------------------===//
184 // TargetLowering Callbacks
185 //===---------------------------------------------------------------------===//
187 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
188 const SmallVectorImpl<ISD::InputArg> &Ins) const {
190 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
193 SDValue AMDGPUTargetLowering::LowerReturn(
195 CallingConv::ID CallConv,
197 const SmallVectorImpl<ISD::OutputArg> &Outs,
198 const SmallVectorImpl<SDValue> &OutVals,
199 SDLoc DL, SelectionDAG &DAG) const {
200 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
203 //===---------------------------------------------------------------------===//
204 // Target specific lowering
205 //===---------------------------------------------------------------------===//
207 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
209 switch (Op.getOpcode()) {
211 Op.getNode()->dump();
212 assert(0 && "Custom lowering code for this"
213 "instruction is not implemented yet!");
215 // AMDIL DAG lowering
216 case ISD::SDIV: return LowerSDIV(Op, DAG);
217 case ISD::SREM: return LowerSREM(Op, DAG);
218 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
219 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
220 // AMDGPU DAG lowering
221 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
222 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
223 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
224 case ISD::STORE: return LowerVectorStore(Op, DAG);
225 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
230 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
232 SelectionDAG &DAG) const {
234 const DataLayout *TD = getTargetMachine().getDataLayout();
235 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
237 assert(G->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS);
238 // XXX: What does the value of G->getOffset() mean?
239 assert(G->getOffset() == 0 &&
240 "Do not know what to do with an non-zero offset");
242 unsigned Offset = MFI->LDSSize;
243 const GlobalValue *GV = G->getGlobal();
244 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
246 // XXX: Account for alignment?
247 MFI->LDSSize += Size;
249 return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
252 void AMDGPUTargetLowering::ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
253 SmallVectorImpl<SDValue> &Args,
255 unsigned Count) const {
256 EVT VT = Op.getValueType();
257 for (unsigned i = Start, e = Start + Count; i != e; ++i) {
258 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
259 VT.getVectorElementType(),
260 Op, DAG.getConstant(i, MVT::i32)));
264 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
265 SelectionDAG &DAG) const {
266 SmallVector<SDValue, 8> Args;
267 SDValue A = Op.getOperand(0);
268 SDValue B = Op.getOperand(1);
270 ExtractVectorElements(A, DAG, Args, 0,
271 A.getValueType().getVectorNumElements());
272 ExtractVectorElements(B, DAG, Args, 0,
273 B.getValueType().getVectorNumElements());
275 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
276 &Args[0], Args.size());
279 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
280 SelectionDAG &DAG) const {
282 SmallVector<SDValue, 8> Args;
283 EVT VT = Op.getValueType();
284 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
285 ExtractVectorElements(Op.getOperand(0), DAG, Args, Start,
286 VT.getVectorNumElements());
288 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
289 &Args[0], Args.size());
293 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
294 SelectionDAG &DAG) const {
295 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
297 EVT VT = Op.getValueType();
299 switch (IntrinsicID) {
301 case AMDGPUIntrinsic::AMDIL_abs:
302 return LowerIntrinsicIABS(Op, DAG);
303 case AMDGPUIntrinsic::AMDIL_exp:
304 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
305 case AMDGPUIntrinsic::AMDGPU_lrp:
306 return LowerIntrinsicLRP(Op, DAG);
307 case AMDGPUIntrinsic::AMDIL_fraction:
308 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
309 case AMDGPUIntrinsic::AMDIL_max:
310 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
312 case AMDGPUIntrinsic::AMDGPU_imax:
313 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
315 case AMDGPUIntrinsic::AMDGPU_umax:
316 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
318 case AMDGPUIntrinsic::AMDIL_min:
319 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
321 case AMDGPUIntrinsic::AMDGPU_imin:
322 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
324 case AMDGPUIntrinsic::AMDGPU_umin:
325 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
327 case AMDGPUIntrinsic::AMDIL_round_nearest:
328 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
332 ///IABS(a) = SMAX(sub(0, a), a)
333 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
334 SelectionDAG &DAG) const {
337 EVT VT = Op.getValueType();
338 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
341 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
344 /// Linear Interpolation
345 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
346 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
347 SelectionDAG &DAG) const {
349 EVT VT = Op.getValueType();
350 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
351 DAG.getConstantFP(1.0f, MVT::f32),
353 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
355 return DAG.getNode(ISD::FADD, DL, VT,
356 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
360 /// \brief Generate Min/Max node
361 SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
362 SelectionDAG &DAG) const {
364 EVT VT = Op.getValueType();
366 SDValue LHS = Op.getOperand(0);
367 SDValue RHS = Op.getOperand(1);
368 SDValue True = Op.getOperand(2);
369 SDValue False = Op.getOperand(3);
370 SDValue CC = Op.getOperand(4);
372 if (VT != MVT::f32 ||
373 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
377 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
391 assert(0 && "Operation should already be optimised !");
399 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
401 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
410 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
412 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
414 case ISD::SETCC_INVALID:
415 assert(0 && "Invalid setcc condcode !");
422 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
423 SelectionDAG &DAG) const {
425 EVT VT = Op.getValueType();
427 SDValue Num = Op.getOperand(0);
428 SDValue Den = Op.getOperand(1);
430 SmallVector<SDValue, 8> Results;
432 // RCP = URECIP(Den) = 2^32 / Den + e
433 // e is rounding error.
434 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
436 // RCP_LO = umulo(RCP, Den) */
437 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
439 // RCP_HI = mulhu (RCP, Den) */
440 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
442 // NEG_RCP_LO = -RCP_LO
443 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
446 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
447 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
450 // Calculate the rounding error from the URECIP instruction
451 // E = mulhu(ABS_RCP_LO, RCP)
452 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
455 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
458 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
460 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
461 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
464 // Quotient = mulhu(Tmp0, Num)
465 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
467 // Num_S_Remainder = Quotient * Den
468 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
470 // Remainder = Num - Num_S_Remainder
471 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
473 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
474 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
475 DAG.getConstant(-1, VT),
476 DAG.getConstant(0, VT),
478 // Remainder_GE_Zero = (Remainder >= 0 ? -1 : 0)
479 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Remainder,
480 DAG.getConstant(0, VT),
481 DAG.getConstant(-1, VT),
482 DAG.getConstant(0, VT),
484 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
485 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
488 // Calculate Division result:
490 // Quotient_A_One = Quotient + 1
491 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
492 DAG.getConstant(1, VT));
494 // Quotient_S_One = Quotient - 1
495 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
496 DAG.getConstant(1, VT));
498 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
499 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
500 Quotient, Quotient_A_One, ISD::SETEQ);
502 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
503 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
504 Quotient_S_One, Div, ISD::SETEQ);
506 // Calculate Rem result:
508 // Remainder_S_Den = Remainder - Den
509 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
511 // Remainder_A_Den = Remainder + Den
512 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
514 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
515 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
516 Remainder, Remainder_S_Den, ISD::SETEQ);
518 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
519 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
520 Remainder_A_Den, Rem, ISD::SETEQ);
524 return DAG.getMergeValues(Ops, 2, DL);
527 SDValue AMDGPUTargetLowering::LowerVectorStore(const SDValue &Op,
528 SelectionDAG &DAG) const {
529 StoreSDNode *Store = dyn_cast<StoreSDNode>(Op);
530 EVT MemVT = Store->getMemoryVT();
531 unsigned MemBits = MemVT.getSizeInBits();
533 // Byte stores are really expensive, so if possible, try to pack
534 // 32-bit vector truncatating store into an i32 store.
535 // XXX: We could also handle optimize other vector bitwidths
536 if (!MemVT.isVector() || MemBits > 32) {
541 const SDValue &Value = Store->getValue();
542 EVT VT = Value.getValueType();
543 const SDValue &Ptr = Store->getBasePtr();
544 EVT MemEltVT = MemVT.getVectorElementType();
545 unsigned MemEltBits = MemEltVT.getSizeInBits();
546 unsigned MemNumElements = MemVT.getVectorNumElements();
547 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), MemVT.getSizeInBits());
551 Mask = DAG.getConstant(0xFF, PackedVT);
554 Mask = DAG.getConstant(0xFFFF, PackedVT);
557 llvm_unreachable("Cannot lower this vector store");
560 for (unsigned i = 0; i < MemNumElements; ++i) {
561 EVT ElemVT = VT.getVectorElementType();
562 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
563 DAG.getConstant(i, MVT::i32));
564 Elt = DAG.getZExtOrTrunc(Elt, DL, PackedVT);
565 Elt = DAG.getNode(ISD::AND, DL, PackedVT, Elt, Mask);
566 SDValue Shift = DAG.getConstant(MemEltBits * i, PackedVT);
567 Elt = DAG.getNode(ISD::SHL, DL, PackedVT, Elt, Shift);
571 PackedValue = DAG.getNode(ISD::OR, DL, PackedVT, PackedValue, Elt);
574 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
575 MachinePointerInfo(Store->getMemOperand()->getValue()),
576 Store->isVolatile(), Store->isNonTemporal(),
577 Store->getAlignment());
580 //===----------------------------------------------------------------------===//
582 //===----------------------------------------------------------------------===//
584 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
585 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
586 return CFP->isExactlyValue(1.0);
588 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
589 return C->isAllOnesValue();
594 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
595 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
596 return CFP->getValueAPF().isZero();
598 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
599 return C->isNullValue();
604 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
605 const TargetRegisterClass *RC,
606 unsigned Reg, EVT VT) const {
607 MachineFunction &MF = DAG.getMachineFunction();
608 MachineRegisterInfo &MRI = MF.getRegInfo();
609 unsigned VirtualRegister;
610 if (!MRI.isLiveIn(Reg)) {
611 VirtualRegister = MRI.createVirtualRegister(RC);
612 MRI.addLiveIn(Reg, VirtualRegister);
614 VirtualRegister = MRI.getLiveInVirtReg(Reg);
616 return DAG.getRegister(VirtualRegister, VT);
619 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
621 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
625 NODE_NAME_CASE(CALL);
626 NODE_NAME_CASE(UMUL);
627 NODE_NAME_CASE(DIV_INF);
628 NODE_NAME_CASE(RET_FLAG);
629 NODE_NAME_CASE(BRANCH_COND);
632 NODE_NAME_CASE(DWORDADDR)
633 NODE_NAME_CASE(FRACT)
640 NODE_NAME_CASE(URECIP)
641 NODE_NAME_CASE(EXPORT)
642 NODE_NAME_CASE(CONST_ADDRESS)
643 NODE_NAME_CASE(REGISTER_LOAD)
644 NODE_NAME_CASE(REGISTER_STORE)
645 NODE_NAME_CASE(LOAD_CONSTANT)
646 NODE_NAME_CASE(LOAD_INPUT)
647 NODE_NAME_CASE(SAMPLE)
648 NODE_NAME_CASE(SAMPLEB)
649 NODE_NAME_CASE(SAMPLED)
650 NODE_NAME_CASE(SAMPLEL)
651 NODE_NAME_CASE(STORE_MSKOR)