1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPURegisterInfo.h"
19 #include "AMDGPUSubtarget.h"
20 #include "AMDILIntrinsicInfo.h"
21 #include "SIMachineFunctionInfo.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/IR/DataLayout.h"
31 #include "AMDGPUGenCallingConv.inc"
33 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
34 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
36 // Initialize target lowering borrowed from AMDIL
39 // We need to custom lower some of the intrinsics
40 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
42 // Library functions. These default to Expand, but we have instructions
44 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
45 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
46 setOperationAction(ISD::FPOW, MVT::f32, Legal);
47 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
48 setOperationAction(ISD::FABS, MVT::f32, Legal);
49 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
50 setOperationAction(ISD::FRINT, MVT::f32, Legal);
52 // The hardware supports ROTR, but not ROTL
53 setOperationAction(ISD::ROTL, MVT::i32, Expand);
55 // Lower floating point store/load to integer store/load to reduce the number
56 // of patterns in tablegen.
57 setOperationAction(ISD::STORE, MVT::f32, Promote);
58 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
60 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
61 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
63 setOperationAction(ISD::LOAD, MVT::f32, Promote);
64 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
66 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
67 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
69 setOperationAction(ISD::MUL, MVT::i64, Expand);
71 setOperationAction(ISD::UDIV, MVT::i32, Expand);
72 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
73 setOperationAction(ISD::UREM, MVT::i32, Expand);
75 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
81 size_t NumTypes = sizeof(types) / sizeof(*types);
83 for (unsigned int x = 0; x < NumTypes; ++x) {
84 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
85 //Expand the following operations for the current type by default
86 setOperationAction(ISD::ADD, VT, Expand);
87 setOperationAction(ISD::AND, VT, Expand);
88 setOperationAction(ISD::MUL, VT, Expand);
89 setOperationAction(ISD::OR, VT, Expand);
90 setOperationAction(ISD::SHL, VT, Expand);
91 setOperationAction(ISD::SRL, VT, Expand);
92 setOperationAction(ISD::SRA, VT, Expand);
93 setOperationAction(ISD::SUB, VT, Expand);
94 setOperationAction(ISD::UDIV, VT, Expand);
95 setOperationAction(ISD::UREM, VT, Expand);
96 setOperationAction(ISD::XOR, VT, Expand);
100 //===---------------------------------------------------------------------===//
101 // TargetLowering Callbacks
102 //===---------------------------------------------------------------------===//
104 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
105 const SmallVectorImpl<ISD::InputArg> &Ins) const {
107 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
110 SDValue AMDGPUTargetLowering::LowerReturn(
112 CallingConv::ID CallConv,
114 const SmallVectorImpl<ISD::OutputArg> &Outs,
115 const SmallVectorImpl<SDValue> &OutVals,
116 SDLoc DL, SelectionDAG &DAG) const {
117 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
120 //===---------------------------------------------------------------------===//
121 // Target specific lowering
122 //===---------------------------------------------------------------------===//
124 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
126 switch (Op.getOpcode()) {
128 Op.getNode()->dump();
129 assert(0 && "Custom lowering code for this"
130 "instruction is not implemented yet!");
132 // AMDIL DAG lowering
133 case ISD::SDIV: return LowerSDIV(Op, DAG);
134 case ISD::SREM: return LowerSREM(Op, DAG);
135 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
136 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
137 // AMDGPU DAG lowering
138 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
139 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
144 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
146 SelectionDAG &DAG) const {
148 const DataLayout *TD = getTargetMachine().getDataLayout();
149 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
150 // XXX: What does the value of G->getOffset() mean?
151 assert(G->getOffset() == 0 &&
152 "Do not know what to do with an non-zero offset");
154 unsigned Offset = MFI->LDSSize;
155 const GlobalValue *GV = G->getGlobal();
156 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
158 // XXX: Account for alignment?
159 MFI->LDSSize += Size;
161 return DAG.getConstant(Offset, MVT::i32);
164 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
165 SelectionDAG &DAG) const {
166 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
168 EVT VT = Op.getValueType();
170 switch (IntrinsicID) {
172 case AMDGPUIntrinsic::AMDIL_abs:
173 return LowerIntrinsicIABS(Op, DAG);
174 case AMDGPUIntrinsic::AMDIL_exp:
175 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
176 case AMDGPUIntrinsic::AMDGPU_lrp:
177 return LowerIntrinsicLRP(Op, DAG);
178 case AMDGPUIntrinsic::AMDIL_fraction:
179 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
180 case AMDGPUIntrinsic::AMDIL_max:
181 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
183 case AMDGPUIntrinsic::AMDGPU_imax:
184 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
186 case AMDGPUIntrinsic::AMDGPU_umax:
187 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
189 case AMDGPUIntrinsic::AMDIL_min:
190 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
192 case AMDGPUIntrinsic::AMDGPU_imin:
193 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
195 case AMDGPUIntrinsic::AMDGPU_umin:
196 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
198 case AMDGPUIntrinsic::AMDIL_round_nearest:
199 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
203 ///IABS(a) = SMAX(sub(0, a), a)
204 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
205 SelectionDAG &DAG) const {
208 EVT VT = Op.getValueType();
209 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
212 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
215 /// Linear Interpolation
216 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
217 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
218 SelectionDAG &DAG) const {
220 EVT VT = Op.getValueType();
221 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
222 DAG.getConstantFP(1.0f, MVT::f32),
224 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
226 return DAG.getNode(ISD::FADD, DL, VT,
227 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
231 /// \brief Generate Min/Max node
232 SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
233 SelectionDAG &DAG) const {
235 EVT VT = Op.getValueType();
237 SDValue LHS = Op.getOperand(0);
238 SDValue RHS = Op.getOperand(1);
239 SDValue True = Op.getOperand(2);
240 SDValue False = Op.getOperand(3);
241 SDValue CC = Op.getOperand(4);
243 if (VT != MVT::f32 ||
244 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
248 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
262 assert(0 && "Operation should already be optimised !");
270 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
272 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
281 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
283 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
285 case ISD::SETCC_INVALID:
286 assert(0 && "Invalid setcc condcode !");
293 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
294 SelectionDAG &DAG) const {
296 EVT VT = Op.getValueType();
298 SDValue Num = Op.getOperand(0);
299 SDValue Den = Op.getOperand(1);
301 SmallVector<SDValue, 8> Results;
303 // RCP = URECIP(Den) = 2^32 / Den + e
304 // e is rounding error.
305 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
307 // RCP_LO = umulo(RCP, Den) */
308 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
310 // RCP_HI = mulhu (RCP, Den) */
311 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
313 // NEG_RCP_LO = -RCP_LO
314 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
317 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
318 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
321 // Calculate the rounding error from the URECIP instruction
322 // E = mulhu(ABS_RCP_LO, RCP)
323 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
326 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
329 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
331 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
332 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
335 // Quotient = mulhu(Tmp0, Num)
336 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
338 // Num_S_Remainder = Quotient * Den
339 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
341 // Remainder = Num - Num_S_Remainder
342 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
344 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
345 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
346 DAG.getConstant(-1, VT),
347 DAG.getConstant(0, VT),
349 // Remainder_GE_Zero = (Remainder >= 0 ? -1 : 0)
350 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Remainder,
351 DAG.getConstant(0, VT),
352 DAG.getConstant(-1, VT),
353 DAG.getConstant(0, VT),
355 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
356 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
359 // Calculate Division result:
361 // Quotient_A_One = Quotient + 1
362 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
363 DAG.getConstant(1, VT));
365 // Quotient_S_One = Quotient - 1
366 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
367 DAG.getConstant(1, VT));
369 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
370 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
371 Quotient, Quotient_A_One, ISD::SETEQ);
373 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
374 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
375 Quotient_S_One, Div, ISD::SETEQ);
377 // Calculate Rem result:
379 // Remainder_S_Den = Remainder - Den
380 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
382 // Remainder_A_Den = Remainder + Den
383 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
385 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
386 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
387 Remainder, Remainder_S_Den, ISD::SETEQ);
389 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
390 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
391 Remainder_A_Den, Rem, ISD::SETEQ);
395 return DAG.getMergeValues(Ops, 2, DL);
398 //===----------------------------------------------------------------------===//
400 //===----------------------------------------------------------------------===//
402 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
403 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
404 return CFP->isExactlyValue(1.0);
406 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
407 return C->isAllOnesValue();
412 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
413 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
414 return CFP->getValueAPF().isZero();
416 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
417 return C->isNullValue();
422 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
423 const TargetRegisterClass *RC,
424 unsigned Reg, EVT VT) const {
425 MachineFunction &MF = DAG.getMachineFunction();
426 MachineRegisterInfo &MRI = MF.getRegInfo();
427 unsigned VirtualRegister;
428 if (!MRI.isLiveIn(Reg)) {
429 VirtualRegister = MRI.createVirtualRegister(RC);
430 MRI.addLiveIn(Reg, VirtualRegister);
432 VirtualRegister = MRI.getLiveInVirtReg(Reg);
434 return DAG.getRegister(VirtualRegister, VT);
437 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
439 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
443 NODE_NAME_CASE(CALL);
444 NODE_NAME_CASE(UMUL);
445 NODE_NAME_CASE(DIV_INF);
446 NODE_NAME_CASE(RET_FLAG);
447 NODE_NAME_CASE(BRANCH_COND);
450 NODE_NAME_CASE(DWORDADDR)
451 NODE_NAME_CASE(FRACT)
458 NODE_NAME_CASE(URECIP)
459 NODE_NAME_CASE(EXPORT)
460 NODE_NAME_CASE(CONST_ADDRESS)
461 NODE_NAME_CASE(REGISTER_LOAD)
462 NODE_NAME_CASE(REGISTER_STORE)