1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPURegisterInfo.h"
19 #include "AMDGPUSubtarget.h"
20 #include "AMDILIntrinsicInfo.h"
21 #include "R600MachineFunctionInfo.h"
22 #include "SIMachineFunctionInfo.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/DataLayout.h"
32 #include "AMDGPUGenCallingConv.inc"
34 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
35 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
37 // Initialize target lowering borrowed from AMDIL
40 // We need to custom lower some of the intrinsics
41 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
43 // Library functions. These default to Expand, but we have instructions
45 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
46 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
47 setOperationAction(ISD::FPOW, MVT::f32, Legal);
48 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
49 setOperationAction(ISD::FABS, MVT::f32, Legal);
50 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
51 setOperationAction(ISD::FRINT, MVT::f32, Legal);
53 // The hardware supports ROTR, but not ROTL
54 setOperationAction(ISD::ROTL, MVT::i32, Expand);
56 // Lower floating point store/load to integer store/load to reduce the number
57 // of patterns in tablegen.
58 setOperationAction(ISD::STORE, MVT::f32, Promote);
59 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
61 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
62 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
64 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
65 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
67 setOperationAction(ISD::STORE, MVT::f64, Promote);
68 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
70 setOperationAction(ISD::LOAD, MVT::f32, Promote);
71 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
73 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
74 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
76 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
77 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
79 setOperationAction(ISD::LOAD, MVT::f64, Promote);
80 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
82 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
83 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
84 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
85 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
87 setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
88 setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
90 setOperationAction(ISD::MUL, MVT::i64, Expand);
92 setOperationAction(ISD::UDIV, MVT::i32, Expand);
93 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
94 setOperationAction(ISD::UREM, MVT::i32, Expand);
95 setOperationAction(ISD::VSELECT, MVT::v2f32, Expand);
96 setOperationAction(ISD::VSELECT, MVT::v4f32, Expand);
98 static const int types[] = {
102 const size_t NumTypes = array_lengthof(types);
104 for (unsigned int x = 0; x < NumTypes; ++x) {
105 MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
106 //Expand the following operations for the current type by default
107 setOperationAction(ISD::ADD, VT, Expand);
108 setOperationAction(ISD::AND, VT, Expand);
109 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
110 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
111 setOperationAction(ISD::MUL, VT, Expand);
112 setOperationAction(ISD::OR, VT, Expand);
113 setOperationAction(ISD::SHL, VT, Expand);
114 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
115 setOperationAction(ISD::SRL, VT, Expand);
116 setOperationAction(ISD::SRA, VT, Expand);
117 setOperationAction(ISD::SUB, VT, Expand);
118 setOperationAction(ISD::UDIV, VT, Expand);
119 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
120 setOperationAction(ISD::UREM, VT, Expand);
121 setOperationAction(ISD::VSELECT, VT, Expand);
122 setOperationAction(ISD::XOR, VT, Expand);
126 //===----------------------------------------------------------------------===//
127 // Target Information
128 //===----------------------------------------------------------------------===//
130 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
135 //===---------------------------------------------------------------------===//
137 //===---------------------------------------------------------------------===//
139 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
140 assert(VT.isFloatingPoint());
141 return VT == MVT::f32;
144 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
145 assert(VT.isFloatingPoint());
146 return VT == MVT::f32;
149 //===---------------------------------------------------------------------===//
150 // TargetLowering Callbacks
151 //===---------------------------------------------------------------------===//
153 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
154 const SmallVectorImpl<ISD::InputArg> &Ins) const {
156 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
159 SDValue AMDGPUTargetLowering::LowerReturn(
161 CallingConv::ID CallConv,
163 const SmallVectorImpl<ISD::OutputArg> &Outs,
164 const SmallVectorImpl<SDValue> &OutVals,
165 SDLoc DL, SelectionDAG &DAG) const {
166 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
169 //===---------------------------------------------------------------------===//
170 // Target specific lowering
171 //===---------------------------------------------------------------------===//
173 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
175 switch (Op.getOpcode()) {
177 Op.getNode()->dump();
178 assert(0 && "Custom lowering code for this"
179 "instruction is not implemented yet!");
181 // AMDIL DAG lowering
182 case ISD::SDIV: return LowerSDIV(Op, DAG);
183 case ISD::SREM: return LowerSREM(Op, DAG);
184 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
185 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
186 // AMDGPU DAG lowering
187 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
188 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
189 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
190 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
195 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
197 SelectionDAG &DAG) const {
199 const DataLayout *TD = getTargetMachine().getDataLayout();
200 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
201 // XXX: What does the value of G->getOffset() mean?
202 assert(G->getOffset() == 0 &&
203 "Do not know what to do with an non-zero offset");
205 unsigned Offset = MFI->LDSSize;
206 const GlobalValue *GV = G->getGlobal();
207 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
209 // XXX: Account for alignment?
210 MFI->LDSSize += Size;
212 return DAG.getConstant(Offset, TD->getPointerSize() == 8 ? MVT::i64 : MVT::i32);
215 void AMDGPUTargetLowering::ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
216 SmallVectorImpl<SDValue> &Args,
218 unsigned Count) const {
219 EVT VT = Op.getValueType();
220 for (unsigned i = Start, e = Start + Count; i != e; ++i) {
221 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
222 VT.getVectorElementType(),
223 Op, DAG.getConstant(i, MVT::i32)));
227 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
228 SelectionDAG &DAG) const {
229 SmallVector<SDValue, 8> Args;
230 SDValue A = Op.getOperand(0);
231 SDValue B = Op.getOperand(1);
233 ExtractVectorElements(A, DAG, Args, 0,
234 A.getValueType().getVectorNumElements());
235 ExtractVectorElements(B, DAG, Args, 0,
236 B.getValueType().getVectorNumElements());
238 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
239 &Args[0], Args.size());
242 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
243 SelectionDAG &DAG) const {
245 SmallVector<SDValue, 8> Args;
246 EVT VT = Op.getValueType();
247 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
248 ExtractVectorElements(Op.getOperand(0), DAG, Args, Start,
249 VT.getVectorNumElements());
251 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
252 &Args[0], Args.size());
256 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
257 SelectionDAG &DAG) const {
258 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
260 EVT VT = Op.getValueType();
262 switch (IntrinsicID) {
264 case AMDGPUIntrinsic::AMDIL_abs:
265 return LowerIntrinsicIABS(Op, DAG);
266 case AMDGPUIntrinsic::AMDIL_exp:
267 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
268 case AMDGPUIntrinsic::AMDGPU_lrp:
269 return LowerIntrinsicLRP(Op, DAG);
270 case AMDGPUIntrinsic::AMDIL_fraction:
271 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
272 case AMDGPUIntrinsic::AMDIL_max:
273 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
275 case AMDGPUIntrinsic::AMDGPU_imax:
276 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
278 case AMDGPUIntrinsic::AMDGPU_umax:
279 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
281 case AMDGPUIntrinsic::AMDIL_min:
282 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, Op.getOperand(1),
284 case AMDGPUIntrinsic::AMDGPU_imin:
285 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
287 case AMDGPUIntrinsic::AMDGPU_umin:
288 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
290 case AMDGPUIntrinsic::AMDIL_round_nearest:
291 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
295 ///IABS(a) = SMAX(sub(0, a), a)
296 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
297 SelectionDAG &DAG) const {
300 EVT VT = Op.getValueType();
301 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
304 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
307 /// Linear Interpolation
308 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
309 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
310 SelectionDAG &DAG) const {
312 EVT VT = Op.getValueType();
313 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
314 DAG.getConstantFP(1.0f, MVT::f32),
316 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
318 return DAG.getNode(ISD::FADD, DL, VT,
319 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
323 /// \brief Generate Min/Max node
324 SDValue AMDGPUTargetLowering::LowerMinMax(SDValue Op,
325 SelectionDAG &DAG) const {
327 EVT VT = Op.getValueType();
329 SDValue LHS = Op.getOperand(0);
330 SDValue RHS = Op.getOperand(1);
331 SDValue True = Op.getOperand(2);
332 SDValue False = Op.getOperand(3);
333 SDValue CC = Op.getOperand(4);
335 if (VT != MVT::f32 ||
336 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
340 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
354 assert(0 && "Operation should already be optimised !");
362 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
364 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
373 return DAG.getNode(AMDGPUISD::FMAX, DL, VT, LHS, RHS);
375 return DAG.getNode(AMDGPUISD::FMIN, DL, VT, LHS, RHS);
377 case ISD::SETCC_INVALID:
378 assert(0 && "Invalid setcc condcode !");
385 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
386 SelectionDAG &DAG) const {
388 EVT VT = Op.getValueType();
390 SDValue Num = Op.getOperand(0);
391 SDValue Den = Op.getOperand(1);
393 SmallVector<SDValue, 8> Results;
395 // RCP = URECIP(Den) = 2^32 / Den + e
396 // e is rounding error.
397 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
399 // RCP_LO = umulo(RCP, Den) */
400 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
402 // RCP_HI = mulhu (RCP, Den) */
403 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
405 // NEG_RCP_LO = -RCP_LO
406 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
409 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
410 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
413 // Calculate the rounding error from the URECIP instruction
414 // E = mulhu(ABS_RCP_LO, RCP)
415 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
418 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
421 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
423 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
424 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
427 // Quotient = mulhu(Tmp0, Num)
428 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
430 // Num_S_Remainder = Quotient * Den
431 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
433 // Remainder = Num - Num_S_Remainder
434 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
436 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
437 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
438 DAG.getConstant(-1, VT),
439 DAG.getConstant(0, VT),
441 // Remainder_GE_Zero = (Remainder >= 0 ? -1 : 0)
442 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Remainder,
443 DAG.getConstant(0, VT),
444 DAG.getConstant(-1, VT),
445 DAG.getConstant(0, VT),
447 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
448 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
451 // Calculate Division result:
453 // Quotient_A_One = Quotient + 1
454 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
455 DAG.getConstant(1, VT));
457 // Quotient_S_One = Quotient - 1
458 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
459 DAG.getConstant(1, VT));
461 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
462 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
463 Quotient, Quotient_A_One, ISD::SETEQ);
465 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
466 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
467 Quotient_S_One, Div, ISD::SETEQ);
469 // Calculate Rem result:
471 // Remainder_S_Den = Remainder - Den
472 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
474 // Remainder_A_Den = Remainder + Den
475 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
477 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
478 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
479 Remainder, Remainder_S_Den, ISD::SETEQ);
481 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
482 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
483 Remainder_A_Den, Rem, ISD::SETEQ);
487 return DAG.getMergeValues(Ops, 2, DL);
490 //===----------------------------------------------------------------------===//
492 //===----------------------------------------------------------------------===//
494 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
495 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
496 return CFP->isExactlyValue(1.0);
498 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
499 return C->isAllOnesValue();
504 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
505 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
506 return CFP->getValueAPF().isZero();
508 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
509 return C->isNullValue();
514 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
515 const TargetRegisterClass *RC,
516 unsigned Reg, EVT VT) const {
517 MachineFunction &MF = DAG.getMachineFunction();
518 MachineRegisterInfo &MRI = MF.getRegInfo();
519 unsigned VirtualRegister;
520 if (!MRI.isLiveIn(Reg)) {
521 VirtualRegister = MRI.createVirtualRegister(RC);
522 MRI.addLiveIn(Reg, VirtualRegister);
524 VirtualRegister = MRI.getLiveInVirtReg(Reg);
526 return DAG.getRegister(VirtualRegister, VT);
529 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
531 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
535 NODE_NAME_CASE(CALL);
536 NODE_NAME_CASE(UMUL);
537 NODE_NAME_CASE(DIV_INF);
538 NODE_NAME_CASE(RET_FLAG);
539 NODE_NAME_CASE(BRANCH_COND);
542 NODE_NAME_CASE(DWORDADDR)
543 NODE_NAME_CASE(FRACT)
550 NODE_NAME_CASE(URECIP)
551 NODE_NAME_CASE(EXPORT)
552 NODE_NAME_CASE(CONST_ADDRESS)
553 NODE_NAME_CASE(REGISTER_LOAD)
554 NODE_NAME_CASE(REGISTER_STORE)
555 NODE_NAME_CASE(LOAD_CONSTANT)
556 NODE_NAME_CASE(LOAD_INPUT)
557 NODE_NAME_CASE(SAMPLE)
558 NODE_NAME_CASE(SAMPLEB)
559 NODE_NAME_CASE(SAMPLED)
560 NODE_NAME_CASE(SAMPLEL)
561 NODE_NAME_CASE(STORE_MSKOR)