1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPUIntrinsicInfo.h"
20 #include "AMDGPURegisterInfo.h"
21 #include "AMDGPUSubtarget.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DiagnosticInfo.h"
32 #include "llvm/IR/DiagnosticPrinter.h"
38 /// Diagnostic information for unimplemented or unsupported feature reporting.
39 class DiagnosticInfoUnsupported : public DiagnosticInfo {
41 const Twine &Description;
46 static int getKindID() {
48 KindID = llvm::getNextAvailablePluginDiagnosticKind();
53 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
54 DiagnosticSeverity Severity = DS_Error)
55 : DiagnosticInfo(getKindID(), Severity),
59 const Function &getFunction() const { return Fn; }
60 const Twine &getDescription() const { return Description; }
62 void print(DiagnosticPrinter &DP) const override {
63 DP << "unsupported " << getDescription() << " in " << Fn.getName();
66 static bool classof(const DiagnosticInfo *DI) {
67 return DI->getKind() == getKindID();
71 int DiagnosticInfoUnsupported::KindID = 0;
75 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
76 CCValAssign::LocInfo LocInfo,
77 ISD::ArgFlagsTy ArgFlags, CCState &State) {
78 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
79 ArgFlags.getOrigAlign());
80 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
85 #include "AMDGPUGenCallingConv.inc"
87 // Find a larger type to do a load / store of a vector with.
88 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
89 unsigned StoreSize = VT.getStoreSizeInBits();
91 return EVT::getIntegerVT(Ctx, StoreSize);
93 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
94 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
97 // Type for a vector that will be loaded to.
98 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
99 unsigned StoreSize = VT.getStoreSizeInBits();
101 return EVT::getIntegerVT(Ctx, 32);
103 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
106 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
107 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
109 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
111 setOperationAction(ISD::Constant, MVT::i32, Legal);
112 setOperationAction(ISD::Constant, MVT::i64, Legal);
113 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
114 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
116 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
117 setOperationAction(ISD::BRIND, MVT::Other, Expand);
119 // We need to custom lower some of the intrinsics
120 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
122 // Library functions. These default to Expand, but we have instructions
124 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
125 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
126 setOperationAction(ISD::FPOW, MVT::f32, Legal);
127 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
128 setOperationAction(ISD::FABS, MVT::f32, Legal);
129 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
130 setOperationAction(ISD::FRINT, MVT::f32, Legal);
131 setOperationAction(ISD::FROUND, MVT::f32, Legal);
132 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
134 // Lower floating point store/load to integer store/load to reduce the number
135 // of patterns in tablegen.
136 setOperationAction(ISD::STORE, MVT::f32, Promote);
137 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
139 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
140 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
142 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
143 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
145 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
146 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
148 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
149 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
151 setOperationAction(ISD::STORE, MVT::f64, Promote);
152 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
154 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
155 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
157 // Custom lowering of vector stores is required for local address space
159 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
160 // XXX: Native v2i32 local address space stores are possible, but not
161 // currently implemented.
162 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
164 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
165 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
166 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
168 // XXX: This can be change to Custom, once ExpandVectorStores can
169 // handle 64-bit stores.
170 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
172 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
173 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
174 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
175 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
176 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
179 setOperationAction(ISD::LOAD, MVT::f32, Promote);
180 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
182 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
183 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
185 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
186 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
188 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
189 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
191 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
192 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
194 setOperationAction(ISD::LOAD, MVT::f64, Promote);
195 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
197 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
198 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
200 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
201 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
202 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
203 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
204 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
205 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
206 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
207 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
208 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
209 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
211 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
212 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
213 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
214 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
215 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
216 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
217 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
218 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
219 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
220 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
221 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
222 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
224 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
226 if (Subtarget->getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
227 setOperationAction(ISD::FCEIL, MVT::f64, Custom);
228 setOperationAction(ISD::FTRUNC, MVT::f64, Custom);
229 setOperationAction(ISD::FRINT, MVT::f64, Custom);
230 setOperationAction(ISD::FFLOOR, MVT::f64, Custom);
233 if (!Subtarget->hasBFI()) {
234 // fcopysign can be done in a single instruction with BFI.
235 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
236 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
239 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
240 for (MVT VT : ScalarIntVTs) {
241 setOperationAction(ISD::SREM, VT, Expand);
242 setOperationAction(ISD::SDIV, VT, Expand);
244 // GPU does not have divrem function for signed or unsigned.
245 setOperationAction(ISD::SDIVREM, VT, Custom);
246 setOperationAction(ISD::UDIVREM, VT, Custom);
248 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
249 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
250 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
252 setOperationAction(ISD::BSWAP, VT, Expand);
253 setOperationAction(ISD::CTTZ, VT, Expand);
254 setOperationAction(ISD::CTLZ, VT, Expand);
257 if (!Subtarget->hasBCNT(32))
258 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
260 if (!Subtarget->hasBCNT(64))
261 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
263 // The hardware supports 32-bit ROTR, but not ROTL.
264 setOperationAction(ISD::ROTL, MVT::i32, Expand);
265 setOperationAction(ISD::ROTL, MVT::i64, Expand);
266 setOperationAction(ISD::ROTR, MVT::i64, Expand);
268 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand);
269 setOperationAction(ISD::MUL, MVT::i64, Expand);
270 setOperationAction(ISD::MULHU, MVT::i64, Expand);
271 setOperationAction(ISD::MULHS, MVT::i64, Expand);
272 setOperationAction(ISD::UDIV, MVT::i32, Expand);
273 setOperationAction(ISD::UREM, MVT::i32, Expand);
274 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
275 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
277 static const MVT::SimpleValueType VectorIntTypes[] = {
278 MVT::v2i32, MVT::v4i32
281 for (MVT VT : VectorIntTypes) {
282 // Expand the following operations for the current type by default.
283 setOperationAction(ISD::ADD, VT, Expand);
284 setOperationAction(ISD::AND, VT, Expand);
285 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
286 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
287 setOperationAction(ISD::MUL, VT, Expand);
288 setOperationAction(ISD::OR, VT, Expand);
289 setOperationAction(ISD::SHL, VT, Expand);
290 setOperationAction(ISD::SRA, VT, Expand);
291 setOperationAction(ISD::SRL, VT, Expand);
292 setOperationAction(ISD::ROTL, VT, Expand);
293 setOperationAction(ISD::ROTR, VT, Expand);
294 setOperationAction(ISD::SUB, VT, Expand);
295 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
296 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
297 // TODO: Implement custom UREM / SREM routines.
298 setOperationAction(ISD::SDIV, VT, Expand);
299 setOperationAction(ISD::UDIV, VT, Expand);
300 setOperationAction(ISD::SREM, VT, Expand);
301 setOperationAction(ISD::UREM, VT, Expand);
302 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
303 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
304 setOperationAction(ISD::SDIVREM, VT, Custom);
305 setOperationAction(ISD::UDIVREM, VT, Custom);
306 setOperationAction(ISD::ADDC, VT, Expand);
307 setOperationAction(ISD::SUBC, VT, Expand);
308 setOperationAction(ISD::ADDE, VT, Expand);
309 setOperationAction(ISD::SUBE, VT, Expand);
310 setOperationAction(ISD::SELECT, VT, Expand);
311 setOperationAction(ISD::VSELECT, VT, Expand);
312 setOperationAction(ISD::SELECT_CC, VT, Expand);
313 setOperationAction(ISD::XOR, VT, Expand);
314 setOperationAction(ISD::BSWAP, VT, Expand);
315 setOperationAction(ISD::CTPOP, VT, Expand);
316 setOperationAction(ISD::CTTZ, VT, Expand);
317 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
318 setOperationAction(ISD::CTLZ, VT, Expand);
319 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
320 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
323 static const MVT::SimpleValueType FloatVectorTypes[] = {
324 MVT::v2f32, MVT::v4f32
327 for (MVT VT : FloatVectorTypes) {
328 setOperationAction(ISD::FABS, VT, Expand);
329 setOperationAction(ISD::FADD, VT, Expand);
330 setOperationAction(ISD::FCEIL, VT, Expand);
331 setOperationAction(ISD::FCOS, VT, Expand);
332 setOperationAction(ISD::FDIV, VT, Expand);
333 setOperationAction(ISD::FEXP2, VT, Expand);
334 setOperationAction(ISD::FLOG2, VT, Expand);
335 setOperationAction(ISD::FPOW, VT, Expand);
336 setOperationAction(ISD::FFLOOR, VT, Expand);
337 setOperationAction(ISD::FTRUNC, VT, Expand);
338 setOperationAction(ISD::FMUL, VT, Expand);
339 setOperationAction(ISD::FRINT, VT, Expand);
340 setOperationAction(ISD::FNEARBYINT, VT, Expand);
341 setOperationAction(ISD::FSQRT, VT, Expand);
342 setOperationAction(ISD::FSIN, VT, Expand);
343 setOperationAction(ISD::FSUB, VT, Expand);
344 setOperationAction(ISD::FNEG, VT, Expand);
345 setOperationAction(ISD::SELECT, VT, Expand);
346 setOperationAction(ISD::VSELECT, VT, Expand);
347 setOperationAction(ISD::SELECT_CC, VT, Expand);
348 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
349 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
352 setOperationAction(ISD::FNEARBYINT, MVT::f32, Custom);
353 setOperationAction(ISD::FNEARBYINT, MVT::f64, Custom);
355 setTargetDAGCombine(ISD::MUL);
356 setTargetDAGCombine(ISD::SELECT_CC);
358 setSchedulingPreference(Sched::RegPressure);
359 setJumpIsExpensive(true);
361 setSelectIsExpensive(false);
362 PredictableSelectIsExpensive = false;
364 // There are no integer divide instructions, and these expand to a pretty
365 // large sequence of instructions.
366 setIntDivIsCheap(false);
367 setPow2DivIsCheap(false);
369 // TODO: Investigate this when 64-bit divides are implemented.
370 addBypassSlowDiv(64, 32);
372 // FIXME: Need to really handle these.
373 MaxStoresPerMemcpy = 4096;
374 MaxStoresPerMemmove = 4096;
375 MaxStoresPerMemset = 4096;
378 //===----------------------------------------------------------------------===//
379 // Target Information
380 //===----------------------------------------------------------------------===//
382 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
386 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
390 // The backend supports 32 and 64 bit floating point immediates.
391 // FIXME: Why are we reporting vectors of FP immediates as legal?
392 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
393 EVT ScalarVT = VT.getScalarType();
394 return (ScalarVT == MVT::f32 || ScalarVT == MVT::f64);
397 // We don't want to shrink f64 / f32 constants.
398 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
399 EVT ScalarVT = VT.getScalarType();
400 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
403 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
405 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
408 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
409 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
411 return ((LScalarSize <= CastScalarSize) ||
412 (CastScalarSize >= 32) ||
416 //===---------------------------------------------------------------------===//
418 //===---------------------------------------------------------------------===//
420 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
421 assert(VT.isFloatingPoint());
422 return VT == MVT::f32;
425 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
426 assert(VT.isFloatingPoint());
427 return VT == MVT::f32;
430 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
431 // Truncate is just accessing a subregister.
432 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
435 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
436 // Truncate is just accessing a subregister.
437 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
438 (Dest->getPrimitiveSizeInBits() % 32 == 0);
441 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
442 const DataLayout *DL = getDataLayout();
443 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
444 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
446 return SrcSize == 32 && DestSize == 64;
449 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
450 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
451 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
452 // this will enable reducing 64-bit operations the 32-bit, which is always
454 return Src == MVT::i32 && Dest == MVT::i64;
457 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
458 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
459 // limited number of native 64-bit operations. Shrinking an operation to fit
460 // in a single 32-bit register should always be helpful. As currently used,
461 // this is much less general than the name suggests, and is only used in
462 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
463 // not profitable, and may actually be harmful.
464 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
467 //===---------------------------------------------------------------------===//
468 // TargetLowering Callbacks
469 //===---------------------------------------------------------------------===//
471 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
472 const SmallVectorImpl<ISD::InputArg> &Ins) const {
474 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
477 SDValue AMDGPUTargetLowering::LowerReturn(
479 CallingConv::ID CallConv,
481 const SmallVectorImpl<ISD::OutputArg> &Outs,
482 const SmallVectorImpl<SDValue> &OutVals,
483 SDLoc DL, SelectionDAG &DAG) const {
484 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
487 //===---------------------------------------------------------------------===//
488 // Target specific lowering
489 //===---------------------------------------------------------------------===//
491 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
492 SmallVectorImpl<SDValue> &InVals) const {
493 SDValue Callee = CLI.Callee;
494 SelectionDAG &DAG = CLI.DAG;
496 const Function &Fn = *DAG.getMachineFunction().getFunction();
498 StringRef FuncName("<unknown>");
500 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
501 FuncName = G->getSymbol();
502 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
503 FuncName = G->getGlobal()->getName();
505 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
506 DAG.getContext()->diagnose(NoCalls);
510 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
511 SelectionDAG &DAG) const {
512 switch (Op.getOpcode()) {
514 Op.getNode()->dump();
515 llvm_unreachable("Custom lowering code for this"
516 "instruction is not implemented yet!");
518 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
519 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
520 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
521 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
522 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
523 case ISD::SDIV: return LowerSDIV(Op, DAG);
524 case ISD::SREM: return LowerSREM(Op, DAG);
525 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
526 case ISD::SDIVREM: return LowerSDIVREM(Op, DAG);
527 case ISD::FCEIL: return LowerFCEIL(Op, DAG);
528 case ISD::FTRUNC: return LowerFTRUNC(Op, DAG);
529 case ISD::FRINT: return LowerFRINT(Op, DAG);
530 case ISD::FNEARBYINT: return LowerFNEARBYINT(Op, DAG);
531 case ISD::FFLOOR: return LowerFFLOOR(Op, DAG);
532 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
537 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
538 SmallVectorImpl<SDValue> &Results,
539 SelectionDAG &DAG) const {
540 switch (N->getOpcode()) {
541 case ISD::SIGN_EXTEND_INREG:
542 // Different parts of legalization seem to interpret which type of
543 // sign_extend_inreg is the one to check for custom lowering. The extended
544 // from type is what really matters, but some places check for custom
545 // lowering of the result type. This results in trying to use
546 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
547 // nothing here and let the illegal result integer be handled normally.
554 // FIXME: This implements accesses to initialized globals in the constant
555 // address space by copying them to private and accessing that. It does not
556 // properly handle illegal types or vectors. The private vector loads are not
557 // scalarized, and the illegal scalars hit an assertion. This technique will not
558 // work well with large initializers, and this should eventually be
559 // removed. Initialized globals should be placed into a data section that the
560 // runtime will load into a buffer before the kernel is executed. Uses of the
561 // global need to be replaced with a pointer loaded from an implicit kernel
562 // argument into this buffer holding the copy of the data, which will remove the
563 // need for any of this.
564 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
565 const GlobalValue *GV,
566 const SDValue &InitPtr,
568 SelectionDAG &DAG) const {
569 const DataLayout *TD = getTargetMachine().getDataLayout();
571 Type *InitTy = Init->getType();
573 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
574 EVT VT = EVT::getEVT(InitTy);
575 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
576 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
577 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
578 TD->getPrefTypeAlignment(InitTy));
581 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
582 EVT VT = EVT::getEVT(CFP->getType());
583 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
584 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
585 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
586 TD->getPrefTypeAlignment(CFP->getType()));
589 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
590 const StructLayout *SL = TD->getStructLayout(ST);
592 EVT PtrVT = InitPtr.getValueType();
593 SmallVector<SDValue, 8> Chains;
595 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
596 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
597 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
599 Constant *Elt = Init->getAggregateElement(I);
600 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
603 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
606 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
607 EVT PtrVT = InitPtr.getValueType();
609 unsigned NumElements;
610 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
611 NumElements = AT->getNumElements();
612 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
613 NumElements = VT->getNumElements();
615 llvm_unreachable("Unexpected type");
617 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
618 SmallVector<SDValue, 8> Chains;
619 for (unsigned i = 0; i < NumElements; ++i) {
620 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
621 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
623 Constant *Elt = Init->getAggregateElement(i);
624 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
627 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
630 if (isa<UndefValue>(Init)) {
631 EVT VT = EVT::getEVT(InitTy);
632 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
633 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
634 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
635 TD->getPrefTypeAlignment(InitTy));
639 llvm_unreachable("Unhandled constant initializer");
642 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
644 SelectionDAG &DAG) const {
646 const DataLayout *TD = getTargetMachine().getDataLayout();
647 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
648 const GlobalValue *GV = G->getGlobal();
650 switch (G->getAddressSpace()) {
651 default: llvm_unreachable("Global Address lowering not implemented for this "
653 case AMDGPUAS::LOCAL_ADDRESS: {
654 // XXX: What does the value of G->getOffset() mean?
655 assert(G->getOffset() == 0 &&
656 "Do not know what to do with an non-zero offset");
659 if (MFI->LocalMemoryObjects.count(GV) == 0) {
660 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
661 Offset = MFI->LDSSize;
662 MFI->LocalMemoryObjects[GV] = Offset;
663 // XXX: Account for alignment?
664 MFI->LDSSize += Size;
666 Offset = MFI->LocalMemoryObjects[GV];
669 return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
671 case AMDGPUAS::CONSTANT_ADDRESS: {
672 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
673 Type *EltType = GV->getType()->getElementType();
674 unsigned Size = TD->getTypeAllocSize(EltType);
675 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
677 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
678 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
680 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
681 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
683 const GlobalVariable *Var = cast<GlobalVariable>(GV);
684 if (!Var->hasInitializer()) {
685 // This has no use, but bugpoint will hit it.
686 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
689 const Constant *Init = Var->getInitializer();
690 SmallVector<SDNode*, 8> WorkList;
692 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
693 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
694 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
696 WorkList.push_back(*I);
698 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
699 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
700 E = WorkList.end(); I != E; ++I) {
701 SmallVector<SDValue, 8> Ops;
702 Ops.push_back(Chain);
703 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
704 Ops.push_back((*I)->getOperand(i));
706 DAG.UpdateNodeOperands(*I, Ops);
708 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
713 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
714 SelectionDAG &DAG) const {
715 SmallVector<SDValue, 8> Args;
716 SDValue A = Op.getOperand(0);
717 SDValue B = Op.getOperand(1);
719 DAG.ExtractVectorElements(A, Args);
720 DAG.ExtractVectorElements(B, Args);
722 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
725 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
726 SelectionDAG &DAG) const {
728 SmallVector<SDValue, 8> Args;
729 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
730 EVT VT = Op.getValueType();
731 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
732 VT.getVectorNumElements());
734 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
737 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
738 SelectionDAG &DAG) const {
740 MachineFunction &MF = DAG.getMachineFunction();
741 const AMDGPUFrameLowering *TFL =
742 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
744 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
746 unsigned FrameIndex = FIN->getIndex();
747 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
748 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
752 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
753 SelectionDAG &DAG) const {
754 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
756 EVT VT = Op.getValueType();
758 switch (IntrinsicID) {
760 case AMDGPUIntrinsic::AMDGPU_abs:
761 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
762 return LowerIntrinsicIABS(Op, DAG);
763 case AMDGPUIntrinsic::AMDGPU_lrp:
764 return LowerIntrinsicLRP(Op, DAG);
765 case AMDGPUIntrinsic::AMDGPU_fract:
766 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
767 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
769 case AMDGPUIntrinsic::AMDGPU_clamp:
770 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
771 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
772 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
774 case Intrinsic::AMDGPU_div_scale: {
775 // 3rd parameter required to be a constant.
776 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
778 return DAG.getUNDEF(VT);
780 // Translate to the operands expected by the machine instruction. The
781 // first parameter must be the same as the first instruction.
782 SDValue Numerator = Op.getOperand(1);
783 SDValue Denominator = Op.getOperand(2);
784 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
786 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, VT,
787 Src0, Denominator, Numerator);
790 case Intrinsic::AMDGPU_div_fmas:
791 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
792 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
794 case Intrinsic::AMDGPU_div_fixup:
795 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
796 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
798 case Intrinsic::AMDGPU_trig_preop:
799 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
800 Op.getOperand(1), Op.getOperand(2));
802 case Intrinsic::AMDGPU_rcp:
803 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
805 case Intrinsic::AMDGPU_rsq:
806 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
808 case AMDGPUIntrinsic::AMDGPU_imax:
809 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
811 case AMDGPUIntrinsic::AMDGPU_umax:
812 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
814 case AMDGPUIntrinsic::AMDGPU_imin:
815 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
817 case AMDGPUIntrinsic::AMDGPU_umin:
818 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
821 case AMDGPUIntrinsic::AMDGPU_umul24:
822 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
823 Op.getOperand(1), Op.getOperand(2));
825 case AMDGPUIntrinsic::AMDGPU_imul24:
826 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
827 Op.getOperand(1), Op.getOperand(2));
829 case AMDGPUIntrinsic::AMDGPU_umad24:
830 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
831 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
833 case AMDGPUIntrinsic::AMDGPU_imad24:
834 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
835 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
837 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
838 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
840 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
841 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
843 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
844 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
846 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
847 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
849 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
850 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
855 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
856 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
861 case AMDGPUIntrinsic::AMDGPU_bfi:
862 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
867 case AMDGPUIntrinsic::AMDGPU_bfm:
868 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
872 case AMDGPUIntrinsic::AMDGPU_brev:
873 return DAG.getNode(AMDGPUISD::BREV, DL, VT, Op.getOperand(1));
875 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
876 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
878 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
879 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
880 case AMDGPUIntrinsic::AMDGPU_trunc:
881 return DAG.getNode(ISD::FTRUNC, DL, VT, Op.getOperand(1));
885 ///IABS(a) = SMAX(sub(0, a), a)
886 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
887 SelectionDAG &DAG) const {
889 EVT VT = Op.getValueType();
890 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
893 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
896 /// Linear Interpolation
897 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
898 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
899 SelectionDAG &DAG) const {
901 EVT VT = Op.getValueType();
902 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
903 DAG.getConstantFP(1.0f, MVT::f32),
905 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
907 return DAG.getNode(ISD::FADD, DL, VT,
908 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
912 /// \brief Generate Min/Max node
913 SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
914 SelectionDAG &DAG) const {
916 EVT VT = N->getValueType(0);
918 SDValue LHS = N->getOperand(0);
919 SDValue RHS = N->getOperand(1);
920 SDValue True = N->getOperand(2);
921 SDValue False = N->getOperand(3);
922 SDValue CC = N->getOperand(4);
924 if (VT != MVT::f32 ||
925 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
929 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
943 llvm_unreachable("Operation should already be optimised!");
950 unsigned Opc = (LHS == True) ? AMDGPUISD::FMIN : AMDGPUISD::FMAX;
951 return DAG.getNode(Opc, DL, VT, LHS, RHS);
959 unsigned Opc = (LHS == True) ? AMDGPUISD::FMAX : AMDGPUISD::FMIN;
960 return DAG.getNode(Opc, DL, VT, LHS, RHS);
962 case ISD::SETCC_INVALID:
963 llvm_unreachable("Invalid setcc condcode!");
968 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
969 SelectionDAG &DAG) const {
970 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
971 EVT MemEltVT = Load->getMemoryVT().getVectorElementType();
972 EVT EltVT = Op.getValueType().getVectorElementType();
973 EVT PtrVT = Load->getBasePtr().getValueType();
974 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
975 SmallVector<SDValue, 8> Loads;
978 for (unsigned i = 0, e = NumElts; i != e; ++i) {
979 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
980 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), PtrVT));
981 Loads.push_back(DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
982 Load->getChain(), Ptr,
983 MachinePointerInfo(Load->getMemOperand()->getValue()),
984 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
985 Load->getAlignment()));
987 return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(), Loads);
990 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
991 SelectionDAG &DAG) const {
992 StoreSDNode *Store = cast<StoreSDNode>(Op);
993 EVT MemVT = Store->getMemoryVT();
994 unsigned MemBits = MemVT.getSizeInBits();
996 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
997 // truncating store into an i32 store.
998 // XXX: We could also handle optimize other vector bitwidths.
999 if (!MemVT.isVector() || MemBits > 32) {
1004 SDValue Value = Store->getValue();
1005 EVT VT = Value.getValueType();
1006 EVT ElemVT = VT.getVectorElementType();
1007 SDValue Ptr = Store->getBasePtr();
1008 EVT MemEltVT = MemVT.getVectorElementType();
1009 unsigned MemEltBits = MemEltVT.getSizeInBits();
1010 unsigned MemNumElements = MemVT.getVectorNumElements();
1011 unsigned PackedSize = MemVT.getStoreSizeInBits();
1012 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1014 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1016 SDValue PackedValue;
1017 for (unsigned i = 0; i < MemNumElements; ++i) {
1018 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1019 DAG.getConstant(i, MVT::i32));
1020 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1021 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1023 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1024 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1029 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1033 if (PackedSize < 32) {
1034 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1035 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1036 Store->getMemOperand()->getPointerInfo(),
1038 Store->isNonTemporal(), Store->isVolatile(),
1039 Store->getAlignment());
1042 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1043 Store->getMemOperand()->getPointerInfo(),
1044 Store->isVolatile(), Store->isNonTemporal(),
1045 Store->getAlignment());
1048 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1049 SelectionDAG &DAG) const {
1050 StoreSDNode *Store = cast<StoreSDNode>(Op);
1051 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1052 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1053 EVT PtrVT = Store->getBasePtr().getValueType();
1054 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1057 SmallVector<SDValue, 8> Chains;
1059 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1060 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1061 Store->getValue(), DAG.getConstant(i, MVT::i32));
1062 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT,
1063 Store->getBasePtr(),
1064 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
1066 Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1067 MachinePointerInfo(Store->getMemOperand()->getValue()),
1068 MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
1069 Store->getAlignment()));
1071 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1074 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1076 LoadSDNode *Load = cast<LoadSDNode>(Op);
1077 ISD::LoadExtType ExtType = Load->getExtensionType();
1078 EVT VT = Op.getValueType();
1079 EVT MemVT = Load->getMemoryVT();
1081 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1082 // We can do the extload to 32-bits, and then need to separately extend to
1085 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1089 Load->getMemOperand());
1090 return DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32);
1093 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1094 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1095 // FIXME: Copied from PPC
1096 // First, load into 32 bits, then truncate to 1 bit.
1098 SDValue Chain = Load->getChain();
1099 SDValue BasePtr = Load->getBasePtr();
1100 MachineMemOperand *MMO = Load->getMemOperand();
1102 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1103 BasePtr, MVT::i8, MMO);
1104 return DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
1107 // Lower loads constant address space global variable loads
1108 if (Load->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
1109 isa<GlobalVariable>(
1110 GetUnderlyingObject(Load->getMemOperand()->getValue()))) {
1112 SDValue Ptr = DAG.getZExtOrTrunc(Load->getBasePtr(), DL,
1113 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
1114 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1115 DAG.getConstant(2, MVT::i32));
1116 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1117 Load->getChain(), Ptr,
1118 DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2));
1121 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1122 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1126 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1127 DAG.getConstant(2, MVT::i32));
1128 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1129 Load->getChain(), Ptr,
1130 DAG.getTargetConstant(0, MVT::i32),
1132 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1134 DAG.getConstant(0x3, MVT::i32));
1135 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1136 DAG.getConstant(3, MVT::i32));
1138 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1140 EVT MemEltVT = MemVT.getScalarType();
1141 if (ExtType == ISD::SEXTLOAD) {
1142 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1143 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
1146 return DAG.getZeroExtendInReg(Ret, DL, MemEltVT);
1149 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1151 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1152 if (Result.getNode()) {
1156 StoreSDNode *Store = cast<StoreSDNode>(Op);
1157 SDValue Chain = Store->getChain();
1158 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1159 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1160 Store->getValue().getValueType().isVector()) {
1161 return SplitVectorStore(Op, DAG);
1164 EVT MemVT = Store->getMemoryVT();
1165 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1166 MemVT.bitsLT(MVT::i32)) {
1168 if (Store->getMemoryVT() == MVT::i8) {
1170 } else if (Store->getMemoryVT() == MVT::i16) {
1173 SDValue BasePtr = Store->getBasePtr();
1174 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1175 DAG.getConstant(2, MVT::i32));
1176 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1177 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1179 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1180 DAG.getConstant(0x3, MVT::i32));
1182 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1183 DAG.getConstant(3, MVT::i32));
1185 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1188 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1190 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1191 MaskedValue, ShiftAmt);
1193 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1195 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1196 DAG.getConstant(0xffffffff, MVT::i32));
1197 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1199 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1200 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1201 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1206 SDValue AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const {
1208 EVT OVT = Op.getValueType();
1209 SDValue LHS = Op.getOperand(0);
1210 SDValue RHS = Op.getOperand(1);
1213 if (!OVT.isVector()) {
1216 } else if (OVT.getVectorNumElements() == 2) {
1219 } else if (OVT.getVectorNumElements() == 4) {
1223 unsigned bitsize = OVT.getScalarType().getSizeInBits();
1224 // char|short jq = ia ^ ib;
1225 SDValue jq = DAG.getNode(ISD::XOR, DL, OVT, LHS, RHS);
1227 // jq = jq >> (bitsize - 2)
1228 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
1231 jq = DAG.getNode(ISD::OR, DL, OVT, jq, DAG.getConstant(1, OVT));
1234 jq = DAG.getSExtOrTrunc(jq, DL, INTTY);
1236 // int ia = (int)LHS;
1237 SDValue ia = DAG.getSExtOrTrunc(LHS, DL, INTTY);
1239 // int ib, (int)RHS;
1240 SDValue ib = DAG.getSExtOrTrunc(RHS, DL, INTTY);
1242 // float fa = (float)ia;
1243 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);
1245 // float fb = (float)ib;
1246 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
1248 // float fq = native_divide(fa, fb);
1249 SDValue fq = DAG.getNode(AMDGPUISD::DIV_INF, DL, FLTTY, fa, fb);
1252 fq = DAG.getNode(ISD::FTRUNC, DL, FLTTY, fq);
1254 // float fqneg = -fq;
1255 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq);
1257 // float fr = mad(fqneg, fb, fa);
1258 SDValue fr = DAG.getNode(ISD::FADD, DL, FLTTY,
1259 DAG.getNode(ISD::MUL, DL, FLTTY, fqneg, fb), fa);
1261 // int iq = (int)fq;
1262 SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);
1265 fr = DAG.getNode(ISD::FABS, DL, FLTTY, fr);
1268 fb = DAG.getNode(ISD::FABS, DL, FLTTY, fb);
1270 // int cv = fr >= fb;
1272 if (INTTY == MVT::i32) {
1273 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
1275 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
1277 // jq = (cv ? jq : 0);
1278 jq = DAG.getNode(ISD::SELECT, DL, OVT, cv, jq,
1279 DAG.getConstant(0, OVT));
1281 iq = DAG.getSExtOrTrunc(iq, DL, OVT);
1282 iq = DAG.getNode(ISD::ADD, DL, OVT, iq, jq);
1286 SDValue AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const {
1288 EVT OVT = Op.getValueType();
1289 SDValue LHS = Op.getOperand(0);
1290 SDValue RHS = Op.getOperand(1);
1291 // The LowerSDIV32 function generates equivalent to the following IL.
1301 // ixor r10, r10, r11
1303 // ixor DST, r0, r10
1312 SDValue r10 = DAG.getSelectCC(DL,
1313 r0, DAG.getConstant(0, OVT),
1314 DAG.getConstant(-1, OVT),
1315 DAG.getConstant(0, OVT),
1319 SDValue r11 = DAG.getSelectCC(DL,
1320 r1, DAG.getConstant(0, OVT),
1321 DAG.getConstant(-1, OVT),
1322 DAG.getConstant(0, OVT),
1326 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1329 r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
1332 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1335 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
1338 r0 = DAG.getNode(ISD::UDIV, DL, OVT, r0, r1);
1340 // ixor r10, r10, r11
1341 r10 = DAG.getNode(ISD::XOR, DL, OVT, r10, r11);
1344 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1346 // ixor DST, r0, r10
1347 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1351 SDValue AMDGPUTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const {
1352 return SDValue(Op.getNode(), 0);
1355 SDValue AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
1356 EVT OVT = Op.getValueType().getScalarType();
1358 if (OVT == MVT::i64)
1359 return LowerSDIV64(Op, DAG);
1361 if (OVT.getScalarType() == MVT::i32)
1362 return LowerSDIV32(Op, DAG);
1364 if (OVT == MVT::i16 || OVT == MVT::i8) {
1365 // FIXME: We should be checking for the masked bits. This isn't reached
1366 // because i8 and i16 are not legal types.
1367 return LowerSDIV24(Op, DAG);
1370 return SDValue(Op.getNode(), 0);
1373 SDValue AMDGPUTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const {
1375 EVT OVT = Op.getValueType();
1376 SDValue LHS = Op.getOperand(0);
1377 SDValue RHS = Op.getOperand(1);
1378 // The LowerSREM32 function generates equivalent to the following IL.
1388 // umul r20, r20, r1
1391 // ixor DST, r0, r10
1400 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT);
1403 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT);
1406 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1409 r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
1412 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1415 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
1418 SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1);
1420 // umul r20, r20, r1
1421 r20 = DAG.getNode(AMDGPUISD::UMUL, DL, OVT, r20, r1);
1424 r0 = DAG.getNode(ISD::SUB, DL, OVT, r0, r20);
1427 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1429 // ixor DST, r0, r10
1430 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1434 SDValue AMDGPUTargetLowering::LowerSREM64(SDValue Op, SelectionDAG &DAG) const {
1435 return SDValue(Op.getNode(), 0);
1438 SDValue AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const {
1439 EVT OVT = Op.getValueType();
1441 if (OVT.getScalarType() == MVT::i64)
1442 return LowerSREM64(Op, DAG);
1444 if (OVT.getScalarType() == MVT::i32)
1445 return LowerSREM32(Op, DAG);
1447 return SDValue(Op.getNode(), 0);
1450 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1451 SelectionDAG &DAG) const {
1453 EVT VT = Op.getValueType();
1455 SDValue Num = Op.getOperand(0);
1456 SDValue Den = Op.getOperand(1);
1458 // RCP = URECIP(Den) = 2^32 / Den + e
1459 // e is rounding error.
1460 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1462 // RCP_LO = umulo(RCP, Den) */
1463 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
1465 // RCP_HI = mulhu (RCP, Den) */
1466 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1468 // NEG_RCP_LO = -RCP_LO
1469 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1472 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1473 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1476 // Calculate the rounding error from the URECIP instruction
1477 // E = mulhu(ABS_RCP_LO, RCP)
1478 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1480 // RCP_A_E = RCP + E
1481 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1483 // RCP_S_E = RCP - E
1484 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1486 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1487 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1490 // Quotient = mulhu(Tmp0, Num)
1491 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1493 // Num_S_Remainder = Quotient * Den
1494 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
1496 // Remainder = Num - Num_S_Remainder
1497 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1499 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1500 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1501 DAG.getConstant(-1, VT),
1502 DAG.getConstant(0, VT),
1504 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1505 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1507 DAG.getConstant(-1, VT),
1508 DAG.getConstant(0, VT),
1510 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1511 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1514 // Calculate Division result:
1516 // Quotient_A_One = Quotient + 1
1517 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1518 DAG.getConstant(1, VT));
1520 // Quotient_S_One = Quotient - 1
1521 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1522 DAG.getConstant(1, VT));
1524 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1525 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1526 Quotient, Quotient_A_One, ISD::SETEQ);
1528 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1529 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1530 Quotient_S_One, Div, ISD::SETEQ);
1532 // Calculate Rem result:
1534 // Remainder_S_Den = Remainder - Den
1535 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1537 // Remainder_A_Den = Remainder + Den
1538 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1540 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1541 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1542 Remainder, Remainder_S_Den, ISD::SETEQ);
1544 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1545 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1546 Remainder_A_Den, Rem, ISD::SETEQ);
1551 return DAG.getMergeValues(Ops, DL);
1554 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1555 SelectionDAG &DAG) const {
1557 EVT VT = Op.getValueType();
1559 SDValue Zero = DAG.getConstant(0, VT);
1560 SDValue NegOne = DAG.getConstant(-1, VT);
1562 SDValue LHS = Op.getOperand(0);
1563 SDValue RHS = Op.getOperand(1);
1565 SDValue LHSign = DAG.getSelectCC(DL, LHS, Zero, NegOne, Zero, ISD::SETLT);
1566 SDValue RHSign = DAG.getSelectCC(DL, RHS, Zero, NegOne, Zero, ISD::SETLT);
1567 SDValue DSign = DAG.getNode(ISD::XOR, DL, VT, LHSign, RHSign);
1568 SDValue RSign = LHSign; // Remainder sign is the same as LHS
1570 LHS = DAG.getNode(ISD::ADD, DL, VT, LHS, LHSign);
1571 RHS = DAG.getNode(ISD::ADD, DL, VT, RHS, RHSign);
1573 LHS = DAG.getNode(ISD::XOR, DL, VT, LHS, LHSign);
1574 RHS = DAG.getNode(ISD::XOR, DL, VT, RHS, RHSign);
1576 SDValue Div = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT), LHS, RHS);
1577 SDValue Rem = Div.getValue(1);
1579 Div = DAG.getNode(ISD::XOR, DL, VT, Div, DSign);
1580 Rem = DAG.getNode(ISD::XOR, DL, VT, Rem, RSign);
1582 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign);
1583 Rem = DAG.getNode(ISD::SUB, DL, VT, Rem, RSign);
1589 return DAG.getMergeValues(Res, DL);
1592 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1594 SDValue Src = Op.getOperand(0);
1596 // result = trunc(src)
1597 // if (src > 0.0 && src != result)
1600 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1602 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1603 const SDValue One = DAG.getConstantFP(1.0, MVT::f64);
1605 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1607 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOGT);
1608 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1609 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1611 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, One, Zero);
1612 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1615 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1617 SDValue Src = Op.getOperand(0);
1619 assert(Op.getValueType() == MVT::f64);
1621 const SDValue Zero = DAG.getConstant(0, MVT::i32);
1622 const SDValue One = DAG.getConstant(1, MVT::i32);
1624 SDValue VecSrc = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Src);
1626 // Extract the upper half, since this is where we will find the sign and
1628 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One);
1630 const unsigned FractBits = 52;
1631 const unsigned ExpBits = 11;
1633 // Extract the exponent.
1634 SDValue ExpPart = DAG.getNode(AMDGPUISD::BFE_I32, SL, MVT::i32,
1636 DAG.getConstant(FractBits - 32, MVT::i32),
1637 DAG.getConstant(ExpBits, MVT::i32));
1638 SDValue Exp = DAG.getNode(ISD::SUB, SL, MVT::i32, ExpPart,
1639 DAG.getConstant(1023, MVT::i32));
1641 // Extract the sign bit.
1642 const SDValue SignBitMask = DAG.getConstant(UINT32_C(1) << 31, MVT::i32);
1643 SDValue SignBit = DAG.getNode(ISD::AND, SL, MVT::i32, Hi, SignBitMask);
1645 // Extend back to to 64-bits.
1646 SDValue SignBit64 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
1648 SignBit64 = DAG.getNode(ISD::BITCAST, SL, MVT::i64, SignBit64);
1650 SDValue BcInt = DAG.getNode(ISD::BITCAST, SL, MVT::i64, Src);
1651 const SDValue FractMask
1652 = DAG.getConstant((UINT64_C(1) << FractBits) - 1, MVT::i64);
1654 SDValue Shr = DAG.getNode(ISD::SRA, SL, MVT::i64, FractMask, Exp);
1655 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64);
1656 SDValue Tmp0 = DAG.getNode(ISD::AND, SL, MVT::i64, BcInt, Not);
1658 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::i32);
1660 const SDValue FiftyOne = DAG.getConstant(FractBits - 1, MVT::i32);
1662 SDValue ExpLt0 = DAG.getSetCC(SL, SetCCVT, Exp, Zero, ISD::SETLT);
1663 SDValue ExpGt51 = DAG.getSetCC(SL, SetCCVT, Exp, FiftyOne, ISD::SETGT);
1665 SDValue Tmp1 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpLt0, SignBit64, Tmp0);
1666 SDValue Tmp2 = DAG.getNode(ISD::SELECT, SL, MVT::i64, ExpGt51, BcInt, Tmp1);
1668 return DAG.getNode(ISD::BITCAST, SL, MVT::f64, Tmp2);
1671 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1673 SDValue Src = Op.getOperand(0);
1675 assert(Op.getValueType() == MVT::f64);
1677 APFloat C1Val(APFloat::IEEEdouble, "0x1.0p+52");
1678 SDValue C1 = DAG.getConstantFP(C1Val, MVT::f64);
1679 SDValue CopySign = DAG.getNode(ISD::FCOPYSIGN, SL, MVT::f64, C1, Src);
1681 SDValue Tmp1 = DAG.getNode(ISD::FADD, SL, MVT::f64, Src, CopySign);
1682 SDValue Tmp2 = DAG.getNode(ISD::FSUB, SL, MVT::f64, Tmp1, CopySign);
1684 SDValue Fabs = DAG.getNode(ISD::FABS, SL, MVT::f64, Src);
1686 APFloat C2Val(APFloat::IEEEdouble, "0x1.fffffffffffffp+51");
1687 SDValue C2 = DAG.getConstantFP(C2Val, MVT::f64);
1689 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1690 SDValue Cond = DAG.getSetCC(SL, SetCCVT, Fabs, C2, ISD::SETOGT);
1692 return DAG.getSelect(SL, MVT::f64, Cond, Src, Tmp2);
1695 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1696 // FNEARBYINT and FRINT are the same, except in their handling of FP
1697 // exceptions. Those aren't really meaningful for us, and OpenCL only has
1698 // rint, so just treat them as equivalent.
1699 return DAG.getNode(ISD::FRINT, SDLoc(Op), Op.getValueType(), Op.getOperand(0));
1702 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1704 SDValue Src = Op.getOperand(0);
1706 // result = trunc(src);
1707 // if (src < 0.0 && src != result)
1710 SDValue Trunc = DAG.getNode(ISD::FTRUNC, SL, MVT::f64, Src);
1712 const SDValue Zero = DAG.getConstantFP(0.0, MVT::f64);
1713 const SDValue NegOne = DAG.getConstantFP(-1.0, MVT::f64);
1715 EVT SetCCVT = getSetCCResultType(*DAG.getContext(), MVT::f64);
1717 SDValue Lt0 = DAG.getSetCC(SL, SetCCVT, Src, Zero, ISD::SETOLT);
1718 SDValue NeTrunc = DAG.getSetCC(SL, SetCCVT, Src, Trunc, ISD::SETONE);
1719 SDValue And = DAG.getNode(ISD::AND, SL, SetCCVT, Lt0, NeTrunc);
1721 SDValue Add = DAG.getNode(ISD::SELECT, SL, MVT::f64, And, NegOne, Zero);
1722 return DAG.getNode(ISD::FADD, SL, MVT::f64, Trunc, Add);
1725 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1726 SelectionDAG &DAG) const {
1727 SDValue S0 = Op.getOperand(0);
1729 if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64)
1732 // f32 uint_to_fp i64
1733 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1734 DAG.getConstant(0, MVT::i32));
1735 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1736 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1737 DAG.getConstant(1, MVT::i32));
1738 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1739 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1740 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1741 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1744 SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
1746 SelectionDAG &DAG) const {
1747 MVT VT = Op.getSimpleValueType();
1749 SDValue Shift = DAG.getConstant(BitsDiff, VT);
1750 // Shift left by 'Shift' bits.
1751 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
1752 // Signed shift Right by 'Shift' bits.
1753 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
1756 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1757 SelectionDAG &DAG) const {
1758 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1759 MVT VT = Op.getSimpleValueType();
1760 MVT ScalarVT = VT.getScalarType();
1765 SDValue Src = Op.getOperand(0);
1768 // TODO: Don't scalarize on Evergreen?
1769 unsigned NElts = VT.getVectorNumElements();
1770 SmallVector<SDValue, 8> Args;
1771 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1773 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1774 for (unsigned I = 0; I < NElts; ++I)
1775 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1777 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1780 //===----------------------------------------------------------------------===//
1781 // Custom DAG optimizations
1782 //===----------------------------------------------------------------------===//
1784 static bool isU24(SDValue Op, SelectionDAG &DAG) {
1785 APInt KnownZero, KnownOne;
1786 EVT VT = Op.getValueType();
1787 DAG.computeKnownBits(Op, KnownZero, KnownOne);
1789 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1792 static bool isI24(SDValue Op, SelectionDAG &DAG) {
1793 EVT VT = Op.getValueType();
1795 // In order for this to be a signed 24-bit value, bit 23, must
1797 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1798 // as unsigned 24-bit values.
1799 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1802 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
1804 SelectionDAG &DAG = DCI.DAG;
1805 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1806 EVT VT = Op.getValueType();
1808 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
1809 APInt KnownZero, KnownOne;
1810 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
1811 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
1812 DCI.CommitTargetLoweringOpt(TLO);
1815 template <typename IntTy>
1816 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
1817 uint32_t Offset, uint32_t Width) {
1818 if (Width + Offset < 32) {
1819 IntTy Result = (Src0 << (32 - Offset - Width)) >> (32 - Width);
1820 return DAG.getConstant(Result, MVT::i32);
1823 return DAG.getConstant(Src0 >> Offset, MVT::i32);
1826 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
1827 DAGCombinerInfo &DCI) const {
1828 SelectionDAG &DAG = DCI.DAG;
1831 switch(N->getOpcode()) {
1834 EVT VT = N->getValueType(0);
1835 SDValue N0 = N->getOperand(0);
1836 SDValue N1 = N->getOperand(1);
1839 // FIXME: Add support for 24-bit multiply with 64-bit output on SI.
1840 if (VT.isVector() || VT.getSizeInBits() > 32)
1843 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
1844 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
1845 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
1846 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
1847 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
1848 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
1849 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
1850 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
1855 // We need to use sext even for MUL_U24, because MUL_U24 is used
1856 // for signed multiply of 8 and 16-bit types.
1857 SDValue Reg = DAG.getSExtOrTrunc(Mul, DL, VT);
1861 case AMDGPUISD::MUL_I24:
1862 case AMDGPUISD::MUL_U24: {
1863 SDValue N0 = N->getOperand(0);
1864 SDValue N1 = N->getOperand(1);
1865 simplifyI24(N0, DCI);
1866 simplifyI24(N1, DCI);
1869 case ISD::SELECT_CC: {
1870 return CombineMinMax(N, DAG);
1872 case AMDGPUISD::BFE_I32:
1873 case AMDGPUISD::BFE_U32: {
1874 assert(!N->getValueType(0).isVector() &&
1875 "Vector handling of BFE not implemented");
1876 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
1880 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
1882 return DAG.getConstant(0, MVT::i32);
1884 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
1888 SDValue BitsFrom = N->getOperand(0);
1889 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
1891 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
1893 if (OffsetVal == 0) {
1894 // This is already sign / zero extended, so try to fold away extra BFEs.
1895 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
1897 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
1898 if (OpSignBits >= SignBits)
1901 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
1903 // This is a sign_extend_inreg. Replace it to take advantage of existing
1904 // DAG Combines. If not eliminated, we will match back to BFE during
1907 // TODO: The sext_inreg of extended types ends, although we can could
1908 // handle them in a single BFE.
1909 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
1910 DAG.getValueType(SmallVT));
1913 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
1916 if (ConstantSDNode *Val = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
1918 return constantFoldBFE<int32_t>(DAG,
1919 Val->getSExtValue(),
1924 return constantFoldBFE<uint32_t>(DAG,
1925 Val->getZExtValue(),
1930 APInt Demanded = APInt::getBitsSet(32,
1932 OffsetVal + WidthVal);
1934 if ((OffsetVal + WidthVal) >= 32) {
1935 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
1936 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1937 BitsFrom, ShiftVal);
1940 APInt KnownZero, KnownOne;
1941 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1942 !DCI.isBeforeLegalizeOps());
1943 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1944 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
1945 TLI.SimplifyDemandedBits(BitsFrom, Demanded, KnownZero, KnownOne, TLO)) {
1946 DCI.CommitTargetLoweringOpt(TLO);
1955 //===----------------------------------------------------------------------===//
1957 //===----------------------------------------------------------------------===//
1959 void AMDGPUTargetLowering::getOriginalFunctionArgs(
1962 const SmallVectorImpl<ISD::InputArg> &Ins,
1963 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
1965 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1966 if (Ins[i].ArgVT == Ins[i].VT) {
1967 OrigIns.push_back(Ins[i]);
1972 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
1973 // Vector has been split into scalars.
1974 VT = Ins[i].ArgVT.getVectorElementType();
1975 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
1976 Ins[i].ArgVT.getVectorElementType() !=
1977 Ins[i].VT.getVectorElementType()) {
1978 // Vector elements have been promoted
1981 // Vector has been spilt into smaller vectors.
1985 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
1986 Ins[i].OrigArgIndex, Ins[i].PartOffset);
1987 OrigIns.push_back(Arg);
1991 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
1992 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
1993 return CFP->isExactlyValue(1.0);
1995 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
1996 return C->isAllOnesValue();
2001 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
2002 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
2003 return CFP->getValueAPF().isZero();
2005 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
2006 return C->isNullValue();
2011 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2012 const TargetRegisterClass *RC,
2013 unsigned Reg, EVT VT) const {
2014 MachineFunction &MF = DAG.getMachineFunction();
2015 MachineRegisterInfo &MRI = MF.getRegInfo();
2016 unsigned VirtualRegister;
2017 if (!MRI.isLiveIn(Reg)) {
2018 VirtualRegister = MRI.createVirtualRegister(RC);
2019 MRI.addLiveIn(Reg, VirtualRegister);
2021 VirtualRegister = MRI.getLiveInVirtReg(Reg);
2023 return DAG.getRegister(VirtualRegister, VT);
2026 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
2028 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2030 default: return nullptr;
2032 NODE_NAME_CASE(CALL);
2033 NODE_NAME_CASE(UMUL);
2034 NODE_NAME_CASE(DIV_INF);
2035 NODE_NAME_CASE(RET_FLAG);
2036 NODE_NAME_CASE(BRANCH_COND);
2039 NODE_NAME_CASE(DWORDADDR)
2040 NODE_NAME_CASE(FRACT)
2041 NODE_NAME_CASE(CLAMP)
2042 NODE_NAME_CASE(FMAX)
2043 NODE_NAME_CASE(SMAX)
2044 NODE_NAME_CASE(UMAX)
2045 NODE_NAME_CASE(FMIN)
2046 NODE_NAME_CASE(SMIN)
2047 NODE_NAME_CASE(UMIN)
2048 NODE_NAME_CASE(URECIP)
2049 NODE_NAME_CASE(DIV_SCALE)
2050 NODE_NAME_CASE(DIV_FMAS)
2051 NODE_NAME_CASE(DIV_FIXUP)
2052 NODE_NAME_CASE(TRIG_PREOP)
2055 NODE_NAME_CASE(DOT4)
2056 NODE_NAME_CASE(BFE_U32)
2057 NODE_NAME_CASE(BFE_I32)
2060 NODE_NAME_CASE(BREV)
2061 NODE_NAME_CASE(MUL_U24)
2062 NODE_NAME_CASE(MUL_I24)
2063 NODE_NAME_CASE(MAD_U24)
2064 NODE_NAME_CASE(MAD_I24)
2065 NODE_NAME_CASE(EXPORT)
2066 NODE_NAME_CASE(CONST_ADDRESS)
2067 NODE_NAME_CASE(REGISTER_LOAD)
2068 NODE_NAME_CASE(REGISTER_STORE)
2069 NODE_NAME_CASE(LOAD_CONSTANT)
2070 NODE_NAME_CASE(LOAD_INPUT)
2071 NODE_NAME_CASE(SAMPLE)
2072 NODE_NAME_CASE(SAMPLEB)
2073 NODE_NAME_CASE(SAMPLED)
2074 NODE_NAME_CASE(SAMPLEL)
2075 NODE_NAME_CASE(CVT_F32_UBYTE0)
2076 NODE_NAME_CASE(CVT_F32_UBYTE1)
2077 NODE_NAME_CASE(CVT_F32_UBYTE2)
2078 NODE_NAME_CASE(CVT_F32_UBYTE3)
2079 NODE_NAME_CASE(BUILD_VERTICAL_VECTOR)
2080 NODE_NAME_CASE(STORE_MSKOR)
2081 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
2085 static void computeKnownBitsForMinMax(const SDValue Op0,
2089 const SelectionDAG &DAG,
2091 APInt Op0Zero, Op0One;
2092 APInt Op1Zero, Op1One;
2093 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
2094 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
2096 KnownZero = Op0Zero & Op1Zero;
2097 KnownOne = Op0One & Op1One;
2100 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2104 const SelectionDAG &DAG,
2105 unsigned Depth) const {
2107 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
2111 unsigned Opc = Op.getOpcode();
2116 case ISD::INTRINSIC_WO_CHAIN: {
2117 // FIXME: The intrinsic should just use the node.
2118 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
2119 case AMDGPUIntrinsic::AMDGPU_imax:
2120 case AMDGPUIntrinsic::AMDGPU_umax:
2121 case AMDGPUIntrinsic::AMDGPU_imin:
2122 case AMDGPUIntrinsic::AMDGPU_umin:
2123 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
2124 KnownZero, KnownOne, DAG, Depth);
2132 case AMDGPUISD::SMAX:
2133 case AMDGPUISD::UMAX:
2134 case AMDGPUISD::SMIN:
2135 case AMDGPUISD::UMIN:
2136 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
2137 KnownZero, KnownOne, DAG, Depth);
2140 case AMDGPUISD::BFE_I32:
2141 case AMDGPUISD::BFE_U32: {
2142 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2146 unsigned BitWidth = 32;
2147 uint32_t Width = CWidth->getZExtValue() & 0x1f;
2149 KnownZero = APInt::getAllOnesValue(BitWidth);
2150 KnownOne = APInt::getNullValue(BitWidth);
2154 // FIXME: This could do a lot more. If offset is 0, should be the same as
2155 // sign_extend_inreg implementation, but that involves duplicating it.
2156 if (Opc == AMDGPUISD::BFE_I32)
2157 KnownOne = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2159 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
2166 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2168 const SelectionDAG &DAG,
2169 unsigned Depth) const {
2170 switch (Op.getOpcode()) {
2171 case AMDGPUISD::BFE_I32: {
2172 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2176 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2177 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2178 if (!Offset || !Offset->isNullValue())
2181 // TODO: Could probably figure something out with non-0 offsets.
2182 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2183 return std::max(SignBits, Op0SignBits);
2186 case AMDGPUISD::BFE_U32: {
2187 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2188 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;