1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This is the parent TargetLowering class for hardware code gen
14 //===----------------------------------------------------------------------===//
16 #include "AMDGPUISelLowering.h"
18 #include "AMDGPUFrameLowering.h"
19 #include "AMDGPURegisterInfo.h"
20 #include "AMDGPUSubtarget.h"
21 #include "AMDILIntrinsicInfo.h"
22 #include "R600MachineFunctionInfo.h"
23 #include "SIMachineFunctionInfo.h"
24 #include "llvm/Analysis/ValueTracking.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/DataLayout.h"
31 #include "llvm/IR/DiagnosticInfo.h"
32 #include "llvm/IR/DiagnosticPrinter.h"
38 /// Diagnostic information for unimplemented or unsupported feature reporting.
39 class DiagnosticInfoUnsupported : public DiagnosticInfo {
41 const Twine &Description;
46 static int getKindID() {
48 KindID = llvm::getNextAvailablePluginDiagnosticKind();
53 DiagnosticInfoUnsupported(const Function &Fn, const Twine &Desc,
54 DiagnosticSeverity Severity = DS_Error)
55 : DiagnosticInfo(getKindID(), Severity),
59 const Function &getFunction() const { return Fn; }
60 const Twine &getDescription() const { return Description; }
62 void print(DiagnosticPrinter &DP) const override {
63 DP << "unsupported " << getDescription() << " in " << Fn.getName();
66 static bool classof(const DiagnosticInfo *DI) {
67 return DI->getKind() == getKindID();
71 int DiagnosticInfoUnsupported::KindID = 0;
75 static bool allocateStack(unsigned ValNo, MVT ValVT, MVT LocVT,
76 CCValAssign::LocInfo LocInfo,
77 ISD::ArgFlagsTy ArgFlags, CCState &State) {
78 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(),
79 ArgFlags.getOrigAlign());
80 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
85 #include "AMDGPUGenCallingConv.inc"
87 // Find a larger type to do a load / store of a vector with.
88 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
89 unsigned StoreSize = VT.getStoreSizeInBits();
91 return EVT::getIntegerVT(Ctx, StoreSize);
93 assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
94 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
97 // Type for a vector that will be loaded to.
98 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
99 unsigned StoreSize = VT.getStoreSizeInBits();
101 return EVT::getIntegerVT(Ctx, 32);
103 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
106 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
107 TargetLowering(TM, new TargetLoweringObjectFileELF()) {
109 Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
111 // Initialize target lowering borrowed from AMDIL
114 // We need to custom lower some of the intrinsics
115 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
117 // Library functions. These default to Expand, but we have instructions
119 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
120 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
121 setOperationAction(ISD::FPOW, MVT::f32, Legal);
122 setOperationAction(ISD::FLOG2, MVT::f32, Legal);
123 setOperationAction(ISD::FABS, MVT::f32, Legal);
124 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
125 setOperationAction(ISD::FRINT, MVT::f32, Legal);
126 setOperationAction(ISD::FROUND, MVT::f32, Legal);
127 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
129 // Lower floating point store/load to integer store/load to reduce the number
130 // of patterns in tablegen.
131 setOperationAction(ISD::STORE, MVT::f32, Promote);
132 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
134 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
135 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
137 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
138 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
140 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
141 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
143 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
144 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
146 setOperationAction(ISD::STORE, MVT::f64, Promote);
147 AddPromotedToType(ISD::STORE, MVT::f64, MVT::i64);
149 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
150 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v2i64);
152 // Custom lowering of vector stores is required for local address space
154 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
155 // XXX: Native v2i32 local address space stores are possible, but not
156 // currently implemented.
157 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
159 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
160 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
161 setTruncStoreAction(MVT::v4i32, MVT::v4i8, Custom);
163 // XXX: This can be change to Custom, once ExpandVectorStores can
164 // handle 64-bit stores.
165 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand);
167 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
168 setTruncStoreAction(MVT::i64, MVT::i8, Expand);
169 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
170 setTruncStoreAction(MVT::v2i64, MVT::v2i1, Expand);
171 setTruncStoreAction(MVT::v4i64, MVT::v4i1, Expand);
174 setOperationAction(ISD::LOAD, MVT::f32, Promote);
175 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
177 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
178 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
180 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
181 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
183 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
184 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
186 setOperationAction(ISD::LOAD, MVT::v16f32, Promote);
187 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
189 setOperationAction(ISD::LOAD, MVT::f64, Promote);
190 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
192 setOperationAction(ISD::LOAD, MVT::v2f64, Promote);
193 AddPromotedToType(ISD::LOAD, MVT::v2f64, MVT::v2i64);
195 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
196 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
197 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom);
198 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
199 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
200 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
201 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
202 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom);
203 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
204 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8i32, Custom);
206 setLoadExtAction(ISD::EXTLOAD, MVT::v2i8, Expand);
207 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i8, Expand);
208 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i8, Expand);
209 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
210 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i8, Expand);
211 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i8, Expand);
212 setLoadExtAction(ISD::EXTLOAD, MVT::v2i16, Expand);
213 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i16, Expand);
214 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, Expand);
215 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, Expand);
216 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, Expand);
217 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, Expand);
219 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
221 if (!Subtarget->hasBFI()) {
222 // fcopysign can be done in a single instruction with BFI.
223 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
224 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
227 const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
228 for (MVT VT : ScalarIntVTs) {
229 setOperationAction(ISD::SREM, VT, Expand);
230 setOperationAction(ISD::SDIV, VT, Custom);
232 // GPU does not have divrem function for signed or unsigned.
233 setOperationAction(ISD::SDIVREM, VT, Expand);
234 setOperationAction(ISD::UDIVREM, VT, Custom);
236 // GPU does not have [S|U]MUL_LOHI functions as a single instruction.
237 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
238 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
240 setOperationAction(ISD::BSWAP, VT, Expand);
241 setOperationAction(ISD::CTTZ, VT, Expand);
242 setOperationAction(ISD::CTLZ, VT, Expand);
245 if (!Subtarget->hasBCNT(32))
246 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
248 if (!Subtarget->hasBCNT(64))
249 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
251 // The hardware supports 32-bit ROTR, but not ROTL.
252 setOperationAction(ISD::ROTL, MVT::i32, Expand);
253 setOperationAction(ISD::ROTL, MVT::i64, Expand);
254 setOperationAction(ISD::ROTR, MVT::i64, Expand);
256 setOperationAction(ISD::MUL, MVT::i64, Expand);
257 setOperationAction(ISD::MULHU, MVT::i64, Expand);
258 setOperationAction(ISD::MULHS, MVT::i64, Expand);
259 setOperationAction(ISD::SUB, MVT::i64, Expand);
260 setOperationAction(ISD::UDIV, MVT::i32, Expand);
261 setOperationAction(ISD::UREM, MVT::i32, Expand);
262 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
263 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
265 static const MVT::SimpleValueType VectorIntTypes[] = {
266 MVT::v2i32, MVT::v4i32
269 for (MVT VT : VectorIntTypes) {
270 // Expand the following operations for the current type by default.
271 setOperationAction(ISD::ADD, VT, Expand);
272 setOperationAction(ISD::AND, VT, Expand);
273 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
274 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
275 setOperationAction(ISD::MUL, VT, Expand);
276 setOperationAction(ISD::OR, VT, Expand);
277 setOperationAction(ISD::SHL, VT, Expand);
278 setOperationAction(ISD::SRA, VT, Expand);
279 setOperationAction(ISD::SRL, VT, Expand);
280 setOperationAction(ISD::ROTL, VT, Expand);
281 setOperationAction(ISD::ROTR, VT, Expand);
282 setOperationAction(ISD::SUB, VT, Expand);
283 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
284 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
285 // TODO: Implement custom UREM / SREM routines.
286 setOperationAction(ISD::SDIV, VT, Custom);
287 setOperationAction(ISD::UDIV, VT, Expand);
288 setOperationAction(ISD::SREM, VT, Expand);
289 setOperationAction(ISD::UREM, VT, Expand);
290 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
291 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
292 setOperationAction(ISD::SDIVREM, VT, Expand);
293 setOperationAction(ISD::UDIVREM, VT, Custom);
294 setOperationAction(ISD::SELECT, VT, Expand);
295 setOperationAction(ISD::VSELECT, VT, Expand);
296 setOperationAction(ISD::XOR, VT, Expand);
297 setOperationAction(ISD::BSWAP, VT, Expand);
298 setOperationAction(ISD::CTPOP, VT, Expand);
299 setOperationAction(ISD::CTTZ, VT, Expand);
300 setOperationAction(ISD::CTLZ, VT, Expand);
303 static const MVT::SimpleValueType FloatVectorTypes[] = {
304 MVT::v2f32, MVT::v4f32
307 for (MVT VT : FloatVectorTypes) {
308 setOperationAction(ISD::FABS, VT, Expand);
309 setOperationAction(ISD::FADD, VT, Expand);
310 setOperationAction(ISD::FCOS, VT, Expand);
311 setOperationAction(ISD::FDIV, VT, Expand);
312 setOperationAction(ISD::FPOW, VT, Expand);
313 setOperationAction(ISD::FFLOOR, VT, Expand);
314 setOperationAction(ISD::FTRUNC, VT, Expand);
315 setOperationAction(ISD::FMUL, VT, Expand);
316 setOperationAction(ISD::FRINT, VT, Expand);
317 setOperationAction(ISD::FSQRT, VT, Expand);
318 setOperationAction(ISD::FSIN, VT, Expand);
319 setOperationAction(ISD::FSUB, VT, Expand);
320 setOperationAction(ISD::FNEG, VT, Expand);
321 setOperationAction(ISD::SELECT, VT, Expand);
322 setOperationAction(ISD::VSELECT, VT, Expand);
323 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
326 setTargetDAGCombine(ISD::MUL);
327 setTargetDAGCombine(ISD::SELECT_CC);
329 setSchedulingPreference(Sched::RegPressure);
330 setJumpIsExpensive(true);
332 // There are no integer divide instructions, and these expand to a pretty
333 // large sequence of instructions.
334 setIntDivIsCheap(false);
336 // TODO: Investigate this when 64-bit divides are implemented.
337 addBypassSlowDiv(64, 32);
339 // FIXME: Need to really handle these.
340 MaxStoresPerMemcpy = 4096;
341 MaxStoresPerMemmove = 4096;
342 MaxStoresPerMemset = 4096;
345 //===----------------------------------------------------------------------===//
346 // Target Information
347 //===----------------------------------------------------------------------===//
349 MVT AMDGPUTargetLowering::getVectorIdxTy() const {
353 // The backend supports 32 and 64 bit floating point immediates.
354 // FIXME: Why are we reporting vectors of FP immediates as legal?
355 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
356 EVT ScalarVT = VT.getScalarType();
357 return (ScalarVT == MVT::f32 || MVT::f64);
360 // We don't want to shrink f64 / f32 constants.
361 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
362 EVT ScalarVT = VT.getScalarType();
363 return (ScalarVT != MVT::f32 && ScalarVT != MVT::f64);
366 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
368 if (LoadTy.getSizeInBits() != CastTy.getSizeInBits())
371 unsigned LScalarSize = LoadTy.getScalarType().getSizeInBits();
372 unsigned CastScalarSize = CastTy.getScalarType().getSizeInBits();
374 return ((LScalarSize <= CastScalarSize) ||
375 (CastScalarSize >= 32) ||
379 //===---------------------------------------------------------------------===//
381 //===---------------------------------------------------------------------===//
383 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
384 assert(VT.isFloatingPoint());
385 return VT == MVT::f32;
388 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
389 assert(VT.isFloatingPoint());
390 return VT == MVT::f32;
393 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
394 // Truncate is just accessing a subregister.
395 return Dest.bitsLT(Source) && (Dest.getSizeInBits() % 32 == 0);
398 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
399 // Truncate is just accessing a subregister.
400 return Dest->getPrimitiveSizeInBits() < Source->getPrimitiveSizeInBits() &&
401 (Dest->getPrimitiveSizeInBits() % 32 == 0);
404 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
405 const DataLayout *DL = getDataLayout();
406 unsigned SrcSize = DL->getTypeSizeInBits(Src->getScalarType());
407 unsigned DestSize = DL->getTypeSizeInBits(Dest->getScalarType());
409 return SrcSize == 32 && DestSize == 64;
412 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
413 // Any register load of a 64-bit value really requires 2 32-bit moves. For all
414 // practical purposes, the extra mov 0 to load a 64-bit is free. As used,
415 // this will enable reducing 64-bit operations the 32-bit, which is always
417 return Src == MVT::i32 && Dest == MVT::i64;
420 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
421 // There aren't really 64-bit registers, but pairs of 32-bit ones and only a
422 // limited number of native 64-bit operations. Shrinking an operation to fit
423 // in a single 32-bit register should always be helpful. As currently used,
424 // this is much less general than the name suggests, and is only used in
425 // places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
426 // not profitable, and may actually be harmful.
427 return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
430 //===---------------------------------------------------------------------===//
431 // TargetLowering Callbacks
432 //===---------------------------------------------------------------------===//
434 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
435 const SmallVectorImpl<ISD::InputArg> &Ins) const {
437 State.AnalyzeFormalArguments(Ins, CC_AMDGPU);
440 SDValue AMDGPUTargetLowering::LowerReturn(
442 CallingConv::ID CallConv,
444 const SmallVectorImpl<ISD::OutputArg> &Outs,
445 const SmallVectorImpl<SDValue> &OutVals,
446 SDLoc DL, SelectionDAG &DAG) const {
447 return DAG.getNode(AMDGPUISD::RET_FLAG, DL, MVT::Other, Chain);
450 //===---------------------------------------------------------------------===//
451 // Target specific lowering
452 //===---------------------------------------------------------------------===//
454 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
455 SmallVectorImpl<SDValue> &InVals) const {
456 SDValue Callee = CLI.Callee;
457 SelectionDAG &DAG = CLI.DAG;
459 const Function &Fn = *DAG.getMachineFunction().getFunction();
461 StringRef FuncName("<unknown>");
463 if (const ExternalSymbolSDNode *G = dyn_cast<ExternalSymbolSDNode>(Callee))
464 FuncName = G->getSymbol();
465 else if (const GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
466 FuncName = G->getGlobal()->getName();
468 DiagnosticInfoUnsupported NoCalls(Fn, "call to function " + FuncName);
469 DAG.getContext()->diagnose(NoCalls);
473 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
474 SelectionDAG &DAG) const {
475 switch (Op.getOpcode()) {
477 Op.getNode()->dump();
478 llvm_unreachable("Custom lowering code for this"
479 "instruction is not implemented yet!");
481 // AMDGPU DAG lowering.
482 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
483 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
484 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
485 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
486 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
487 case ISD::SDIV: return LowerSDIV(Op, DAG);
488 case ISD::SREM: return LowerSREM(Op, DAG);
489 case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
490 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG);
492 // AMDIL DAG lowering.
493 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
498 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
499 SmallVectorImpl<SDValue> &Results,
500 SelectionDAG &DAG) const {
501 switch (N->getOpcode()) {
502 case ISD::SIGN_EXTEND_INREG:
503 // Different parts of legalization seem to interpret which type of
504 // sign_extend_inreg is the one to check for custom lowering. The extended
505 // from type is what really matters, but some places check for custom
506 // lowering of the result type. This results in trying to use
507 // ReplaceNodeResults to sext_in_reg to an illegal type, so we'll just do
508 // nothing here and let the illegal result integer be handled normally.
511 SDValue Op = SDValue(N, 0);
513 EVT VT = Op.getValueType();
514 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
515 N->getOperand(0), N->getOperand(1));
516 Results.push_back(UDIVREM);
520 SDValue Op = SDValue(N, 0);
522 EVT VT = Op.getValueType();
523 SDValue UDIVREM = DAG.getNode(ISD::UDIVREM, DL, DAG.getVTList(VT, VT),
524 N->getOperand(0), N->getOperand(1));
525 Results.push_back(UDIVREM.getValue(1));
529 SDValue Op = SDValue(N, 0);
531 EVT VT = Op.getValueType();
532 EVT HalfVT = VT.getHalfSizedIntegerVT(*DAG.getContext());
534 SDValue one = DAG.getConstant(1, HalfVT);
535 SDValue zero = DAG.getConstant(0, HalfVT);
538 SDValue LHS = N->getOperand(0);
539 SDValue LHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, zero);
540 SDValue LHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, LHS, one);
542 SDValue RHS = N->getOperand(1);
543 SDValue RHS_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, zero);
544 SDValue RHS_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, RHS, one);
546 // Get Speculative values
547 SDValue DIV_Part = DAG.getNode(ISD::UDIV, DL, HalfVT, LHS_Hi, RHS_Lo);
548 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
550 SDValue REM_Hi = zero;
551 SDValue REM_Lo = DAG.getSelectCC(DL, RHS_Hi, zero, REM_Part, LHS_Hi, ISD::SETEQ);
553 SDValue DIV_Hi = DAG.getSelectCC(DL, RHS_Hi, zero, DIV_Part, zero, ISD::SETEQ);
554 SDValue DIV_Lo = zero;
556 const unsigned halfBitWidth = HalfVT.getSizeInBits();
558 for (unsigned i = 0; i < halfBitWidth; ++i) {
559 SDValue POS = DAG.getConstant(halfBitWidth - i - 1, HalfVT);
560 // Get Value of high bit
562 if (halfBitWidth == 32 && Subtarget->hasBFE()) {
563 HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
565 HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
566 HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
569 SDValue Carry = DAG.getNode(ISD::SRL, DL, HalfVT, REM_Lo,
570 DAG.getConstant(halfBitWidth - 1, HalfVT));
571 REM_Hi = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Hi, one);
572 REM_Hi = DAG.getNode(ISD::OR, DL, HalfVT, REM_Hi, Carry);
574 REM_Lo = DAG.getNode(ISD::SHL, DL, HalfVT, REM_Lo, one);
575 REM_Lo = DAG.getNode(ISD::OR, DL, HalfVT, REM_Lo, HBit);
578 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
580 SDValue BIT = DAG.getConstant(1 << (halfBitWidth - i - 1), HalfVT);
581 SDValue realBIT = DAG.getSelectCC(DL, REM, RHS, BIT, zero, ISD::SETGE);
583 DIV_Lo = DAG.getNode(ISD::OR, DL, HalfVT, DIV_Lo, realBIT);
587 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS);
589 REM = DAG.getSelectCC(DL, REM, RHS, REM_sub, REM, ISD::SETGE);
590 REM_Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, zero);
591 REM_Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, HalfVT, REM, one);
594 SDValue REM = DAG.getNode(ISD::BUILD_PAIR, DL, VT, REM_Lo, REM_Hi);
595 SDValue DIV = DAG.getNode(ISD::BUILD_PAIR, DL, VT, DIV_Lo, DIV_Hi);
596 Results.push_back(DIV);
597 Results.push_back(REM);
605 // FIXME: This implements accesses to initialized globals in the constant
606 // address space by copying them to private and accessing that. It does not
607 // properly handle illegal types or vectors. The private vector loads are not
608 // scalarized, and the illegal scalars hit an assertion. This technique will not
609 // work well with large initializers, and this should eventually be
610 // removed. Initialized globals should be placed into a data section that the
611 // runtime will load into a buffer before the kernel is executed. Uses of the
612 // global need to be replaced with a pointer loaded from an implicit kernel
613 // argument into this buffer holding the copy of the data, which will remove the
614 // need for any of this.
615 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
616 const GlobalValue *GV,
617 const SDValue &InitPtr,
619 SelectionDAG &DAG) const {
620 const DataLayout *TD = getTargetMachine().getDataLayout();
622 Type *InitTy = Init->getType();
624 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Init)) {
625 EVT VT = EVT::getEVT(InitTy);
626 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
627 return DAG.getStore(Chain, DL, DAG.getConstant(*CI, VT), InitPtr,
628 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
629 TD->getPrefTypeAlignment(InitTy));
632 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(Init)) {
633 EVT VT = EVT::getEVT(CFP->getType());
634 PointerType *PtrTy = PointerType::get(CFP->getType(), 0);
635 return DAG.getStore(Chain, DL, DAG.getConstantFP(*CFP, VT), InitPtr,
636 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
637 TD->getPrefTypeAlignment(CFP->getType()));
640 if (StructType *ST = dyn_cast<StructType>(InitTy)) {
641 const StructLayout *SL = TD->getStructLayout(ST);
643 EVT PtrVT = InitPtr.getValueType();
644 SmallVector<SDValue, 8> Chains;
646 for (unsigned I = 0, N = ST->getNumElements(); I != N; ++I) {
647 SDValue Offset = DAG.getConstant(SL->getElementOffset(I), PtrVT);
648 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
650 Constant *Elt = Init->getAggregateElement(I);
651 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
654 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
657 if (SequentialType *SeqTy = dyn_cast<SequentialType>(InitTy)) {
658 EVT PtrVT = InitPtr.getValueType();
660 unsigned NumElements;
661 if (ArrayType *AT = dyn_cast<ArrayType>(SeqTy))
662 NumElements = AT->getNumElements();
663 else if (VectorType *VT = dyn_cast<VectorType>(SeqTy))
664 NumElements = VT->getNumElements();
666 llvm_unreachable("Unexpected type");
668 unsigned EltSize = TD->getTypeAllocSize(SeqTy->getElementType());
669 SmallVector<SDValue, 8> Chains;
670 for (unsigned i = 0; i < NumElements; ++i) {
671 SDValue Offset = DAG.getConstant(i * EltSize, PtrVT);
672 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, InitPtr, Offset);
674 Constant *Elt = Init->getAggregateElement(i);
675 Chains.push_back(LowerConstantInitializer(Elt, GV, Ptr, Chain, DAG));
678 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
681 if (isa<UndefValue>(Init)) {
682 EVT VT = EVT::getEVT(InitTy);
683 PointerType *PtrTy = PointerType::get(InitTy, AMDGPUAS::PRIVATE_ADDRESS);
684 return DAG.getStore(Chain, DL, DAG.getUNDEF(VT), InitPtr,
685 MachinePointerInfo(UndefValue::get(PtrTy)), false, false,
686 TD->getPrefTypeAlignment(InitTy));
690 llvm_unreachable("Unhandled constant initializer");
693 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
695 SelectionDAG &DAG) const {
697 const DataLayout *TD = getTargetMachine().getDataLayout();
698 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Op);
699 const GlobalValue *GV = G->getGlobal();
701 switch (G->getAddressSpace()) {
702 default: llvm_unreachable("Global Address lowering not implemented for this "
704 case AMDGPUAS::LOCAL_ADDRESS: {
705 // XXX: What does the value of G->getOffset() mean?
706 assert(G->getOffset() == 0 &&
707 "Do not know what to do with an non-zero offset");
710 if (MFI->LocalMemoryObjects.count(GV) == 0) {
711 uint64_t Size = TD->getTypeAllocSize(GV->getType()->getElementType());
712 Offset = MFI->LDSSize;
713 MFI->LocalMemoryObjects[GV] = Offset;
714 // XXX: Account for alignment?
715 MFI->LDSSize += Size;
717 Offset = MFI->LocalMemoryObjects[GV];
720 return DAG.getConstant(Offset, getPointerTy(G->getAddressSpace()));
722 case AMDGPUAS::CONSTANT_ADDRESS: {
723 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
724 Type *EltType = GV->getType()->getElementType();
725 unsigned Size = TD->getTypeAllocSize(EltType);
726 unsigned Alignment = TD->getPrefTypeAlignment(EltType);
728 MVT PrivPtrVT = getPointerTy(AMDGPUAS::PRIVATE_ADDRESS);
729 MVT ConstPtrVT = getPointerTy(AMDGPUAS::CONSTANT_ADDRESS);
731 int FI = FrameInfo->CreateStackObject(Size, Alignment, false);
732 SDValue InitPtr = DAG.getFrameIndex(FI, PrivPtrVT);
734 const GlobalVariable *Var = cast<GlobalVariable>(GV);
735 if (!Var->hasInitializer()) {
736 // This has no use, but bugpoint will hit it.
737 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
740 const Constant *Init = Var->getInitializer();
741 SmallVector<SDNode*, 8> WorkList;
743 for (SDNode::use_iterator I = DAG.getEntryNode()->use_begin(),
744 E = DAG.getEntryNode()->use_end(); I != E; ++I) {
745 if (I->getOpcode() != AMDGPUISD::REGISTER_LOAD && I->getOpcode() != ISD::LOAD)
747 WorkList.push_back(*I);
749 SDValue Chain = LowerConstantInitializer(Init, GV, InitPtr, DAG.getEntryNode(), DAG);
750 for (SmallVector<SDNode*, 8>::iterator I = WorkList.begin(),
751 E = WorkList.end(); I != E; ++I) {
752 SmallVector<SDValue, 8> Ops;
753 Ops.push_back(Chain);
754 for (unsigned i = 1; i < (*I)->getNumOperands(); ++i) {
755 Ops.push_back((*I)->getOperand(i));
757 DAG.UpdateNodeOperands(*I, Ops);
759 return DAG.getZExtOrTrunc(InitPtr, SDLoc(Op), ConstPtrVT);
764 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
765 SelectionDAG &DAG) const {
766 SmallVector<SDValue, 8> Args;
767 SDValue A = Op.getOperand(0);
768 SDValue B = Op.getOperand(1);
770 DAG.ExtractVectorElements(A, Args);
771 DAG.ExtractVectorElements(B, Args);
773 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
776 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
777 SelectionDAG &DAG) const {
779 SmallVector<SDValue, 8> Args;
780 unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
781 EVT VT = Op.getValueType();
782 DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
783 VT.getVectorNumElements());
785 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(), Args);
788 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
789 SelectionDAG &DAG) const {
791 MachineFunction &MF = DAG.getMachineFunction();
792 const AMDGPUFrameLowering *TFL =
793 static_cast<const AMDGPUFrameLowering*>(getTargetMachine().getFrameLowering());
795 FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);
797 unsigned FrameIndex = FIN->getIndex();
798 unsigned Offset = TFL->getFrameIndexOffset(MF, FrameIndex);
799 return DAG.getConstant(Offset * 4 * TFL->getStackWidth(MF),
803 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
804 SelectionDAG &DAG) const {
805 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
807 EVT VT = Op.getValueType();
809 switch (IntrinsicID) {
811 case AMDGPUIntrinsic::AMDGPU_abs:
812 case AMDGPUIntrinsic::AMDIL_abs: // Legacy name.
813 return LowerIntrinsicIABS(Op, DAG);
814 case AMDGPUIntrinsic::AMDGPU_lrp:
815 return LowerIntrinsicLRP(Op, DAG);
816 case AMDGPUIntrinsic::AMDGPU_fract:
817 case AMDGPUIntrinsic::AMDIL_fraction: // Legacy name.
818 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
820 case AMDGPUIntrinsic::AMDGPU_clamp:
821 case AMDGPUIntrinsic::AMDIL_clamp: // Legacy name.
822 return DAG.getNode(AMDGPUISD::CLAMP, DL, VT,
823 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
825 case AMDGPUIntrinsic::AMDGPU_imax:
826 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
828 case AMDGPUIntrinsic::AMDGPU_umax:
829 return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
831 case AMDGPUIntrinsic::AMDGPU_imin:
832 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
834 case AMDGPUIntrinsic::AMDGPU_umin:
835 return DAG.getNode(AMDGPUISD::UMIN, DL, VT, Op.getOperand(1),
838 case AMDGPUIntrinsic::AMDGPU_umul24:
839 return DAG.getNode(AMDGPUISD::MUL_U24, DL, VT,
840 Op.getOperand(1), Op.getOperand(2));
842 case AMDGPUIntrinsic::AMDGPU_imul24:
843 return DAG.getNode(AMDGPUISD::MUL_I24, DL, VT,
844 Op.getOperand(1), Op.getOperand(2));
846 case AMDGPUIntrinsic::AMDGPU_umad24:
847 return DAG.getNode(AMDGPUISD::MAD_U24, DL, VT,
848 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
850 case AMDGPUIntrinsic::AMDGPU_imad24:
851 return DAG.getNode(AMDGPUISD::MAD_I24, DL, VT,
852 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
854 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte0:
855 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Op.getOperand(1));
857 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte1:
858 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE1, DL, VT, Op.getOperand(1));
860 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte2:
861 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE2, DL, VT, Op.getOperand(1));
863 case AMDGPUIntrinsic::AMDGPU_cvt_f32_ubyte3:
864 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE3, DL, VT, Op.getOperand(1));
866 case AMDGPUIntrinsic::AMDGPU_bfe_i32:
867 return DAG.getNode(AMDGPUISD::BFE_I32, DL, VT,
872 case AMDGPUIntrinsic::AMDGPU_bfe_u32:
873 return DAG.getNode(AMDGPUISD::BFE_U32, DL, VT,
878 case AMDGPUIntrinsic::AMDGPU_bfi:
879 return DAG.getNode(AMDGPUISD::BFI, DL, VT,
884 case AMDGPUIntrinsic::AMDGPU_bfm:
885 return DAG.getNode(AMDGPUISD::BFM, DL, VT,
889 case AMDGPUIntrinsic::AMDIL_exp: // Legacy name.
890 return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
892 case AMDGPUIntrinsic::AMDIL_round_nearest: // Legacy name.
893 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
897 ///IABS(a) = SMAX(sub(0, a), a)
898 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
899 SelectionDAG &DAG) const {
901 EVT VT = Op.getValueType();
902 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
905 return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
908 /// Linear Interpolation
909 /// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
910 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
911 SelectionDAG &DAG) const {
913 EVT VT = Op.getValueType();
914 SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
915 DAG.getConstantFP(1.0f, MVT::f32),
917 SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
919 return DAG.getNode(ISD::FADD, DL, VT,
920 DAG.getNode(ISD::FMUL, DL, VT, Op.getOperand(1), Op.getOperand(2)),
924 /// \brief Generate Min/Max node
925 SDValue AMDGPUTargetLowering::CombineMinMax(SDNode *N,
926 SelectionDAG &DAG) const {
928 EVT VT = N->getValueType(0);
930 SDValue LHS = N->getOperand(0);
931 SDValue RHS = N->getOperand(1);
932 SDValue True = N->getOperand(2);
933 SDValue False = N->getOperand(3);
934 SDValue CC = N->getOperand(4);
936 if (VT != MVT::f32 ||
937 !((LHS == True && RHS == False) || (LHS == False && RHS == True))) {
941 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get();
955 llvm_unreachable("Operation should already be optimised!");
962 unsigned Opc = (LHS == True) ? AMDGPUISD::FMIN : AMDGPUISD::FMAX;
963 return DAG.getNode(Opc, DL, VT, LHS, RHS);
971 unsigned Opc = (LHS == True) ? AMDGPUISD::FMAX : AMDGPUISD::FMIN;
972 return DAG.getNode(Opc, DL, VT, LHS, RHS);
974 case ISD::SETCC_INVALID:
975 llvm_unreachable("Invalid setcc condcode!");
980 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue &Op,
981 SelectionDAG &DAG) const {
982 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op);
983 EVT MemEltVT = Load->getMemoryVT().getVectorElementType();
984 EVT EltVT = Op.getValueType().getVectorElementType();
985 EVT PtrVT = Load->getBasePtr().getValueType();
986 unsigned NumElts = Load->getMemoryVT().getVectorNumElements();
987 SmallVector<SDValue, 8> Loads;
990 for (unsigned i = 0, e = NumElts; i != e; ++i) {
991 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT, Load->getBasePtr(),
992 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8), PtrVT));
993 Loads.push_back(DAG.getExtLoad(Load->getExtensionType(), SL, EltVT,
994 Load->getChain(), Ptr,
995 MachinePointerInfo(Load->getMemOperand()->getValue()),
996 MemEltVT, Load->isVolatile(), Load->isNonTemporal(),
997 Load->getAlignment()));
999 return DAG.getNode(ISD::BUILD_VECTOR, SL, Op.getValueType(), Loads);
1002 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1003 SelectionDAG &DAG) const {
1004 StoreSDNode *Store = cast<StoreSDNode>(Op);
1005 EVT MemVT = Store->getMemoryVT();
1006 unsigned MemBits = MemVT.getSizeInBits();
1008 // Byte stores are really expensive, so if possible, try to pack 32-bit vector
1009 // truncating store into an i32 store.
1010 // XXX: We could also handle optimize other vector bitwidths.
1011 if (!MemVT.isVector() || MemBits > 32) {
1016 SDValue Value = Store->getValue();
1017 EVT VT = Value.getValueType();
1018 EVT ElemVT = VT.getVectorElementType();
1019 SDValue Ptr = Store->getBasePtr();
1020 EVT MemEltVT = MemVT.getVectorElementType();
1021 unsigned MemEltBits = MemEltVT.getSizeInBits();
1022 unsigned MemNumElements = MemVT.getVectorNumElements();
1023 unsigned PackedSize = MemVT.getStoreSizeInBits();
1024 SDValue Mask = DAG.getConstant((1 << MemEltBits) - 1, MVT::i32);
1026 assert(Value.getValueType().getScalarSizeInBits() >= 32);
1028 SDValue PackedValue;
1029 for (unsigned i = 0; i < MemNumElements; ++i) {
1030 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ElemVT, Value,
1031 DAG.getConstant(i, MVT::i32));
1032 Elt = DAG.getZExtOrTrunc(Elt, DL, MVT::i32);
1033 Elt = DAG.getNode(ISD::AND, DL, MVT::i32, Elt, Mask); // getZeroExtendInReg
1035 SDValue Shift = DAG.getConstant(MemEltBits * i, MVT::i32);
1036 Elt = DAG.getNode(ISD::SHL, DL, MVT::i32, Elt, Shift);
1041 PackedValue = DAG.getNode(ISD::OR, DL, MVT::i32, PackedValue, Elt);
1045 if (PackedSize < 32) {
1046 EVT PackedVT = EVT::getIntegerVT(*DAG.getContext(), PackedSize);
1047 return DAG.getTruncStore(Store->getChain(), DL, PackedValue, Ptr,
1048 Store->getMemOperand()->getPointerInfo(),
1050 Store->isNonTemporal(), Store->isVolatile(),
1051 Store->getAlignment());
1054 return DAG.getStore(Store->getChain(), DL, PackedValue, Ptr,
1055 Store->getMemOperand()->getPointerInfo(),
1056 Store->isVolatile(), Store->isNonTemporal(),
1057 Store->getAlignment());
1060 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1061 SelectionDAG &DAG) const {
1062 StoreSDNode *Store = cast<StoreSDNode>(Op);
1063 EVT MemEltVT = Store->getMemoryVT().getVectorElementType();
1064 EVT EltVT = Store->getValue().getValueType().getVectorElementType();
1065 EVT PtrVT = Store->getBasePtr().getValueType();
1066 unsigned NumElts = Store->getMemoryVT().getVectorNumElements();
1069 SmallVector<SDValue, 8> Chains;
1071 for (unsigned i = 0, e = NumElts; i != e; ++i) {
1072 SDValue Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, EltVT,
1073 Store->getValue(), DAG.getConstant(i, MVT::i32));
1074 SDValue Ptr = DAG.getNode(ISD::ADD, SL, PtrVT,
1075 Store->getBasePtr(),
1076 DAG.getConstant(i * (MemEltVT.getSizeInBits() / 8),
1078 Chains.push_back(DAG.getTruncStore(Store->getChain(), SL, Val, Ptr,
1079 MachinePointerInfo(Store->getMemOperand()->getValue()),
1080 MemEltVT, Store->isVolatile(), Store->isNonTemporal(),
1081 Store->getAlignment()));
1083 return DAG.getNode(ISD::TokenFactor, SL, MVT::Other, Chains);
1086 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1088 LoadSDNode *Load = cast<LoadSDNode>(Op);
1089 ISD::LoadExtType ExtType = Load->getExtensionType();
1090 EVT VT = Op.getValueType();
1091 EVT MemVT = Load->getMemoryVT();
1093 if (ExtType != ISD::NON_EXTLOAD && !VT.isVector() && VT.getSizeInBits() > 32) {
1094 // We can do the extload to 32-bits, and then need to separately extend to
1097 SDValue ExtLoad32 = DAG.getExtLoad(ExtType, DL, MVT::i32,
1101 Load->getMemOperand());
1102 return DAG.getNode(ISD::getExtForLoadExtType(ExtType), DL, VT, ExtLoad32);
1105 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1106 assert(VT == MVT::i1 && "Only i1 non-extloads expected");
1107 // FIXME: Copied from PPC
1108 // First, load into 32 bits, then truncate to 1 bit.
1110 SDValue Chain = Load->getChain();
1111 SDValue BasePtr = Load->getBasePtr();
1112 MachineMemOperand *MMO = Load->getMemOperand();
1114 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
1115 BasePtr, MVT::i8, MMO);
1116 return DAG.getNode(ISD::TRUNCATE, DL, VT, NewLD);
1119 // Lower loads constant address space global variable loads
1120 if (Load->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
1121 isa<GlobalVariable>(
1122 GetUnderlyingObject(Load->getMemOperand()->getValue()))) {
1124 SDValue Ptr = DAG.getZExtOrTrunc(Load->getBasePtr(), DL,
1125 getPointerTy(AMDGPUAS::PRIVATE_ADDRESS));
1126 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr,
1127 DAG.getConstant(2, MVT::i32));
1128 return DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1129 Load->getChain(), Ptr,
1130 DAG.getTargetConstant(0, MVT::i32), Op.getOperand(2));
1133 if (Load->getAddressSpace() != AMDGPUAS::PRIVATE_ADDRESS ||
1134 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1138 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Load->getBasePtr(),
1139 DAG.getConstant(2, MVT::i32));
1140 SDValue Ret = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, Op.getValueType(),
1141 Load->getChain(), Ptr,
1142 DAG.getTargetConstant(0, MVT::i32),
1144 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32,
1146 DAG.getConstant(0x3, MVT::i32));
1147 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1148 DAG.getConstant(3, MVT::i32));
1150 Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Ret, ShiftAmt);
1152 EVT MemEltVT = MemVT.getScalarType();
1153 if (ExtType == ISD::SEXTLOAD) {
1154 SDValue MemEltVTNode = DAG.getValueType(MemEltVT);
1155 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode);
1158 return DAG.getZeroExtendInReg(Ret, DL, MemEltVT);
1161 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1163 SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);
1164 if (Result.getNode()) {
1168 StoreSDNode *Store = cast<StoreSDNode>(Op);
1169 SDValue Chain = Store->getChain();
1170 if ((Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1171 Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) &&
1172 Store->getValue().getValueType().isVector()) {
1173 return SplitVectorStore(Op, DAG);
1176 EVT MemVT = Store->getMemoryVT();
1177 if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS &&
1178 MemVT.bitsLT(MVT::i32)) {
1180 if (Store->getMemoryVT() == MVT::i8) {
1182 } else if (Store->getMemoryVT() == MVT::i16) {
1185 SDValue BasePtr = Store->getBasePtr();
1186 SDValue Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, BasePtr,
1187 DAG.getConstant(2, MVT::i32));
1188 SDValue Dst = DAG.getNode(AMDGPUISD::REGISTER_LOAD, DL, MVT::i32,
1189 Chain, Ptr, DAG.getTargetConstant(0, MVT::i32));
1191 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, BasePtr,
1192 DAG.getConstant(0x3, MVT::i32));
1194 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx,
1195 DAG.getConstant(3, MVT::i32));
1197 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32,
1200 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT);
1202 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32,
1203 MaskedValue, ShiftAmt);
1205 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, DAG.getConstant(Mask, MVT::i32),
1207 DstMask = DAG.getNode(ISD::XOR, DL, MVT::i32, DstMask,
1208 DAG.getConstant(0xffffffff, MVT::i32));
1209 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask);
1211 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue);
1212 return DAG.getNode(AMDGPUISD::REGISTER_STORE, DL, MVT::Other,
1213 Chain, Value, Ptr, DAG.getTargetConstant(0, MVT::i32));
1218 SDValue AMDGPUTargetLowering::LowerSDIV24(SDValue Op, SelectionDAG &DAG) const {
1220 EVT OVT = Op.getValueType();
1221 SDValue LHS = Op.getOperand(0);
1222 SDValue RHS = Op.getOperand(1);
1225 if (!OVT.isVector()) {
1228 } else if (OVT.getVectorNumElements() == 2) {
1231 } else if (OVT.getVectorNumElements() == 4) {
1235 unsigned bitsize = OVT.getScalarType().getSizeInBits();
1236 // char|short jq = ia ^ ib;
1237 SDValue jq = DAG.getNode(ISD::XOR, DL, OVT, LHS, RHS);
1239 // jq = jq >> (bitsize - 2)
1240 jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));
1243 jq = DAG.getNode(ISD::OR, DL, OVT, jq, DAG.getConstant(1, OVT));
1246 jq = DAG.getSExtOrTrunc(jq, DL, INTTY);
1248 // int ia = (int)LHS;
1249 SDValue ia = DAG.getSExtOrTrunc(LHS, DL, INTTY);
1251 // int ib, (int)RHS;
1252 SDValue ib = DAG.getSExtOrTrunc(RHS, DL, INTTY);
1254 // float fa = (float)ia;
1255 SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);
1257 // float fb = (float)ib;
1258 SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);
1260 // float fq = native_divide(fa, fb);
1261 SDValue fq = DAG.getNode(AMDGPUISD::DIV_INF, DL, FLTTY, fa, fb);
1264 fq = DAG.getNode(ISD::FTRUNC, DL, FLTTY, fq);
1266 // float fqneg = -fq;
1267 SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq);
1269 // float fr = mad(fqneg, fb, fa);
1270 SDValue fr = DAG.getNode(ISD::FADD, DL, FLTTY,
1271 DAG.getNode(ISD::MUL, DL, FLTTY, fqneg, fb), fa);
1273 // int iq = (int)fq;
1274 SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);
1277 fr = DAG.getNode(ISD::FABS, DL, FLTTY, fr);
1280 fb = DAG.getNode(ISD::FABS, DL, FLTTY, fb);
1282 // int cv = fr >= fb;
1284 if (INTTY == MVT::i32) {
1285 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
1287 cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);
1289 // jq = (cv ? jq : 0);
1290 jq = DAG.getNode(ISD::SELECT, DL, OVT, cv, jq,
1291 DAG.getConstant(0, OVT));
1293 iq = DAG.getSExtOrTrunc(iq, DL, OVT);
1294 iq = DAG.getNode(ISD::ADD, DL, OVT, iq, jq);
1298 SDValue AMDGPUTargetLowering::LowerSDIV32(SDValue Op, SelectionDAG &DAG) const {
1300 EVT OVT = Op.getValueType();
1301 SDValue LHS = Op.getOperand(0);
1302 SDValue RHS = Op.getOperand(1);
1303 // The LowerSDIV32 function generates equivalent to the following IL.
1313 // ixor r10, r10, r11
1315 // ixor DST, r0, r10
1324 SDValue r10 = DAG.getSelectCC(DL,
1325 r0, DAG.getConstant(0, OVT),
1326 DAG.getConstant(-1, OVT),
1327 DAG.getConstant(0, OVT),
1331 SDValue r11 = DAG.getSelectCC(DL,
1332 r1, DAG.getConstant(0, OVT),
1333 DAG.getConstant(-1, OVT),
1334 DAG.getConstant(0, OVT),
1338 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1341 r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
1344 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1347 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
1350 r0 = DAG.getNode(ISD::UDIV, DL, OVT, r0, r1);
1352 // ixor r10, r10, r11
1353 r10 = DAG.getNode(ISD::XOR, DL, OVT, r10, r11);
1356 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1358 // ixor DST, r0, r10
1359 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1363 SDValue AMDGPUTargetLowering::LowerSDIV64(SDValue Op, SelectionDAG &DAG) const {
1364 return SDValue(Op.getNode(), 0);
1367 SDValue AMDGPUTargetLowering::LowerSDIV(SDValue Op, SelectionDAG &DAG) const {
1368 EVT OVT = Op.getValueType().getScalarType();
1370 if (OVT == MVT::i64)
1371 return LowerSDIV64(Op, DAG);
1373 if (OVT.getScalarType() == MVT::i32)
1374 return LowerSDIV32(Op, DAG);
1376 if (OVT == MVT::i16 || OVT == MVT::i8) {
1377 // FIXME: We should be checking for the masked bits. This isn't reached
1378 // because i8 and i16 are not legal types.
1379 return LowerSDIV24(Op, DAG);
1382 return SDValue(Op.getNode(), 0);
1385 SDValue AMDGPUTargetLowering::LowerSREM32(SDValue Op, SelectionDAG &DAG) const {
1387 EVT OVT = Op.getValueType();
1388 SDValue LHS = Op.getOperand(0);
1389 SDValue RHS = Op.getOperand(1);
1390 // The LowerSREM32 function generates equivalent to the following IL.
1400 // umul r20, r20, r1
1403 // ixor DST, r0, r10
1412 SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT);
1415 SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT);
1418 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1421 r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);
1424 r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1427 r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);
1430 SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1);
1432 // umul r20, r20, r1
1433 r20 = DAG.getNode(AMDGPUISD::UMUL, DL, OVT, r20, r1);
1436 r0 = DAG.getNode(ISD::SUB, DL, OVT, r0, r20);
1439 r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);
1441 // ixor DST, r0, r10
1442 SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);
1446 SDValue AMDGPUTargetLowering::LowerSREM64(SDValue Op, SelectionDAG &DAG) const {
1447 return SDValue(Op.getNode(), 0);
1450 SDValue AMDGPUTargetLowering::LowerSREM(SDValue Op, SelectionDAG &DAG) const {
1451 EVT OVT = Op.getValueType();
1453 if (OVT.getScalarType() == MVT::i64)
1454 return LowerSREM64(Op, DAG);
1456 if (OVT.getScalarType() == MVT::i32)
1457 return LowerSREM32(Op, DAG);
1459 return SDValue(Op.getNode(), 0);
1462 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1463 SelectionDAG &DAG) const {
1465 EVT VT = Op.getValueType();
1467 SDValue Num = Op.getOperand(0);
1468 SDValue Den = Op.getOperand(1);
1470 // RCP = URECIP(Den) = 2^32 / Den + e
1471 // e is rounding error.
1472 SDValue RCP = DAG.getNode(AMDGPUISD::URECIP, DL, VT, Den);
1474 // RCP_LO = umulo(RCP, Den) */
1475 SDValue RCP_LO = DAG.getNode(ISD::UMULO, DL, VT, RCP, Den);
1477 // RCP_HI = mulhu (RCP, Den) */
1478 SDValue RCP_HI = DAG.getNode(ISD::MULHU, DL, VT, RCP, Den);
1480 // NEG_RCP_LO = -RCP_LO
1481 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
1484 // ABS_RCP_LO = (RCP_HI == 0 ? NEG_RCP_LO : RCP_LO)
1485 SDValue ABS_RCP_LO = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1488 // Calculate the rounding error from the URECIP instruction
1489 // E = mulhu(ABS_RCP_LO, RCP)
1490 SDValue E = DAG.getNode(ISD::MULHU, DL, VT, ABS_RCP_LO, RCP);
1492 // RCP_A_E = RCP + E
1493 SDValue RCP_A_E = DAG.getNode(ISD::ADD, DL, VT, RCP, E);
1495 // RCP_S_E = RCP - E
1496 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E);
1498 // Tmp0 = (RCP_HI == 0 ? RCP_A_E : RCP_SUB_E)
1499 SDValue Tmp0 = DAG.getSelectCC(DL, RCP_HI, DAG.getConstant(0, VT),
1502 // Quotient = mulhu(Tmp0, Num)
1503 SDValue Quotient = DAG.getNode(ISD::MULHU, DL, VT, Tmp0, Num);
1505 // Num_S_Remainder = Quotient * Den
1506 SDValue Num_S_Remainder = DAG.getNode(ISD::UMULO, DL, VT, Quotient, Den);
1508 // Remainder = Num - Num_S_Remainder
1509 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder);
1511 // Remainder_GE_Den = (Remainder >= Den ? -1 : 0)
1512 SDValue Remainder_GE_Den = DAG.getSelectCC(DL, Remainder, Den,
1513 DAG.getConstant(-1, VT),
1514 DAG.getConstant(0, VT),
1516 // Remainder_GE_Zero = (Num >= Num_S_Remainder ? -1 : 0)
1517 SDValue Remainder_GE_Zero = DAG.getSelectCC(DL, Num,
1519 DAG.getConstant(-1, VT),
1520 DAG.getConstant(0, VT),
1522 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
1523 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den,
1526 // Calculate Division result:
1528 // Quotient_A_One = Quotient + 1
1529 SDValue Quotient_A_One = DAG.getNode(ISD::ADD, DL, VT, Quotient,
1530 DAG.getConstant(1, VT));
1532 // Quotient_S_One = Quotient - 1
1533 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient,
1534 DAG.getConstant(1, VT));
1536 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
1537 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1538 Quotient, Quotient_A_One, ISD::SETEQ);
1540 // Div = (Remainder_GE_Zero == 0 ? Quotient_S_One : Div)
1541 Div = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1542 Quotient_S_One, Div, ISD::SETEQ);
1544 // Calculate Rem result:
1546 // Remainder_S_Den = Remainder - Den
1547 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den);
1549 // Remainder_A_Den = Remainder + Den
1550 SDValue Remainder_A_Den = DAG.getNode(ISD::ADD, DL, VT, Remainder, Den);
1552 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
1553 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
1554 Remainder, Remainder_S_Den, ISD::SETEQ);
1556 // Rem = (Remainder_GE_Zero == 0 ? Remainder_A_Den : Rem)
1557 Rem = DAG.getSelectCC(DL, Remainder_GE_Zero, DAG.getConstant(0, VT),
1558 Remainder_A_Den, Rem, ISD::SETEQ);
1563 return DAG.getMergeValues(Ops, DL);
1566 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
1567 SelectionDAG &DAG) const {
1568 SDValue S0 = Op.getOperand(0);
1570 if (Op.getValueType() != MVT::f32 || S0.getValueType() != MVT::i64)
1573 // f32 uint_to_fp i64
1574 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1575 DAG.getConstant(0, MVT::i32));
1576 SDValue FloatLo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Lo);
1577 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, S0,
1578 DAG.getConstant(1, MVT::i32));
1579 SDValue FloatHi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, Hi);
1580 FloatHi = DAG.getNode(ISD::FMUL, DL, MVT::f32, FloatHi,
1581 DAG.getConstantFP(4294967296.0f, MVT::f32)); // 2^32
1582 return DAG.getNode(ISD::FADD, DL, MVT::f32, FloatLo, FloatHi);
1585 SDValue AMDGPUTargetLowering::ExpandSIGN_EXTEND_INREG(SDValue Op,
1587 SelectionDAG &DAG) const {
1588 MVT VT = Op.getSimpleValueType();
1590 SDValue Shift = DAG.getConstant(BitsDiff, VT);
1591 // Shift left by 'Shift' bits.
1592 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Op.getOperand(0), Shift);
1593 // Signed shift Right by 'Shift' bits.
1594 return DAG.getNode(ISD::SRA, DL, VT, Shl, Shift);
1597 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
1598 SelectionDAG &DAG) const {
1599 EVT ExtraVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
1600 MVT VT = Op.getSimpleValueType();
1601 MVT ScalarVT = VT.getScalarType();
1606 SDValue Src = Op.getOperand(0);
1609 // TODO: Don't scalarize on Evergreen?
1610 unsigned NElts = VT.getVectorNumElements();
1611 SmallVector<SDValue, 8> Args;
1612 DAG.ExtractVectorElements(Src, Args, 0, NElts);
1614 SDValue VTOp = DAG.getValueType(ExtraVT.getScalarType());
1615 for (unsigned I = 0; I < NElts; ++I)
1616 Args[I] = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, ScalarVT, Args[I], VTOp);
1618 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Args);
1621 //===----------------------------------------------------------------------===//
1622 // Custom DAG optimizations
1623 //===----------------------------------------------------------------------===//
1625 static bool isU24(SDValue Op, SelectionDAG &DAG) {
1626 APInt KnownZero, KnownOne;
1627 EVT VT = Op.getValueType();
1628 DAG.computeKnownBits(Op, KnownZero, KnownOne);
1630 return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
1633 static bool isI24(SDValue Op, SelectionDAG &DAG) {
1634 EVT VT = Op.getValueType();
1636 // In order for this to be a signed 24-bit value, bit 23, must
1638 return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
1639 // as unsigned 24-bit values.
1640 (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
1643 static void simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
1645 SelectionDAG &DAG = DCI.DAG;
1646 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1647 EVT VT = Op.getValueType();
1649 APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
1650 APInt KnownZero, KnownOne;
1651 TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
1652 if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO))
1653 DCI.CommitTargetLoweringOpt(TLO);
1656 template <typename IntTy>
1657 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0,
1658 uint32_t Offset, uint32_t Width) {
1659 if (Width + Offset < 32) {
1660 IntTy Result = (Src0 << (32 - Offset - Width)) >> (32 - Width);
1661 return DAG.getConstant(Result, MVT::i32);
1664 return DAG.getConstant(Src0 >> Offset, MVT::i32);
1667 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
1668 DAGCombinerInfo &DCI) const {
1669 SelectionDAG &DAG = DCI.DAG;
1672 switch(N->getOpcode()) {
1675 EVT VT = N->getValueType(0);
1676 SDValue N0 = N->getOperand(0);
1677 SDValue N1 = N->getOperand(1);
1680 // FIXME: Add support for 24-bit multiply with 64-bit output on SI.
1681 if (VT.isVector() || VT.getSizeInBits() > 32)
1684 if (Subtarget->hasMulU24() && isU24(N0, DAG) && isU24(N1, DAG)) {
1685 N0 = DAG.getZExtOrTrunc(N0, DL, MVT::i32);
1686 N1 = DAG.getZExtOrTrunc(N1, DL, MVT::i32);
1687 Mul = DAG.getNode(AMDGPUISD::MUL_U24, DL, MVT::i32, N0, N1);
1688 } else if (Subtarget->hasMulI24() && isI24(N0, DAG) && isI24(N1, DAG)) {
1689 N0 = DAG.getSExtOrTrunc(N0, DL, MVT::i32);
1690 N1 = DAG.getSExtOrTrunc(N1, DL, MVT::i32);
1691 Mul = DAG.getNode(AMDGPUISD::MUL_I24, DL, MVT::i32, N0, N1);
1696 // We need to use sext even for MUL_U24, because MUL_U24 is used
1697 // for signed multiply of 8 and 16-bit types.
1698 SDValue Reg = DAG.getSExtOrTrunc(Mul, DL, VT);
1702 case AMDGPUISD::MUL_I24:
1703 case AMDGPUISD::MUL_U24: {
1704 SDValue N0 = N->getOperand(0);
1705 SDValue N1 = N->getOperand(1);
1706 simplifyI24(N0, DCI);
1707 simplifyI24(N1, DCI);
1710 case ISD::SELECT_CC: {
1711 return CombineMinMax(N, DAG);
1713 case AMDGPUISD::BFE_I32:
1714 case AMDGPUISD::BFE_U32: {
1715 assert(!N->getValueType(0).isVector() &&
1716 "Vector handling of BFE not implemented");
1717 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
1721 uint32_t WidthVal = Width->getZExtValue() & 0x1f;
1723 return DAG.getConstant(0, MVT::i32);
1725 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
1729 SDValue BitsFrom = N->getOperand(0);
1730 uint32_t OffsetVal = Offset->getZExtValue() & 0x1f;
1732 bool Signed = N->getOpcode() == AMDGPUISD::BFE_I32;
1734 if (OffsetVal == 0) {
1735 // This is already sign / zero extended, so try to fold away extra BFEs.
1736 unsigned SignBits = Signed ? (32 - WidthVal + 1) : (32 - WidthVal);
1738 unsigned OpSignBits = DAG.ComputeNumSignBits(BitsFrom);
1739 if (OpSignBits >= SignBits)
1742 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal);
1744 // This is a sign_extend_inreg. Replace it to take advantage of existing
1745 // DAG Combines. If not eliminated, we will match back to BFE during
1748 // TODO: The sext_inreg of extended types ends, although we can could
1749 // handle them in a single BFE.
1750 return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, BitsFrom,
1751 DAG.getValueType(SmallVT));
1754 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
1757 if (ConstantSDNode *Val = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
1759 return constantFoldBFE<int32_t>(DAG,
1760 Val->getSExtValue(),
1765 return constantFoldBFE<uint32_t>(DAG,
1766 Val->getZExtValue(),
1771 APInt Demanded = APInt::getBitsSet(32,
1773 OffsetVal + WidthVal);
1775 if ((OffsetVal + WidthVal) >= 32) {
1776 SDValue ShiftVal = DAG.getConstant(OffsetVal, MVT::i32);
1777 return DAG.getNode(Signed ? ISD::SRA : ISD::SRL, DL, MVT::i32,
1778 BitsFrom, ShiftVal);
1781 APInt KnownZero, KnownOne;
1782 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1783 !DCI.isBeforeLegalizeOps());
1784 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1785 if (TLO.ShrinkDemandedConstant(BitsFrom, Demanded) ||
1786 TLI.SimplifyDemandedBits(BitsFrom, Demanded, KnownZero, KnownOne, TLO)) {
1787 DCI.CommitTargetLoweringOpt(TLO);
1796 //===----------------------------------------------------------------------===//
1798 //===----------------------------------------------------------------------===//
1800 void AMDGPUTargetLowering::getOriginalFunctionArgs(
1803 const SmallVectorImpl<ISD::InputArg> &Ins,
1804 SmallVectorImpl<ISD::InputArg> &OrigIns) const {
1806 for (unsigned i = 0, e = Ins.size(); i < e; ++i) {
1807 if (Ins[i].ArgVT == Ins[i].VT) {
1808 OrigIns.push_back(Ins[i]);
1813 if (Ins[i].ArgVT.isVector() && !Ins[i].VT.isVector()) {
1814 // Vector has been split into scalars.
1815 VT = Ins[i].ArgVT.getVectorElementType();
1816 } else if (Ins[i].VT.isVector() && Ins[i].ArgVT.isVector() &&
1817 Ins[i].ArgVT.getVectorElementType() !=
1818 Ins[i].VT.getVectorElementType()) {
1819 // Vector elements have been promoted
1822 // Vector has been spilt into smaller vectors.
1826 ISD::InputArg Arg(Ins[i].Flags, VT, VT, Ins[i].Used,
1827 Ins[i].OrigArgIndex, Ins[i].PartOffset);
1828 OrigIns.push_back(Arg);
1832 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {
1833 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
1834 return CFP->isExactlyValue(1.0);
1836 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
1837 return C->isAllOnesValue();
1842 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {
1843 if (ConstantFPSDNode * CFP = dyn_cast<ConstantFPSDNode>(Op)) {
1844 return CFP->getValueAPF().isZero();
1846 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
1847 return C->isNullValue();
1852 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
1853 const TargetRegisterClass *RC,
1854 unsigned Reg, EVT VT) const {
1855 MachineFunction &MF = DAG.getMachineFunction();
1856 MachineRegisterInfo &MRI = MF.getRegInfo();
1857 unsigned VirtualRegister;
1858 if (!MRI.isLiveIn(Reg)) {
1859 VirtualRegister = MRI.createVirtualRegister(RC);
1860 MRI.addLiveIn(Reg, VirtualRegister);
1862 VirtualRegister = MRI.getLiveInVirtReg(Reg);
1864 return DAG.getRegister(VirtualRegister, VT);
1867 #define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
1869 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
1871 default: return nullptr;
1873 NODE_NAME_CASE(CALL);
1874 NODE_NAME_CASE(UMUL);
1875 NODE_NAME_CASE(DIV_INF);
1876 NODE_NAME_CASE(RET_FLAG);
1877 NODE_NAME_CASE(BRANCH_COND);
1880 NODE_NAME_CASE(DWORDADDR)
1881 NODE_NAME_CASE(FRACT)
1882 NODE_NAME_CASE(CLAMP)
1883 NODE_NAME_CASE(FMAX)
1884 NODE_NAME_CASE(SMAX)
1885 NODE_NAME_CASE(UMAX)
1886 NODE_NAME_CASE(FMIN)
1887 NODE_NAME_CASE(SMIN)
1888 NODE_NAME_CASE(UMIN)
1889 NODE_NAME_CASE(BFE_U32)
1890 NODE_NAME_CASE(BFE_I32)
1893 NODE_NAME_CASE(MUL_U24)
1894 NODE_NAME_CASE(MUL_I24)
1895 NODE_NAME_CASE(MAD_U24)
1896 NODE_NAME_CASE(MAD_I24)
1897 NODE_NAME_CASE(URECIP)
1898 NODE_NAME_CASE(DOT4)
1899 NODE_NAME_CASE(EXPORT)
1900 NODE_NAME_CASE(CONST_ADDRESS)
1901 NODE_NAME_CASE(REGISTER_LOAD)
1902 NODE_NAME_CASE(REGISTER_STORE)
1903 NODE_NAME_CASE(LOAD_CONSTANT)
1904 NODE_NAME_CASE(LOAD_INPUT)
1905 NODE_NAME_CASE(SAMPLE)
1906 NODE_NAME_CASE(SAMPLEB)
1907 NODE_NAME_CASE(SAMPLED)
1908 NODE_NAME_CASE(SAMPLEL)
1909 NODE_NAME_CASE(CVT_F32_UBYTE0)
1910 NODE_NAME_CASE(CVT_F32_UBYTE1)
1911 NODE_NAME_CASE(CVT_F32_UBYTE2)
1912 NODE_NAME_CASE(CVT_F32_UBYTE3)
1913 NODE_NAME_CASE(STORE_MSKOR)
1914 NODE_NAME_CASE(TBUFFER_STORE_FORMAT)
1918 static void computeKnownBitsForMinMax(const SDValue Op0,
1922 const SelectionDAG &DAG,
1924 APInt Op0Zero, Op0One;
1925 APInt Op1Zero, Op1One;
1926 DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
1927 DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
1929 KnownZero = Op0Zero & Op1Zero;
1930 KnownOne = Op0One & Op1One;
1933 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
1937 const SelectionDAG &DAG,
1938 unsigned Depth) const {
1940 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0); // Don't know anything.
1944 unsigned Opc = Op.getOpcode();
1949 case ISD::INTRINSIC_WO_CHAIN: {
1950 // FIXME: The intrinsic should just use the node.
1951 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
1952 case AMDGPUIntrinsic::AMDGPU_imax:
1953 case AMDGPUIntrinsic::AMDGPU_umax:
1954 case AMDGPUIntrinsic::AMDGPU_imin:
1955 case AMDGPUIntrinsic::AMDGPU_umin:
1956 computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
1957 KnownZero, KnownOne, DAG, Depth);
1965 case AMDGPUISD::SMAX:
1966 case AMDGPUISD::UMAX:
1967 case AMDGPUISD::SMIN:
1968 case AMDGPUISD::UMIN:
1969 computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
1970 KnownZero, KnownOne, DAG, Depth);
1973 case AMDGPUISD::BFE_I32:
1974 case AMDGPUISD::BFE_U32: {
1975 ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
1979 unsigned BitWidth = 32;
1980 uint32_t Width = CWidth->getZExtValue() & 0x1f;
1982 KnownZero = APInt::getAllOnesValue(BitWidth);
1983 KnownOne = APInt::getNullValue(BitWidth);
1987 // FIXME: This could do a lot more. If offset is 0, should be the same as
1988 // sign_extend_inreg implementation, but that involves duplicating it.
1989 if (Opc == AMDGPUISD::BFE_I32)
1990 KnownOne = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
1992 KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
1999 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
2001 const SelectionDAG &DAG,
2002 unsigned Depth) const {
2003 switch (Op.getOpcode()) {
2004 case AMDGPUISD::BFE_I32: {
2005 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2009 unsigned SignBits = 32 - Width->getZExtValue() + 1;
2010 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(Op.getOperand(1));
2011 if (!Offset || !Offset->isNullValue())
2014 // TODO: Could probably figure something out with non-0 offsets.
2015 unsigned Op0SignBits = DAG.ComputeNumSignBits(Op.getOperand(0), Depth + 1);
2016 return std::max(SignBits, Op0SignBits);
2019 case AMDGPUISD::BFE_U32: {
2020 ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
2021 return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;