1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition of the TargetLowering class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
27 class AMDGPUTargetLowering : public TargetLowering {
29 const AMDGPUSubtarget *Subtarget;
32 SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33 const SDValue &InitPtr,
35 SelectionDAG &DAG) const;
36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40 /// \brief Lower vector stores by merging the vector elements into an integer
41 /// of the same bitwidth.
42 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
43 /// \brief Split a vector store into multiple scalar stores.
44 /// \returns The resulting chain.
46 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
51 SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
55 SDValue ExpandSIGN_EXTEND_INREG(SDValue Op,
57 SelectionDAG &DAG) const;
58 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
60 SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
61 SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
64 static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
65 static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
67 virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
68 SelectionDAG &DAG) const;
70 /// \brief Split a vector load into a scalar load of each component.
71 SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const;
73 /// \brief Split a vector load into 2 loads of half the vector.
74 SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
76 /// \brief Split a vector store into a scalar store of each component.
77 SDValue ScalarizeVectorStore(SDValue Op, SelectionDAG &DAG) const;
79 /// \brief Split a vector store into 2 stores of half the vector.
80 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
82 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
84 SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
85 SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
86 bool isHWTrueValue(SDValue Op) const;
87 bool isHWFalseValue(SDValue Op) const;
89 /// The SelectionDAGBuilder will automatically promote function arguments
90 /// with illegal types. However, this does not work for the AMDGPU targets
91 /// since the function arguments are stored in memory as these illegal types.
92 /// In order to handle this properly we need to get the origianl types sizes
93 /// from the LLVM IR Function and fixup the ISD:InputArg values before
94 /// passing them to AnalyzeFormalArguments()
95 void getOriginalFunctionArgs(SelectionDAG &DAG,
97 const SmallVectorImpl<ISD::InputArg> &Ins,
98 SmallVectorImpl<ISD::InputArg> &OrigIns) const;
99 void AnalyzeFormalArguments(CCState &State,
100 const SmallVectorImpl<ISD::InputArg> &Ins) const;
103 AMDGPUTargetLowering(TargetMachine &TM);
105 bool isFAbsFree(EVT VT) const override;
106 bool isFNegFree(EVT VT) const override;
107 bool isTruncateFree(EVT Src, EVT Dest) const override;
108 bool isTruncateFree(Type *Src, Type *Dest) const override;
110 bool isZExtFree(Type *Src, Type *Dest) const override;
111 bool isZExtFree(EVT Src, EVT Dest) const override;
112 bool isZExtFree(SDValue Val, EVT VT2) const override;
114 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
116 MVT getVectorIdxTy() const override;
117 bool isSelectSupported(SelectSupportKind) const override;
119 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
120 bool ShouldShrinkFPConstant(EVT VT) const override;
122 bool isLoadBitCastBeneficial(EVT, EVT) const override;
123 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
125 const SmallVectorImpl<ISD::OutputArg> &Outs,
126 const SmallVectorImpl<SDValue> &OutVals,
127 SDLoc DL, SelectionDAG &DAG) const override;
128 SDValue LowerCall(CallLoweringInfo &CLI,
129 SmallVectorImpl<SDValue> &InVals) const override;
131 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
132 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
133 void ReplaceNodeResults(SDNode * N,
134 SmallVectorImpl<SDValue> &Results,
135 SelectionDAG &DAG) const override;
137 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
139 SDValue CombineMinMax(SDNode *N, SelectionDAG &DAG) const;
140 const char* getTargetNodeName(unsigned Opcode) const override;
142 virtual SDNode *PostISelFolding(MachineSDNode *N,
143 SelectionDAG &DAG) const {
147 /// \brief Determine which of the bits specified in \p Mask are known to be
148 /// either zero or one and return them in the \p KnownZero and \p KnownOne
150 void computeKnownBitsForTargetNode(const SDValue Op,
153 const SelectionDAG &DAG,
154 unsigned Depth = 0) const override;
156 virtual unsigned ComputeNumSignBitsForTargetNode(
158 const SelectionDAG &DAG,
159 unsigned Depth = 0) const override;
161 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
164 /// \returns a RegisterSDNode representing Reg.
165 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
166 const TargetRegisterClass *RC,
167 unsigned Reg, EVT VT) const;
170 namespace AMDGPUISD {
174 FIRST_NUMBER = ISD::BUILTIN_OP_END,
175 CALL, // Function call based on a single integer
176 UMUL, // 32bit unsigned multiplication
179 // End AMDIL ISD Opcodes
184 // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
185 // Denormals handled on some parts.
198 TRIG_PREOP, // 1 ULP max error for f64
200 // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
201 // For f64, max error 2^29 ULP, handles denormals.
207 BFE_U32, // Extract range of bits with zero extension to 32-bits.
208 BFE_I32, // Extract range of bits with sign extension to 32-bits.
209 BFI, // (src0 & src1) | (~src0 & src2)
210 BFM, // Insert a range of bits into a 32-bit word.
211 BREV, // Reverse bits.
227 // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
232 /// This node is for VLIW targets and it is used to represent a vector
233 /// that is stored in consecutive registers with the same channel.
240 BUILD_VERTICAL_VECTOR,
241 /// Pointer to the start of the shader's constant data.
243 FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
246 TBUFFER_STORE_FORMAT,
247 LAST_AMDGPU_ISD_NUMBER
251 } // End namespace AMDGPUISD
253 } // End namespace llvm