1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition of the TargetLowering class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef AMDGPUISELLOWERING_H
17 #define AMDGPUISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
23 class AMDGPUMachineFunction;
24 class MachineRegisterInfo;
26 class AMDGPUTargetLowering : public TargetLowering {
28 void ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
29 SmallVectorImpl<SDValue> &Args,
30 unsigned Start, unsigned Count) const;
31 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
32 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
33 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
34 /// \brief Lower vector stores by merging the vector elements into an integer
35 /// of the same bitwidth.
36 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
37 /// \brief Split a vector store into multiple scalar stores.
38 /// \returns The resulting chain.
39 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
40 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
44 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
47 /// \returns a RegisterSDNode representing Reg.
48 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
49 const TargetRegisterClass *RC,
50 unsigned Reg, EVT VT) const;
51 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
52 SelectionDAG &DAG) const;
53 /// \brief Split a vector load into multiple scalar loads.
54 SDValue SplitVectorLoad(const SDValue &Op, SelectionDAG &DAG) const;
55 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
57 bool isHWTrueValue(SDValue Op) const;
58 bool isHWFalseValue(SDValue Op) const;
60 /// The SelectionDAGBuilder will automatically promote function arguments
61 /// with illegal types. However, this does not work for the AMDGPU targets
62 /// since the function arguments are stored in memory as these illegal types.
63 /// In order to handle this properly we need to get the origianl types sizes
64 /// from the LLVM IR Function and fixup the ISD:InputArg values before
65 /// passing them to AnalyzeFormalArguments()
66 void getOriginalFunctionArgs(SelectionDAG &DAG,
68 const SmallVectorImpl<ISD::InputArg> &Ins,
69 SmallVectorImpl<ISD::InputArg> &OrigIns) const;
70 void AnalyzeFormalArguments(CCState &State,
71 const SmallVectorImpl<ISD::InputArg> &Ins) const;
74 AMDGPUTargetLowering(TargetMachine &TM);
76 virtual bool isFAbsFree(EVT VT) const;
77 virtual bool isFNegFree(EVT VT) const;
78 virtual MVT getVectorIdxTy() const;
79 virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
81 const SmallVectorImpl<ISD::OutputArg> &Outs,
82 const SmallVectorImpl<SDValue> &OutVals,
83 SDLoc DL, SelectionDAG &DAG) const;
84 virtual SDValue LowerCall(CallLoweringInfo &CLI,
85 SmallVectorImpl<SDValue> &InVals) const {
87 llvm_unreachable("Undefined function");
90 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
94 virtual const char* getTargetNodeName(unsigned Opcode) const;
96 virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const {
100 // Functions defined in AMDILISelLowering.cpp
103 /// \brief Determine which of the bits specified in \p Mask are known to be
104 /// either zero or one and return them in the \p KnownZero and \p KnownOne
106 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
109 const SelectionDAG &DAG,
110 unsigned Depth = 0) const;
112 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
113 const CallInst &I, unsigned Intrinsic) const;
115 /// We want to mark f32/f64 floating point values as legal.
116 bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
118 /// We don't want to shrink f64/f32 constants.
119 bool ShouldShrinkFPConstant(EVT VT) const;
122 void InitAMDILLowering();
123 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
126 SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
127 SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
129 SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
130 SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
131 SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
132 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
133 EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
134 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
138 namespace AMDGPUISD {
142 FIRST_NUMBER = ISD::BUILTIN_OP_END,
143 CALL, // Function call based on a single integer
144 UMUL, // 32bit unsigned multiplication
145 DIV_INF, // Divide with infinity returned on zero divisor
148 // End AMDIL ISD Opcodes
171 FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
174 TBUFFER_STORE_FORMAT,
175 LAST_AMDGPU_ISD_NUMBER
179 } // End namespace AMDGPUISD
181 } // End namespace llvm
183 #endif // AMDGPUISELLOWERING_H