1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition of the TargetLowering class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef AMDGPUISELLOWERING_H
17 #define AMDGPUISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
23 class AMDGPUMachineFunction;
24 class MachineRegisterInfo;
26 class AMDGPUTargetLowering : public TargetLowering {
28 void ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
29 SmallVectorImpl<SDValue> &Args,
30 unsigned Start, unsigned Count) const;
31 SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
32 const SDValue &InitPtr,
34 SelectionDAG &DAG) const;
35 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
39 /// \brief Lower vector stores by merging the vector elements into an integer
40 /// of the same bitwidth.
41 SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
42 /// \brief Split a vector store into multiple scalar stores.
43 /// \returns The resulting chain.
44 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
45 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
49 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
52 /// \returns a RegisterSDNode representing Reg.
53 virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
54 const TargetRegisterClass *RC,
55 unsigned Reg, EVT VT) const;
56 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
57 SelectionDAG &DAG) const;
58 /// \brief Split a vector load into multiple scalar loads.
59 SDValue SplitVectorLoad(const SDValue &Op, SelectionDAG &DAG) const;
60 SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
61 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
62 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
63 bool isHWTrueValue(SDValue Op) const;
64 bool isHWFalseValue(SDValue Op) const;
66 /// The SelectionDAGBuilder will automatically promote function arguments
67 /// with illegal types. However, this does not work for the AMDGPU targets
68 /// since the function arguments are stored in memory as these illegal types.
69 /// In order to handle this properly we need to get the origianl types sizes
70 /// from the LLVM IR Function and fixup the ISD:InputArg values before
71 /// passing them to AnalyzeFormalArguments()
72 void getOriginalFunctionArgs(SelectionDAG &DAG,
74 const SmallVectorImpl<ISD::InputArg> &Ins,
75 SmallVectorImpl<ISD::InputArg> &OrigIns) const;
76 void AnalyzeFormalArguments(CCState &State,
77 const SmallVectorImpl<ISD::InputArg> &Ins) const;
80 AMDGPUTargetLowering(TargetMachine &TM);
82 virtual bool isFAbsFree(EVT VT) const LLVM_OVERRIDE;
83 virtual bool isFNegFree(EVT VT) const LLVM_OVERRIDE;
84 virtual bool isTruncateFree(EVT Src, EVT Dest) const LLVM_OVERRIDE;
85 virtual bool isTruncateFree(Type *Src, Type *Dest) const LLVM_OVERRIDE;
86 virtual MVT getVectorIdxTy() const LLVM_OVERRIDE;
87 virtual bool isLoadBitCastBeneficial(EVT, EVT) const LLVM_OVERRIDE;
88 virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
90 const SmallVectorImpl<ISD::OutputArg> &Outs,
91 const SmallVectorImpl<SDValue> &OutVals,
92 SDLoc DL, SelectionDAG &DAG) const;
93 virtual SDValue LowerCall(CallLoweringInfo &CLI,
94 SmallVectorImpl<SDValue> &InVals) const {
96 llvm_unreachable("Undefined function");
99 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
100 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
101 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
102 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
103 virtual const char* getTargetNodeName(unsigned Opcode) const;
105 virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const {
109 // Functions defined in AMDILISelLowering.cpp
112 /// \brief Determine which of the bits specified in \p Mask are known to be
113 /// either zero or one and return them in the \p KnownZero and \p KnownOne
115 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
118 const SelectionDAG &DAG,
119 unsigned Depth = 0) const;
121 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
122 const CallInst &I, unsigned Intrinsic) const;
124 /// We want to mark f32/f64 floating point values as legal.
125 bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
127 /// We don't want to shrink f64/f32 constants.
128 bool ShouldShrinkFPConstant(EVT VT) const;
131 void InitAMDILLowering();
132 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
133 SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
134 SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
135 SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
136 SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
137 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
138 SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
139 SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
140 SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
141 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
142 EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
143 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
144 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
147 namespace AMDGPUISD {
151 FIRST_NUMBER = ISD::BUILTIN_OP_END,
152 CALL, // Function call based on a single integer
153 UMUL, // 32bit unsigned multiplication
154 DIV_INF, // Divide with infinity returned on zero divisor
157 // End AMDIL ISD Opcodes
180 FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
183 TBUFFER_STORE_FORMAT,
184 LAST_AMDGPU_ISD_NUMBER
188 } // End namespace AMDGPUISD
190 } // End namespace llvm
192 #endif // AMDGPUISELLOWERING_H