1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition of the TargetLowering class that is common
14 //===----------------------------------------------------------------------===//
16 #ifndef AMDGPUISELLOWERING_H
17 #define AMDGPUISELLOWERING_H
19 #include "llvm/Target/TargetLowering.h"
23 class MachineRegisterInfo;
25 class AMDGPUTargetLowering : public TargetLowering {
27 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
28 SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
32 /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
35 /// \returns a RegisterSDNode representing Reg.
36 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
37 unsigned Reg, EVT VT) const;
39 bool isHWTrueValue(SDValue Op) const;
40 bool isHWFalseValue(SDValue Op) const;
43 AMDGPUTargetLowering(TargetMachine &TM);
45 virtual SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
47 const SmallVectorImpl<ISD::InputArg> &Ins,
48 DebugLoc DL, SelectionDAG &DAG,
49 SmallVectorImpl<SDValue> &InVals) const;
51 virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
53 const SmallVectorImpl<ISD::OutputArg> &Outs,
54 const SmallVectorImpl<SDValue> &OutVals,
55 DebugLoc DL, SelectionDAG &DAG) const;
57 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
59 SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
60 SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
61 virtual const char* getTargetNodeName(unsigned Opcode) const;
63 // Functions defined in AMDILISelLowering.cpp
66 /// \brief Determine which of the bits specified in \p Mask are known to be
67 /// either zero or one and return them in the \p KnownZero and \p KnownOne
69 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
72 const SelectionDAG &DAG,
73 unsigned Depth = 0) const;
75 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
76 const CallInst &I, unsigned Intrinsic) const;
78 /// We want to mark f32/f64 floating point values as legal.
79 bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
81 /// We don't want to shrink f64/f32 constants.
82 bool ShouldShrinkFPConstant(EVT VT) const;
85 void InitAMDILLowering();
86 SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
94 SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
95 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
96 EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
97 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
98 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
101 namespace AMDGPUISD {
105 FIRST_NUMBER = ISD::BUILTIN_OP_END,
106 MAD, // 32bit Fused Multiply Add instruction
107 CALL, // Function call based on a single integer
108 UMUL, // 32bit unsigned multiplication
109 DIV_INF, // Divide with infinity returned on zero divisor
112 // End AMDIL ISD Opcodes
126 LAST_AMDGPU_ISD_NUMBER
130 } // End namespace AMDGPUISD
135 SI_FIRST = AMDGPUISD::LAST_AMDGPU_ISD_NUMBER,
140 } // End namespace SIISD
142 } // End namespace llvm
144 #endif // AMDGPUISELLOWERING_H